1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8mm.dtsi" 9 10/ { 11 model = "FSL i.MX8MM EVK board"; 12 compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; 13 14 chosen { 15 stdout-path = &uart2; 16 }; 17 18 leds { 19 compatible = "gpio-leds"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_led>; 22 23 status { 24 label = "status"; 25 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 26 default-state = "on"; 27 }; 28 }; 29 30 reg_usdhc2_vmmc: regulator-usdhc2 { 31 compatible = "regulator-fixed"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 34 regulator-name = "VSD_3V3"; 35 regulator-min-microvolt = <3300000>; 36 regulator-max-microvolt = <3300000>; 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 38 enable-active-high; 39 }; 40}; 41 42&A53_0 { 43 cpu-supply = <&buck2_reg>; 44}; 45 46&fec1 { 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_fec1>; 49 phy-mode = "rgmii-id"; 50 phy-handle = <ðphy0>; 51 fsl,magic-packet; 52 status = "okay"; 53 54 mdio { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 ethphy0: ethernet-phy@0 { 59 compatible = "ethernet-phy-ieee802.3-c22"; 60 reg = <0>; 61 at803x,led-act-blind-workaround; 62 at803x,eee-okay; 63 at803x,vddio-1p8v; 64 }; 65 }; 66}; 67 68&snvs_pwrkey { 69 status = "okay"; 70}; 71 72&uart2 { /* console */ 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_uart2>; 75 status = "okay"; 76}; 77 78&usdhc2 { 79 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 80 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 81 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 82 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 83 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 84 bus-width = <4>; 85 vmmc-supply = <®_usdhc2_vmmc>; 86 status = "okay"; 87}; 88 89&usdhc3 { 90 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 91 pinctrl-0 = <&pinctrl_usdhc3>; 92 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 93 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 94 bus-width = <8>; 95 non-removable; 96 status = "okay"; 97}; 98 99&wdog1 { 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_wdog>; 102 fsl,ext-reset-output; 103 status = "okay"; 104}; 105 106&i2c1 { 107 clock-frequency = <400000>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_i2c1>; 110 status = "okay"; 111 112 pmic@4b { 113 compatible = "rohm,bd71847"; 114 reg = <0x4b>; 115 pinctrl-0 = <&pinctrl_pmic>; 116 interrupt-parent = <&gpio1>; 117 interrupts = <3 GPIO_ACTIVE_LOW>; 118 rohm,reset-snvs-powered; 119 120 regulators { 121 buck1_reg: BUCK1 { 122 regulator-name = "BUCK1"; 123 regulator-min-microvolt = <700000>; 124 regulator-max-microvolt = <1300000>; 125 regulator-boot-on; 126 regulator-always-on; 127 regulator-ramp-delay = <1250>; 128 }; 129 130 buck2_reg: BUCK2 { 131 regulator-name = "BUCK2"; 132 regulator-min-microvolt = <700000>; 133 regulator-max-microvolt = <1300000>; 134 regulator-boot-on; 135 regulator-always-on; 136 regulator-ramp-delay = <1250>; 137 rohm,dvs-run-voltage = <1000000>; 138 rohm,dvs-idle-voltage = <900000>; 139 }; 140 141 buck3_reg: BUCK3 { 142 // BUCK5 in datasheet 143 regulator-name = "BUCK3"; 144 regulator-min-microvolt = <700000>; 145 regulator-max-microvolt = <1350000>; 146 regulator-boot-on; 147 regulator-always-on; 148 }; 149 150 buck4_reg: BUCK4 { 151 // BUCK6 in datasheet 152 regulator-name = "BUCK4"; 153 regulator-min-microvolt = <3000000>; 154 regulator-max-microvolt = <3300000>; 155 regulator-boot-on; 156 regulator-always-on; 157 }; 158 159 buck5_reg: BUCK5 { 160 // BUCK7 in datasheet 161 regulator-name = "BUCK5"; 162 regulator-min-microvolt = <1605000>; 163 regulator-max-microvolt = <1995000>; 164 regulator-boot-on; 165 regulator-always-on; 166 }; 167 168 buck6_reg: BUCK6 { 169 // BUCK8 in datasheet 170 regulator-name = "BUCK6"; 171 regulator-min-microvolt = <800000>; 172 regulator-max-microvolt = <1400000>; 173 regulator-boot-on; 174 regulator-always-on; 175 }; 176 177 ldo1_reg: LDO1 { 178 regulator-name = "LDO1"; 179 regulator-min-microvolt = <3000000>; 180 regulator-max-microvolt = <3300000>; 181 regulator-boot-on; 182 regulator-always-on; 183 }; 184 185 ldo2_reg: LDO2 { 186 regulator-name = "LDO2"; 187 regulator-min-microvolt = <900000>; 188 regulator-max-microvolt = <900000>; 189 regulator-boot-on; 190 regulator-always-on; 191 }; 192 193 ldo3_reg: LDO3 { 194 regulator-name = "LDO3"; 195 regulator-min-microvolt = <1800000>; 196 regulator-max-microvolt = <3300000>; 197 regulator-boot-on; 198 regulator-always-on; 199 }; 200 201 ldo4_reg: LDO4 { 202 regulator-name = "LDO4"; 203 regulator-min-microvolt = <900000>; 204 regulator-max-microvolt = <1800000>; 205 regulator-boot-on; 206 regulator-always-on; 207 }; 208 209 ldo6_reg: LDO6 { 210 regulator-name = "LDO6"; 211 regulator-min-microvolt = <900000>; 212 regulator-max-microvolt = <1800000>; 213 regulator-boot-on; 214 regulator-always-on; 215 }; 216 }; 217 }; 218}; 219 220&iomuxc { 221 pinctrl-names = "default"; 222 223 pinctrl_fec1: fec1grp { 224 fsl,pins = < 225 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 226 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 227 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 228 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 229 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 230 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 231 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 232 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 233 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 234 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 235 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 236 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 237 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 238 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 239 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 240 >; 241 }; 242 243 pinctrl_gpio_led: gpioledgrp { 244 fsl,pins = < 245 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 246 >; 247 }; 248 249 pinctrl_i2c1: i2c1grp { 250 fsl,pins = < 251 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 252 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 253 >; 254 }; 255 256 pinctrl_pmic: pmicirq { 257 fsl,pins = < 258 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 259 >; 260 }; 261 262 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { 263 fsl,pins = < 264 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 265 >; 266 }; 267 268 pinctrl_uart2: uart2grp { 269 fsl,pins = < 270 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 271 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 272 >; 273 }; 274 275 pinctrl_usdhc2_gpio: usdhc2grpgpio { 276 fsl,pins = < 277 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 278 >; 279 }; 280 281 pinctrl_usdhc2: usdhc2grp { 282 fsl,pins = < 283 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 284 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 285 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 286 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 287 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 288 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 289 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 290 >; 291 }; 292 293 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 294 fsl,pins = < 295 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 296 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 297 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 298 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 299 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 300 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 301 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 302 >; 303 }; 304 305 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 306 fsl,pins = < 307 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 308 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 309 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 310 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 311 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 312 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 313 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 314 >; 315 }; 316 317 pinctrl_usdhc3: usdhc3grp { 318 fsl,pins = < 319 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 320 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 321 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 322 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 323 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 324 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 325 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 326 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 327 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 328 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 329 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 330 >; 331 }; 332 333 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 334 fsl,pins = < 335 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 336 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 337 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 338 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 339 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 340 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 341 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 342 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 343 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 344 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 345 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 346 >; 347 }; 348 349 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 350 fsl,pins = < 351 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 352 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 353 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 354 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 355 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 356 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 357 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 358 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 359 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 360 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 361 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 362 >; 363 }; 364 365 pinctrl_wdog: wdoggrp { 366 fsl,pins = < 367 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 368 >; 369 }; 370}; 371