1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12	model = "FSL i.MX8MM EVK board";
13	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14
15	chosen {
16		stdout-path = &uart2;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x0 0x40000000 0 0x80000000>;
22	};
23
24	leds {
25		compatible = "gpio-leds";
26		pinctrl-names = "default";
27		pinctrl-0 = <&pinctrl_gpio_led>;
28
29		status {
30			label = "status";
31			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
32			default-state = "on";
33		};
34	};
35
36	reg_usdhc2_vmmc: regulator-usdhc2 {
37		compatible = "regulator-fixed";
38		pinctrl-names = "default";
39		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
40		regulator-name = "VSD_3V3";
41		regulator-min-microvolt = <3300000>;
42		regulator-max-microvolt = <3300000>;
43		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
44		enable-active-high;
45	};
46
47	wm8524: audio-codec {
48		#sound-dai-cells = <0>;
49		compatible = "wlf,wm8524";
50		pinctrl-names = "default";
51		pinctrl-0 = <&pinctrl_gpio_wlf>;
52		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
53	};
54
55	sound-wm8524 {
56		compatible = "simple-audio-card";
57		simple-audio-card,name = "wm8524-audio";
58		simple-audio-card,format = "i2s";
59		simple-audio-card,frame-master = <&cpudai>;
60		simple-audio-card,bitclock-master = <&cpudai>;
61		simple-audio-card,widgets =
62			"Line", "Left Line Out Jack",
63			"Line", "Right Line Out Jack";
64		simple-audio-card,routing =
65			"Left Line Out Jack", "LINEVOUTL",
66			"Right Line Out Jack", "LINEVOUTR";
67
68		cpudai: simple-audio-card,cpu {
69			sound-dai = <&sai3>;
70			dai-tdm-slot-num = <2>;
71			dai-tdm-slot-width = <32>;
72		};
73
74		simple-audio-card,codec {
75			sound-dai = <&wm8524>;
76			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
77		};
78	};
79};
80
81&A53_0 {
82	cpu-supply = <&buck2_reg>;
83};
84
85&A53_1 {
86	cpu-supply = <&buck2_reg>;
87};
88
89&A53_2 {
90	cpu-supply = <&buck2_reg>;
91};
92
93&A53_3 {
94	cpu-supply = <&buck2_reg>;
95};
96
97&ddrc {
98	operating-points-v2 = <&ddrc_opp_table>;
99
100	ddrc_opp_table: opp-table {
101		compatible = "operating-points-v2";
102
103		opp-25M {
104			opp-hz = /bits/ 64 <25000000>;
105		};
106
107		opp-100M {
108			opp-hz = /bits/ 64 <100000000>;
109		};
110
111		opp-750M {
112			opp-hz = /bits/ 64 <750000000>;
113		};
114	};
115};
116
117&fec1 {
118	pinctrl-names = "default";
119	pinctrl-0 = <&pinctrl_fec1>;
120	phy-mode = "rgmii-id";
121	phy-handle = <&ethphy0>;
122	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
123	phy-reset-duration = <10>;
124	fsl,magic-packet;
125	status = "okay";
126
127	mdio {
128		#address-cells = <1>;
129		#size-cells = <0>;
130
131		ethphy0: ethernet-phy@0 {
132			compatible = "ethernet-phy-ieee802.3-c22";
133			reg = <0>;
134		};
135	};
136};
137
138&i2c1 {
139	clock-frequency = <400000>;
140	pinctrl-names = "default";
141	pinctrl-0 = <&pinctrl_i2c1>;
142	status = "okay";
143
144	pmic@4b {
145		compatible = "rohm,bd71847";
146		reg = <0x4b>;
147		pinctrl-0 = <&pinctrl_pmic>;
148		interrupt-parent = <&gpio1>;
149		interrupts = <3 GPIO_ACTIVE_LOW>;
150		rohm,reset-snvs-powered;
151
152		regulators {
153			buck1_reg: BUCK1 {
154				regulator-name = "BUCK1";
155				regulator-min-microvolt = <700000>;
156				regulator-max-microvolt = <1300000>;
157				regulator-boot-on;
158				regulator-always-on;
159				regulator-ramp-delay = <1250>;
160			};
161
162			buck2_reg: BUCK2 {
163				regulator-name = "BUCK2";
164				regulator-min-microvolt = <700000>;
165				regulator-max-microvolt = <1300000>;
166				regulator-boot-on;
167				regulator-always-on;
168				regulator-ramp-delay = <1250>;
169				rohm,dvs-run-voltage = <1000000>;
170				rohm,dvs-idle-voltage = <900000>;
171			};
172
173			buck3_reg: BUCK3 {
174				// BUCK5 in datasheet
175				regulator-name = "BUCK3";
176				regulator-min-microvolt = <700000>;
177				regulator-max-microvolt = <1350000>;
178				regulator-boot-on;
179				regulator-always-on;
180			};
181
182			buck4_reg: BUCK4 {
183				// BUCK6 in datasheet
184				regulator-name = "BUCK4";
185				regulator-min-microvolt = <3000000>;
186				regulator-max-microvolt = <3300000>;
187				regulator-boot-on;
188				regulator-always-on;
189			};
190
191			buck5_reg: BUCK5 {
192				// BUCK7 in datasheet
193				regulator-name = "BUCK5";
194				regulator-min-microvolt = <1605000>;
195				regulator-max-microvolt = <1995000>;
196				regulator-boot-on;
197				regulator-always-on;
198			};
199
200			buck6_reg: BUCK6 {
201				// BUCK8 in datasheet
202				regulator-name = "BUCK6";
203				regulator-min-microvolt = <800000>;
204				regulator-max-microvolt = <1400000>;
205				regulator-boot-on;
206				regulator-always-on;
207			};
208
209			ldo1_reg: LDO1 {
210				regulator-name = "LDO1";
211				regulator-min-microvolt = <1600000>;
212				regulator-max-microvolt = <3300000>;
213				regulator-boot-on;
214				regulator-always-on;
215			};
216
217			ldo2_reg: LDO2 {
218				regulator-name = "LDO2";
219				regulator-min-microvolt = <800000>;
220				regulator-max-microvolt = <900000>;
221				regulator-boot-on;
222				regulator-always-on;
223			};
224
225			ldo3_reg: LDO3 {
226				regulator-name = "LDO3";
227				regulator-min-microvolt = <1800000>;
228				regulator-max-microvolt = <3300000>;
229				regulator-boot-on;
230				regulator-always-on;
231			};
232
233			ldo4_reg: LDO4 {
234				regulator-name = "LDO4";
235				regulator-min-microvolt = <900000>;
236				regulator-max-microvolt = <1800000>;
237				regulator-boot-on;
238				regulator-always-on;
239			};
240
241			ldo6_reg: LDO6 {
242				regulator-name = "LDO6";
243				regulator-min-microvolt = <900000>;
244				regulator-max-microvolt = <1800000>;
245				regulator-boot-on;
246				regulator-always-on;
247			};
248		};
249	};
250};
251
252&i2c2 {
253	clock-frequency = <400000>;
254	pinctrl-names = "default";
255	pinctrl-0 = <&pinctrl_i2c2>;
256	status = "okay";
257
258	ptn5110: tcpc@50 {
259		compatible = "nxp,ptn5110";
260		pinctrl-names = "default";
261		pinctrl-0 = <&pinctrl_typec1>;
262		reg = <0x50>;
263		interrupt-parent = <&gpio2>;
264		interrupts = <11 8>;
265		status = "okay";
266
267		port {
268			typec1_dr_sw: endpoint {
269				remote-endpoint = <&usb1_drd_sw>;
270			};
271		};
272
273		typec1_con: connector {
274			compatible = "usb-c-connector";
275			label = "USB-C";
276			power-role = "dual";
277			data-role = "dual";
278			try-power-role = "sink";
279			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
280			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
281				     PDO_VAR(5000, 20000, 3000)>;
282			op-sink-microwatt = <15000000>;
283			self-powered;
284		};
285	};
286};
287
288&i2c3 {
289	clock-frequency = <400000>;
290	pinctrl-names = "default";
291	pinctrl-0 = <&pinctrl_i2c3>;
292	status = "okay";
293
294	pca6416: gpio@20 {
295		compatible = "ti,tca6416";
296		reg = <0x20>;
297		gpio-controller;
298		#gpio-cells = <2>;
299	};
300};
301
302&sai3 {
303	pinctrl-names = "default";
304	pinctrl-0 = <&pinctrl_sai3>;
305	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
306	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
307	assigned-clock-rates = <24576000>;
308	status = "okay";
309};
310
311&snvs_pwrkey {
312	status = "okay";
313};
314
315&uart2 { /* console */
316	pinctrl-names = "default";
317	pinctrl-0 = <&pinctrl_uart2>;
318	status = "okay";
319};
320
321&usbotg1 {
322	dr_mode = "otg";
323	hnp-disable;
324	srp-disable;
325	adp-disable;
326	usb-role-switch;
327	samsung,picophy-pre-emp-curr-control = <3>;
328	samsung,picophy-dc-vol-level-adjust = <7>;
329	status = "okay";
330
331	port {
332		usb1_drd_sw: endpoint {
333			remote-endpoint = <&typec1_dr_sw>;
334		};
335	};
336};
337
338&usdhc2 {
339	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
340	assigned-clock-rates = <200000000>;
341	pinctrl-names = "default", "state_100mhz", "state_200mhz";
342	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
343	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
344	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
345	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
346	bus-width = <4>;
347	vmmc-supply = <&reg_usdhc2_vmmc>;
348	status = "okay";
349};
350
351&usdhc3 {
352	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
353	assigned-clock-rates = <400000000>;
354	pinctrl-names = "default", "state_100mhz", "state_200mhz";
355	pinctrl-0 = <&pinctrl_usdhc3>;
356	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
357	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
358	bus-width = <8>;
359	non-removable;
360	status = "okay";
361};
362
363&wdog1 {
364	pinctrl-names = "default";
365	pinctrl-0 = <&pinctrl_wdog>;
366	fsl,ext-reset-output;
367	status = "okay";
368};
369
370&iomuxc {
371	pinctrl-names = "default";
372
373	pinctrl_fec1: fec1grp {
374		fsl,pins = <
375			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
376			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
377			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
378			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
379			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
380			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
381			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
382			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
383			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
384			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
385			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
386			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
387			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
388			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
389			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
390		>;
391	};
392
393	pinctrl_gpio_led: gpioledgrp {
394		fsl,pins = <
395			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
396		>;
397	};
398
399	pinctrl_gpio_wlf: gpiowlfgrp {
400		fsl,pins = <
401			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
402		>;
403	};
404
405	pinctrl_i2c1: i2c1grp {
406		fsl,pins = <
407			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
408			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
409		>;
410	};
411
412	pinctrl_i2c2: i2c2grp {
413		fsl,pins = <
414			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
415			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
416		>;
417	};
418
419	pinctrl_i2c3: i2c3grp {
420		fsl,pins = <
421			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
422			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
423		>;
424	};
425
426	pinctrl_pmic: pmicirq {
427		fsl,pins = <
428			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
429		>;
430	};
431
432	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
433		fsl,pins = <
434			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
435		>;
436	};
437
438	pinctrl_sai3: sai3grp {
439		fsl,pins = <
440			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
441			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
442			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
443			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
444		>;
445	};
446
447	pinctrl_typec1: typec1grp {
448		fsl,pins = <
449			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
450		>;
451	};
452
453	pinctrl_uart2: uart2grp {
454		fsl,pins = <
455			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
456			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
457		>;
458	};
459
460	pinctrl_usdhc2_gpio: usdhc2grpgpio {
461		fsl,pins = <
462			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
463		>;
464	};
465
466	pinctrl_usdhc2: usdhc2grp {
467		fsl,pins = <
468			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
469			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
470			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
471			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
472			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
473			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
474			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
475		>;
476	};
477
478	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
479		fsl,pins = <
480			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
481			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
482			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
483			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
484			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
485			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
486			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
487		>;
488	};
489
490	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
491		fsl,pins = <
492			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
493			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
494			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
495			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
496			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
497			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
498			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
499		>;
500	};
501
502	pinctrl_usdhc3: usdhc3grp {
503		fsl,pins = <
504			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
505			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
506			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
507			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
508			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
509			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
510			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
511			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
512			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
513			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
514			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
515		>;
516	};
517
518	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
519		fsl,pins = <
520			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
521			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
522			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
523			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
524			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
525			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
526			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
527			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
528			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
529			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
530			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
531		>;
532	};
533
534	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
535		fsl,pins = <
536			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
537			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
538			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
539			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
540			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
541			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
542			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
543			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
544			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
545			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
546			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
547		>;
548	};
549
550	pinctrl_wdog: wdoggrp {
551		fsl,pins = <
552			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
553		>;
554	};
555};
556