1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx8mm.dtsi" 10 11/ { 12 model = "FSL i.MX8MM EVK board"; 13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x0 0x40000000 0 0x80000000>; 22 }; 23 24 leds { 25 compatible = "gpio-leds"; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_gpio_led>; 28 29 status { 30 label = "status"; 31 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 32 default-state = "on"; 33 }; 34 }; 35 36 reg_usdhc2_vmmc: regulator-usdhc2 { 37 compatible = "regulator-fixed"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 40 regulator-name = "VSD_3V3"; 41 regulator-min-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>; 43 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 }; 46 47 wm8524: audio-codec { 48 #sound-dai-cells = <0>; 49 compatible = "wlf,wm8524"; 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_gpio_wlf>; 52 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 53 }; 54 55 sound-wm8524 { 56 compatible = "simple-audio-card"; 57 simple-audio-card,name = "wm8524-audio"; 58 simple-audio-card,format = "i2s"; 59 simple-audio-card,frame-master = <&cpudai>; 60 simple-audio-card,bitclock-master = <&cpudai>; 61 simple-audio-card,widgets = 62 "Line", "Left Line Out Jack", 63 "Line", "Right Line Out Jack"; 64 simple-audio-card,routing = 65 "Left Line Out Jack", "LINEVOUTL", 66 "Right Line Out Jack", "LINEVOUTR"; 67 68 cpudai: simple-audio-card,cpu { 69 sound-dai = <&sai3>; 70 dai-tdm-slot-num = <2>; 71 dai-tdm-slot-width = <32>; 72 }; 73 74 simple-audio-card,codec { 75 sound-dai = <&wm8524>; 76 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 77 }; 78 }; 79}; 80 81&A53_0 { 82 cpu-supply = <&buck2_reg>; 83}; 84 85&ddrc { 86 operating-points-v2 = <&ddrc_opp_table>; 87 88 ddrc_opp_table: opp-table { 89 compatible = "operating-points-v2"; 90 91 opp-25M { 92 opp-hz = /bits/ 64 <25000000>; 93 }; 94 95 opp-100M { 96 opp-hz = /bits/ 64 <100000000>; 97 }; 98 99 opp-750M { 100 opp-hz = /bits/ 64 <750000000>; 101 }; 102 }; 103}; 104 105&fec1 { 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_fec1>; 108 phy-mode = "rgmii-id"; 109 phy-handle = <ðphy0>; 110 fsl,magic-packet; 111 status = "okay"; 112 113 mdio { 114 #address-cells = <1>; 115 #size-cells = <0>; 116 117 ethphy0: ethernet-phy@0 { 118 compatible = "ethernet-phy-ieee802.3-c22"; 119 reg = <0>; 120 }; 121 }; 122}; 123 124&i2c1 { 125 clock-frequency = <400000>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_i2c1>; 128 status = "okay"; 129 130 pmic@4b { 131 compatible = "rohm,bd71847"; 132 reg = <0x4b>; 133 pinctrl-0 = <&pinctrl_pmic>; 134 interrupt-parent = <&gpio1>; 135 interrupts = <3 GPIO_ACTIVE_LOW>; 136 rohm,reset-snvs-powered; 137 138 regulators { 139 buck1_reg: BUCK1 { 140 regulator-name = "BUCK1"; 141 regulator-min-microvolt = <700000>; 142 regulator-max-microvolt = <1300000>; 143 regulator-boot-on; 144 regulator-always-on; 145 regulator-ramp-delay = <1250>; 146 }; 147 148 buck2_reg: BUCK2 { 149 regulator-name = "BUCK2"; 150 regulator-min-microvolt = <700000>; 151 regulator-max-microvolt = <1300000>; 152 regulator-boot-on; 153 regulator-always-on; 154 regulator-ramp-delay = <1250>; 155 rohm,dvs-run-voltage = <1000000>; 156 rohm,dvs-idle-voltage = <900000>; 157 }; 158 159 buck3_reg: BUCK3 { 160 // BUCK5 in datasheet 161 regulator-name = "BUCK3"; 162 regulator-min-microvolt = <700000>; 163 regulator-max-microvolt = <1350000>; 164 regulator-boot-on; 165 regulator-always-on; 166 }; 167 168 buck4_reg: BUCK4 { 169 // BUCK6 in datasheet 170 regulator-name = "BUCK4"; 171 regulator-min-microvolt = <3000000>; 172 regulator-max-microvolt = <3300000>; 173 regulator-boot-on; 174 regulator-always-on; 175 }; 176 177 buck5_reg: BUCK5 { 178 // BUCK7 in datasheet 179 regulator-name = "BUCK5"; 180 regulator-min-microvolt = <1605000>; 181 regulator-max-microvolt = <1995000>; 182 regulator-boot-on; 183 regulator-always-on; 184 }; 185 186 buck6_reg: BUCK6 { 187 // BUCK8 in datasheet 188 regulator-name = "BUCK6"; 189 regulator-min-microvolt = <800000>; 190 regulator-max-microvolt = <1400000>; 191 regulator-boot-on; 192 regulator-always-on; 193 }; 194 195 ldo1_reg: LDO1 { 196 regulator-name = "LDO1"; 197 regulator-min-microvolt = <3000000>; 198 regulator-max-microvolt = <3300000>; 199 regulator-boot-on; 200 regulator-always-on; 201 }; 202 203 ldo2_reg: LDO2 { 204 regulator-name = "LDO2"; 205 regulator-min-microvolt = <900000>; 206 regulator-max-microvolt = <900000>; 207 regulator-boot-on; 208 regulator-always-on; 209 }; 210 211 ldo3_reg: LDO3 { 212 regulator-name = "LDO3"; 213 regulator-min-microvolt = <1800000>; 214 regulator-max-microvolt = <3300000>; 215 regulator-boot-on; 216 regulator-always-on; 217 }; 218 219 ldo4_reg: LDO4 { 220 regulator-name = "LDO4"; 221 regulator-min-microvolt = <900000>; 222 regulator-max-microvolt = <1800000>; 223 regulator-boot-on; 224 regulator-always-on; 225 }; 226 227 ldo6_reg: LDO6 { 228 regulator-name = "LDO6"; 229 regulator-min-microvolt = <900000>; 230 regulator-max-microvolt = <1800000>; 231 regulator-boot-on; 232 regulator-always-on; 233 }; 234 }; 235 }; 236}; 237 238&i2c2 { 239 clock-frequency = <400000>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_i2c2>; 242 status = "okay"; 243 244 ptn5110: tcpc@50 { 245 compatible = "nxp,ptn5110"; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_typec1>; 248 reg = <0x50>; 249 interrupt-parent = <&gpio2>; 250 interrupts = <11 8>; 251 status = "okay"; 252 253 port { 254 typec1_dr_sw: endpoint { 255 remote-endpoint = <&usb1_drd_sw>; 256 }; 257 }; 258 259 typec1_con: connector { 260 compatible = "usb-c-connector"; 261 label = "USB-C"; 262 power-role = "dual"; 263 data-role = "dual"; 264 try-power-role = "sink"; 265 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 266 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 267 PDO_VAR(5000, 20000, 3000)>; 268 op-sink-microwatt = <15000000>; 269 self-powered; 270 }; 271 }; 272}; 273 274&i2c3 { 275 clock-frequency = <400000>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_i2c3>; 278 status = "okay"; 279 280 pca6416: gpio@20 { 281 compatible = "ti,tca6416"; 282 reg = <0x20>; 283 gpio-controller; 284 #gpio-cells = <2>; 285 }; 286}; 287 288&sai3 { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_sai3>; 291 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 292 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 293 assigned-clock-rates = <24576000>; 294 status = "okay"; 295}; 296 297&snvs_pwrkey { 298 status = "okay"; 299}; 300 301&uart2 { /* console */ 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_uart2>; 304 status = "okay"; 305}; 306 307&usbotg1 { 308 dr_mode = "otg"; 309 hnp-disable; 310 srp-disable; 311 adp-disable; 312 usb-role-switch; 313 status = "okay"; 314 315 port { 316 usb1_drd_sw: endpoint { 317 remote-endpoint = <&typec1_dr_sw>; 318 }; 319 }; 320}; 321 322&usdhc2 { 323 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 324 assigned-clock-rates = <200000000>; 325 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 326 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 327 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 328 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 329 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 330 bus-width = <4>; 331 vmmc-supply = <®_usdhc2_vmmc>; 332 status = "okay"; 333}; 334 335&usdhc3 { 336 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 337 assigned-clock-rates = <400000000>; 338 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 339 pinctrl-0 = <&pinctrl_usdhc3>; 340 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 341 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 342 bus-width = <8>; 343 non-removable; 344 status = "okay"; 345}; 346 347&wdog1 { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pinctrl_wdog>; 350 fsl,ext-reset-output; 351 status = "okay"; 352}; 353 354&iomuxc { 355 pinctrl-names = "default"; 356 357 pinctrl_fec1: fec1grp { 358 fsl,pins = < 359 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 360 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 361 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 362 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 363 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 364 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 365 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 366 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 367 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 368 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 369 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 370 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 371 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 372 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 373 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 374 >; 375 }; 376 377 pinctrl_gpio_led: gpioledgrp { 378 fsl,pins = < 379 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 380 >; 381 }; 382 383 pinctrl_gpio_wlf: gpiowlfgrp { 384 fsl,pins = < 385 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 386 >; 387 }; 388 389 pinctrl_i2c1: i2c1grp { 390 fsl,pins = < 391 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 392 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 393 >; 394 }; 395 396 pinctrl_i2c2: i2c2grp { 397 fsl,pins = < 398 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 399 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 400 >; 401 }; 402 403 pinctrl_i2c3: i2c3grp { 404 fsl,pins = < 405 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 406 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 407 >; 408 }; 409 410 pinctrl_pmic: pmicirq { 411 fsl,pins = < 412 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 413 >; 414 }; 415 416 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { 417 fsl,pins = < 418 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 419 >; 420 }; 421 422 pinctrl_sai3: sai3grp { 423 fsl,pins = < 424 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 425 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 426 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 427 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 428 >; 429 }; 430 431 pinctrl_typec1: typec1grp { 432 fsl,pins = < 433 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 434 >; 435 }; 436 437 pinctrl_uart2: uart2grp { 438 fsl,pins = < 439 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 440 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 441 >; 442 }; 443 444 pinctrl_usdhc2_gpio: usdhc2grpgpio { 445 fsl,pins = < 446 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 447 >; 448 }; 449 450 pinctrl_usdhc2: usdhc2grp { 451 fsl,pins = < 452 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 453 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 454 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 455 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 456 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 457 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 458 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 459 >; 460 }; 461 462 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 463 fsl,pins = < 464 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 465 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 466 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 467 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 468 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 469 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 470 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 471 >; 472 }; 473 474 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 475 fsl,pins = < 476 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 477 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 478 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 479 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 480 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 481 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 482 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 483 >; 484 }; 485 486 pinctrl_usdhc3: usdhc3grp { 487 fsl,pins = < 488 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 489 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 490 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 491 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 492 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 493 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 494 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 495 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 496 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 497 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 498 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 499 >; 500 }; 501 502 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 503 fsl,pins = < 504 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 505 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 506 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 507 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 508 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 509 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 510 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 511 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 512 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 513 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 514 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 515 >; 516 }; 517 518 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 519 fsl,pins = < 520 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 521 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 522 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 523 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 524 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 525 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 526 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 527 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 528 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 529 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 530 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 531 >; 532 }; 533 534 pinctrl_wdog: wdoggrp { 535 fsl,pins = < 536 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 537 >; 538 }; 539}; 540