1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12	model = "FSL i.MX8MM EVK board";
13	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14
15	chosen {
16		stdout-path = &uart2;
17	};
18
19	leds {
20		compatible = "gpio-leds";
21		pinctrl-names = "default";
22		pinctrl-0 = <&pinctrl_gpio_led>;
23
24		status {
25			label = "status";
26			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
27			default-state = "on";
28		};
29	};
30
31	reg_usdhc2_vmmc: regulator-usdhc2 {
32		compatible = "regulator-fixed";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35		regulator-name = "VSD_3V3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39		enable-active-high;
40	};
41
42	wm8524: audio-codec {
43		#sound-dai-cells = <0>;
44		compatible = "wlf,wm8524";
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_gpio_wlf>;
47		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
48	};
49
50	sound-wm8524 {
51		compatible = "simple-audio-card";
52		simple-audio-card,name = "wm8524-audio";
53		simple-audio-card,format = "i2s";
54		simple-audio-card,frame-master = <&cpudai>;
55		simple-audio-card,bitclock-master = <&cpudai>;
56		simple-audio-card,widgets =
57			"Line", "Left Line Out Jack",
58			"Line", "Right Line Out Jack";
59		simple-audio-card,routing =
60			"Left Line Out Jack", "LINEVOUTL",
61			"Right Line Out Jack", "LINEVOUTR";
62
63		cpudai: simple-audio-card,cpu {
64			sound-dai = <&sai3>;
65		};
66
67		simple-audio-card,codec {
68			sound-dai = <&wm8524>;
69			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
70		};
71	};
72};
73
74&A53_0 {
75	cpu-supply = <&buck2_reg>;
76};
77
78&fec1 {
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_fec1>;
81	phy-mode = "rgmii-id";
82	phy-handle = <&ethphy0>;
83	fsl,magic-packet;
84	status = "okay";
85
86	mdio {
87		#address-cells = <1>;
88		#size-cells = <0>;
89
90		ethphy0: ethernet-phy@0 {
91			compatible = "ethernet-phy-ieee802.3-c22";
92			reg = <0>;
93		};
94	};
95};
96
97&sai3 {
98	pinctrl-names = "default";
99	pinctrl-0 = <&pinctrl_sai3>;
100	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
101	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
102	assigned-clock-rates = <24576000>;
103	status = "okay";
104};
105
106&snvs_pwrkey {
107	status = "okay";
108};
109
110&uart2 { /* console */
111	pinctrl-names = "default";
112	pinctrl-0 = <&pinctrl_uart2>;
113	status = "okay";
114};
115
116&usbotg1 {
117	dr_mode = "otg";
118	hnp-disable;
119	srp-disable;
120	adp-disable;
121	usb-role-switch;
122	status = "okay";
123
124	port {
125		usb1_drd_sw: endpoint {
126			remote-endpoint = <&typec1_dr_sw>;
127		};
128	};
129};
130
131&usdhc2 {
132	pinctrl-names = "default", "state_100mhz", "state_200mhz";
133	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
134	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
135	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
136	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
137	bus-width = <4>;
138	vmmc-supply = <&reg_usdhc2_vmmc>;
139	status = "okay";
140};
141
142&usdhc3 {
143	pinctrl-names = "default", "state_100mhz", "state_200mhz";
144	pinctrl-0 = <&pinctrl_usdhc3>;
145	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
146	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
147	bus-width = <8>;
148	non-removable;
149	status = "okay";
150};
151
152&wdog1 {
153	pinctrl-names = "default";
154	pinctrl-0 = <&pinctrl_wdog>;
155	fsl,ext-reset-output;
156	status = "okay";
157};
158
159&i2c1 {
160	clock-frequency = <400000>;
161	pinctrl-names = "default";
162	pinctrl-0 = <&pinctrl_i2c1>;
163	status = "okay";
164
165	pmic@4b {
166		compatible = "rohm,bd71847";
167		reg = <0x4b>;
168		pinctrl-0 = <&pinctrl_pmic>;
169		interrupt-parent = <&gpio1>;
170		interrupts = <3 GPIO_ACTIVE_LOW>;
171		rohm,reset-snvs-powered;
172
173		regulators {
174			buck1_reg: BUCK1 {
175				regulator-name = "BUCK1";
176				regulator-min-microvolt = <700000>;
177				regulator-max-microvolt = <1300000>;
178				regulator-boot-on;
179				regulator-always-on;
180				regulator-ramp-delay = <1250>;
181			};
182
183			buck2_reg: BUCK2 {
184				regulator-name = "BUCK2";
185				regulator-min-microvolt = <700000>;
186				regulator-max-microvolt = <1300000>;
187				regulator-boot-on;
188				regulator-always-on;
189				regulator-ramp-delay = <1250>;
190				rohm,dvs-run-voltage = <1000000>;
191				rohm,dvs-idle-voltage = <900000>;
192			};
193
194			buck3_reg: BUCK3 {
195				// BUCK5 in datasheet
196				regulator-name = "BUCK3";
197				regulator-min-microvolt = <700000>;
198				regulator-max-microvolt = <1350000>;
199				regulator-boot-on;
200				regulator-always-on;
201			};
202
203			buck4_reg: BUCK4 {
204				// BUCK6 in datasheet
205				regulator-name = "BUCK4";
206				regulator-min-microvolt = <3000000>;
207				regulator-max-microvolt = <3300000>;
208				regulator-boot-on;
209				regulator-always-on;
210			};
211
212			buck5_reg: BUCK5 {
213				// BUCK7 in datasheet
214				regulator-name = "BUCK5";
215				regulator-min-microvolt = <1605000>;
216				regulator-max-microvolt = <1995000>;
217				regulator-boot-on;
218				regulator-always-on;
219			};
220
221			buck6_reg: BUCK6 {
222				// BUCK8 in datasheet
223				regulator-name = "BUCK6";
224				regulator-min-microvolt = <800000>;
225				regulator-max-microvolt = <1400000>;
226				regulator-boot-on;
227				regulator-always-on;
228			};
229
230			ldo1_reg: LDO1 {
231				regulator-name = "LDO1";
232				regulator-min-microvolt = <3000000>;
233				regulator-max-microvolt = <3300000>;
234				regulator-boot-on;
235				regulator-always-on;
236			};
237
238			ldo2_reg: LDO2 {
239				regulator-name = "LDO2";
240				regulator-min-microvolt = <900000>;
241				regulator-max-microvolt = <900000>;
242				regulator-boot-on;
243				regulator-always-on;
244			};
245
246			ldo3_reg: LDO3 {
247				regulator-name = "LDO3";
248				regulator-min-microvolt = <1800000>;
249				regulator-max-microvolt = <3300000>;
250				regulator-boot-on;
251				regulator-always-on;
252			};
253
254			ldo4_reg: LDO4 {
255				regulator-name = "LDO4";
256				regulator-min-microvolt = <900000>;
257				regulator-max-microvolt = <1800000>;
258				regulator-boot-on;
259				regulator-always-on;
260			};
261
262			ldo6_reg: LDO6 {
263				regulator-name = "LDO6";
264				regulator-min-microvolt = <900000>;
265				regulator-max-microvolt = <1800000>;
266				regulator-boot-on;
267				regulator-always-on;
268			};
269		};
270	};
271};
272
273&i2c2 {
274	clock-frequency = <400000>;
275	pinctrl-names = "default";
276	pinctrl-0 = <&pinctrl_i2c2>;
277	status = "okay";
278
279	ptn5110: tcpc@50 {
280		compatible = "nxp,ptn5110";
281		pinctrl-names = "default";
282		pinctrl-0 = <&pinctrl_typec1>;
283		reg = <0x50>;
284		interrupt-parent = <&gpio2>;
285		interrupts = <11 8>;
286		status = "okay";
287
288		port {
289			typec1_dr_sw: endpoint {
290				remote-endpoint = <&usb1_drd_sw>;
291			};
292		};
293
294		typec1_con: connector {
295			compatible = "usb-c-connector";
296			label = "USB-C";
297			power-role = "dual";
298			data-role = "dual";
299			try-power-role = "sink";
300			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
301			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
302				     PDO_VAR(5000, 20000, 3000)>;
303			op-sink-microwatt = <15000000>;
304			self-powered;
305		};
306	};
307};
308
309&iomuxc {
310	pinctrl-names = "default";
311
312	pinctrl_fec1: fec1grp {
313		fsl,pins = <
314			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
315			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
316			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
317			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
318			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
319			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
320			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
321			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
322			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
323			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
324			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
325			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
326			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
327			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
328			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
329		>;
330	};
331
332	pinctrl_gpio_led: gpioledgrp {
333		fsl,pins = <
334			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
335		>;
336	};
337
338	pinctrl_gpio_wlf: gpiowlfgrp {
339		fsl,pins = <
340			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
341		>;
342	};
343
344	pinctrl_i2c1: i2c1grp {
345		fsl,pins = <
346			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
347			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
348		>;
349	};
350
351	pinctrl_i2c2: i2c2grp {
352		fsl,pins = <
353			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
354			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
355		>;
356	};
357
358	pinctrl_pmic: pmicirq {
359		fsl,pins = <
360			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
361		>;
362	};
363
364	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
365		fsl,pins = <
366			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
367		>;
368	};
369
370	pinctrl_sai3: sai3grp {
371		fsl,pins = <
372			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
373			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
374			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
375			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
376		>;
377	};
378
379	pinctrl_typec1: typec1grp {
380		fsl,pins = <
381			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
382		>;
383	};
384
385	pinctrl_uart2: uart2grp {
386		fsl,pins = <
387			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
388			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
389		>;
390	};
391
392	pinctrl_usdhc2_gpio: usdhc2grpgpio {
393		fsl,pins = <
394			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
395		>;
396	};
397
398	pinctrl_usdhc2: usdhc2grp {
399		fsl,pins = <
400			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
401			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
402			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
403			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
404			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
405			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
406			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
407		>;
408	};
409
410	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
411		fsl,pins = <
412			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
413			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
414			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
415			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
416			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
417			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
418			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
419		>;
420	};
421
422	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
423		fsl,pins = <
424			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
425			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
426			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
427			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
428			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
429			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
430			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
431		>;
432	};
433
434	pinctrl_usdhc3: usdhc3grp {
435		fsl,pins = <
436			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
437			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
438			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
439			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
440			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
441			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
442			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
443			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
444			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
445			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
446			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
447		>;
448	};
449
450	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
451		fsl,pins = <
452			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
453			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
454			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
455			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
456			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
457			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
458			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
459			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
460			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
461			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
462			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
463		>;
464	};
465
466	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
467		fsl,pins = <
468			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
469			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
470			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
471			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
472			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
473			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
474			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
475			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
476			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
477			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
478			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
479		>;
480	};
481
482	pinctrl_wdog: wdoggrp {
483		fsl,pins = <
484			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
485		>;
486	};
487};
488