1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12	model = "FSL i.MX8MM EVK board";
13	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14
15	chosen {
16		stdout-path = &uart2;
17	};
18
19	leds {
20		compatible = "gpio-leds";
21		pinctrl-names = "default";
22		pinctrl-0 = <&pinctrl_gpio_led>;
23
24		status {
25			label = "status";
26			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
27			default-state = "on";
28		};
29	};
30
31	reg_usdhc2_vmmc: regulator-usdhc2 {
32		compatible = "regulator-fixed";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35		regulator-name = "VSD_3V3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39		enable-active-high;
40	};
41
42	wm8524: audio-codec {
43		#sound-dai-cells = <0>;
44		compatible = "wlf,wm8524";
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_gpio_wlf>;
47		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
48	};
49
50	sound-wm8524 {
51		compatible = "simple-audio-card";
52		simple-audio-card,name = "wm8524-audio";
53		simple-audio-card,format = "i2s";
54		simple-audio-card,frame-master = <&cpudai>;
55		simple-audio-card,bitclock-master = <&cpudai>;
56		simple-audio-card,widgets =
57			"Line", "Left Line Out Jack",
58			"Line", "Right Line Out Jack";
59		simple-audio-card,routing =
60			"Left Line Out Jack", "LINEVOUTL",
61			"Right Line Out Jack", "LINEVOUTR";
62
63		cpudai: simple-audio-card,cpu {
64			sound-dai = <&sai3>;
65			dai-tdm-slot-num = <2>;
66			dai-tdm-slot-width = <32>;
67		};
68
69		simple-audio-card,codec {
70			sound-dai = <&wm8524>;
71			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
72		};
73	};
74};
75
76&A53_0 {
77	cpu-supply = <&buck2_reg>;
78};
79
80&fec1 {
81	pinctrl-names = "default";
82	pinctrl-0 = <&pinctrl_fec1>;
83	phy-mode = "rgmii-id";
84	phy-handle = <&ethphy0>;
85	fsl,magic-packet;
86	status = "okay";
87
88	mdio {
89		#address-cells = <1>;
90		#size-cells = <0>;
91
92		ethphy0: ethernet-phy@0 {
93			compatible = "ethernet-phy-ieee802.3-c22";
94			reg = <0>;
95		};
96	};
97};
98
99&i2c1 {
100	clock-frequency = <400000>;
101	pinctrl-names = "default";
102	pinctrl-0 = <&pinctrl_i2c1>;
103	status = "okay";
104
105	pmic@4b {
106		compatible = "rohm,bd71847";
107		reg = <0x4b>;
108		pinctrl-0 = <&pinctrl_pmic>;
109		interrupt-parent = <&gpio1>;
110		interrupts = <3 GPIO_ACTIVE_LOW>;
111		rohm,reset-snvs-powered;
112
113		regulators {
114			buck1_reg: BUCK1 {
115				regulator-name = "BUCK1";
116				regulator-min-microvolt = <700000>;
117				regulator-max-microvolt = <1300000>;
118				regulator-boot-on;
119				regulator-always-on;
120				regulator-ramp-delay = <1250>;
121			};
122
123			buck2_reg: BUCK2 {
124				regulator-name = "BUCK2";
125				regulator-min-microvolt = <700000>;
126				regulator-max-microvolt = <1300000>;
127				regulator-boot-on;
128				regulator-always-on;
129				regulator-ramp-delay = <1250>;
130				rohm,dvs-run-voltage = <1000000>;
131				rohm,dvs-idle-voltage = <900000>;
132			};
133
134			buck3_reg: BUCK3 {
135				// BUCK5 in datasheet
136				regulator-name = "BUCK3";
137				regulator-min-microvolt = <700000>;
138				regulator-max-microvolt = <1350000>;
139				regulator-boot-on;
140				regulator-always-on;
141			};
142
143			buck4_reg: BUCK4 {
144				// BUCK6 in datasheet
145				regulator-name = "BUCK4";
146				regulator-min-microvolt = <3000000>;
147				regulator-max-microvolt = <3300000>;
148				regulator-boot-on;
149				regulator-always-on;
150			};
151
152			buck5_reg: BUCK5 {
153				// BUCK7 in datasheet
154				regulator-name = "BUCK5";
155				regulator-min-microvolt = <1605000>;
156				regulator-max-microvolt = <1995000>;
157				regulator-boot-on;
158				regulator-always-on;
159			};
160
161			buck6_reg: BUCK6 {
162				// BUCK8 in datasheet
163				regulator-name = "BUCK6";
164				regulator-min-microvolt = <800000>;
165				regulator-max-microvolt = <1400000>;
166				regulator-boot-on;
167				regulator-always-on;
168			};
169
170			ldo1_reg: LDO1 {
171				regulator-name = "LDO1";
172				regulator-min-microvolt = <3000000>;
173				regulator-max-microvolt = <3300000>;
174				regulator-boot-on;
175				regulator-always-on;
176			};
177
178			ldo2_reg: LDO2 {
179				regulator-name = "LDO2";
180				regulator-min-microvolt = <900000>;
181				regulator-max-microvolt = <900000>;
182				regulator-boot-on;
183				regulator-always-on;
184			};
185
186			ldo3_reg: LDO3 {
187				regulator-name = "LDO3";
188				regulator-min-microvolt = <1800000>;
189				regulator-max-microvolt = <3300000>;
190				regulator-boot-on;
191				regulator-always-on;
192			};
193
194			ldo4_reg: LDO4 {
195				regulator-name = "LDO4";
196				regulator-min-microvolt = <900000>;
197				regulator-max-microvolt = <1800000>;
198				regulator-boot-on;
199				regulator-always-on;
200			};
201
202			ldo6_reg: LDO6 {
203				regulator-name = "LDO6";
204				regulator-min-microvolt = <900000>;
205				regulator-max-microvolt = <1800000>;
206				regulator-boot-on;
207				regulator-always-on;
208			};
209		};
210	};
211};
212
213&i2c2 {
214	clock-frequency = <400000>;
215	pinctrl-names = "default";
216	pinctrl-0 = <&pinctrl_i2c2>;
217	status = "okay";
218
219	ptn5110: tcpc@50 {
220		compatible = "nxp,ptn5110";
221		pinctrl-names = "default";
222		pinctrl-0 = <&pinctrl_typec1>;
223		reg = <0x50>;
224		interrupt-parent = <&gpio2>;
225		interrupts = <11 8>;
226		status = "okay";
227
228		port {
229			typec1_dr_sw: endpoint {
230				remote-endpoint = <&usb1_drd_sw>;
231			};
232		};
233
234		typec1_con: connector {
235			compatible = "usb-c-connector";
236			label = "USB-C";
237			power-role = "dual";
238			data-role = "dual";
239			try-power-role = "sink";
240			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
241			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
242				     PDO_VAR(5000, 20000, 3000)>;
243			op-sink-microwatt = <15000000>;
244			self-powered;
245		};
246	};
247};
248
249&i2c3 {
250	clock-frequency = <400000>;
251	pinctrl-names = "default";
252	pinctrl-0 = <&pinctrl_i2c3>;
253	status = "okay";
254
255	pca6416: gpio@20 {
256		compatible = "ti,tca6416";
257		reg = <0x20>;
258		gpio-controller;
259		#gpio-cells = <2>;
260	};
261};
262
263&sai3 {
264	pinctrl-names = "default";
265	pinctrl-0 = <&pinctrl_sai3>;
266	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
267	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
268	assigned-clock-rates = <24576000>;
269	status = "okay";
270};
271
272&snvs_pwrkey {
273	status = "okay";
274};
275
276&uart2 { /* console */
277	pinctrl-names = "default";
278	pinctrl-0 = <&pinctrl_uart2>;
279	status = "okay";
280};
281
282&usbotg1 {
283	dr_mode = "otg";
284	hnp-disable;
285	srp-disable;
286	adp-disable;
287	usb-role-switch;
288	status = "okay";
289
290	port {
291		usb1_drd_sw: endpoint {
292			remote-endpoint = <&typec1_dr_sw>;
293		};
294	};
295};
296
297&usdhc2 {
298	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
299	assigned-clock-rates = <200000000>;
300	pinctrl-names = "default", "state_100mhz", "state_200mhz";
301	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
302	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
303	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
304	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
305	bus-width = <4>;
306	vmmc-supply = <&reg_usdhc2_vmmc>;
307	status = "okay";
308};
309
310&usdhc3 {
311	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
312	assigned-clock-rates = <400000000>;
313	pinctrl-names = "default", "state_100mhz", "state_200mhz";
314	pinctrl-0 = <&pinctrl_usdhc3>;
315	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
316	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
317	bus-width = <8>;
318	non-removable;
319	status = "okay";
320};
321
322&wdog1 {
323	pinctrl-names = "default";
324	pinctrl-0 = <&pinctrl_wdog>;
325	fsl,ext-reset-output;
326	status = "okay";
327};
328
329&iomuxc {
330	pinctrl-names = "default";
331
332	pinctrl_fec1: fec1grp {
333		fsl,pins = <
334			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
335			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
336			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
337			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
338			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
339			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
340			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
341			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
342			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
343			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
344			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
345			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
346			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
347			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
348			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
349		>;
350	};
351
352	pinctrl_gpio_led: gpioledgrp {
353		fsl,pins = <
354			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
355		>;
356	};
357
358	pinctrl_gpio_wlf: gpiowlfgrp {
359		fsl,pins = <
360			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
361		>;
362	};
363
364	pinctrl_i2c1: i2c1grp {
365		fsl,pins = <
366			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
367			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
368		>;
369	};
370
371	pinctrl_i2c2: i2c2grp {
372		fsl,pins = <
373			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
374			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
375		>;
376	};
377
378	pinctrl_i2c3: i2c3grp {
379		fsl,pins = <
380			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
381			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
382		>;
383	};
384
385	pinctrl_pmic: pmicirq {
386		fsl,pins = <
387			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
388		>;
389	};
390
391	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
392		fsl,pins = <
393			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
394		>;
395	};
396
397	pinctrl_sai3: sai3grp {
398		fsl,pins = <
399			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
400			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
401			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
402			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
403		>;
404	};
405
406	pinctrl_typec1: typec1grp {
407		fsl,pins = <
408			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
409		>;
410	};
411
412	pinctrl_uart2: uart2grp {
413		fsl,pins = <
414			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
415			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
416		>;
417	};
418
419	pinctrl_usdhc2_gpio: usdhc2grpgpio {
420		fsl,pins = <
421			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
422		>;
423	};
424
425	pinctrl_usdhc2: usdhc2grp {
426		fsl,pins = <
427			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
428			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
429			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
430			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
431			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
432			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
433			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
434		>;
435	};
436
437	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
438		fsl,pins = <
439			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
440			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
441			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
442			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
443			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
444			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
445			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
446		>;
447	};
448
449	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
450		fsl,pins = <
451			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
452			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
453			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
454			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
455			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
456			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
457			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
458		>;
459	};
460
461	pinctrl_usdhc3: usdhc3grp {
462		fsl,pins = <
463			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
464			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
465			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
466			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
467			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
468			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
469			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
470			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
471			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
472			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
473			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
474		>;
475	};
476
477	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
478		fsl,pins = <
479			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
480			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
481			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
482			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
483			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
484			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
485			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
486			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
487			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
488			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
489			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
490		>;
491	};
492
493	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
494		fsl,pins = <
495			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
496			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
497			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
498			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
499			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
500			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
501			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
502			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
503			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
504			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
505			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
506		>;
507	};
508
509	pinctrl_wdog: wdoggrp {
510		fsl,pins = <
511			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
512		>;
513	};
514};
515