1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8mm.dtsi" 9 10/ { 11 model = "FSL i.MX8MM EVK board"; 12 compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; 13 14 chosen { 15 stdout-path = &uart2; 16 }; 17 18 leds { 19 compatible = "gpio-leds"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_led>; 22 23 status { 24 label = "status"; 25 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 26 default-state = "on"; 27 }; 28 }; 29 30 reg_usdhc2_vmmc: regulator-usdhc2 { 31 compatible = "regulator-fixed"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 34 regulator-name = "VSD_3V3"; 35 regulator-min-microvolt = <3300000>; 36 regulator-max-microvolt = <3300000>; 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 38 enable-active-high; 39 }; 40}; 41 42&A53_0 { 43 cpu-supply = <&buck2_reg>; 44}; 45 46&fec1 { 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_fec1>; 49 phy-mode = "rgmii-id"; 50 phy-handle = <ðphy0>; 51 fsl,magic-packet; 52 status = "okay"; 53 54 mdio { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 ethphy0: ethernet-phy@0 { 59 compatible = "ethernet-phy-ieee802.3-c22"; 60 reg = <0>; 61 at803x,led-act-blind-workaround; 62 at803x,eee-okay; 63 at803x,vddio-1p8v; 64 }; 65 }; 66}; 67 68&uart2 { /* console */ 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_uart2>; 71 status = "okay"; 72}; 73 74&usdhc2 { 75 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 76 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 77 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 78 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 79 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 80 bus-width = <4>; 81 vmmc-supply = <®_usdhc2_vmmc>; 82 status = "okay"; 83}; 84 85&usdhc3 { 86 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 87 pinctrl-0 = <&pinctrl_usdhc3>; 88 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 89 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 90 bus-width = <8>; 91 non-removable; 92 status = "okay"; 93}; 94 95&wdog1 { 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_wdog>; 98 fsl,ext-reset-output; 99 status = "okay"; 100}; 101 102&i2c1 { 103 clock-frequency = <400000>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_i2c1>; 106 status = "okay"; 107 108 pmic@4b { 109 compatible = "rohm,bd71847"; 110 reg = <0x4b>; 111 pinctrl-0 = <&pinctrl_pmic>; 112 interrupt-parent = <&gpio1>; 113 interrupts = <3 GPIO_ACTIVE_LOW>; 114 rohm,reset-snvs-powered; 115 116 regulators { 117 buck1_reg: BUCK1 { 118 regulator-name = "BUCK1"; 119 regulator-min-microvolt = <700000>; 120 regulator-max-microvolt = <1300000>; 121 regulator-boot-on; 122 regulator-always-on; 123 regulator-ramp-delay = <1250>; 124 }; 125 126 buck2_reg: BUCK2 { 127 regulator-name = "BUCK2"; 128 regulator-min-microvolt = <700000>; 129 regulator-max-microvolt = <1300000>; 130 regulator-boot-on; 131 regulator-always-on; 132 regulator-ramp-delay = <1250>; 133 rohm,dvs-run-voltage = <1000000>; 134 rohm,dvs-idle-voltage = <900000>; 135 }; 136 137 buck3_reg: BUCK3 { 138 // BUCK5 in datasheet 139 regulator-name = "BUCK3"; 140 regulator-min-microvolt = <700000>; 141 regulator-max-microvolt = <1350000>; 142 regulator-boot-on; 143 regulator-always-on; 144 }; 145 146 buck4_reg: BUCK4 { 147 // BUCK6 in datasheet 148 regulator-name = "BUCK4"; 149 regulator-min-microvolt = <3000000>; 150 regulator-max-microvolt = <3300000>; 151 regulator-boot-on; 152 regulator-always-on; 153 }; 154 155 buck5_reg: BUCK5 { 156 // BUCK7 in datasheet 157 regulator-name = "BUCK5"; 158 regulator-min-microvolt = <1605000>; 159 regulator-max-microvolt = <1995000>; 160 regulator-boot-on; 161 regulator-always-on; 162 }; 163 164 buck6_reg: BUCK6 { 165 // BUCK8 in datasheet 166 regulator-name = "BUCK6"; 167 regulator-min-microvolt = <800000>; 168 regulator-max-microvolt = <1400000>; 169 regulator-boot-on; 170 regulator-always-on; 171 }; 172 173 ldo1_reg: LDO1 { 174 regulator-name = "LDO1"; 175 regulator-min-microvolt = <3000000>; 176 regulator-max-microvolt = <3300000>; 177 regulator-boot-on; 178 regulator-always-on; 179 }; 180 181 ldo2_reg: LDO2 { 182 regulator-name = "LDO2"; 183 regulator-min-microvolt = <900000>; 184 regulator-max-microvolt = <900000>; 185 regulator-boot-on; 186 regulator-always-on; 187 }; 188 189 ldo3_reg: LDO3 { 190 regulator-name = "LDO3"; 191 regulator-min-microvolt = <1800000>; 192 regulator-max-microvolt = <3300000>; 193 regulator-boot-on; 194 regulator-always-on; 195 }; 196 197 ldo4_reg: LDO4 { 198 regulator-name = "LDO4"; 199 regulator-min-microvolt = <900000>; 200 regulator-max-microvolt = <1800000>; 201 regulator-boot-on; 202 regulator-always-on; 203 }; 204 205 ldo6_reg: LDO6 { 206 regulator-name = "LDO6"; 207 regulator-min-microvolt = <900000>; 208 regulator-max-microvolt = <1800000>; 209 regulator-boot-on; 210 regulator-always-on; 211 }; 212 }; 213 }; 214}; 215 216&iomuxc { 217 pinctrl-names = "default"; 218 219 pinctrl_fec1: fec1grp { 220 fsl,pins = < 221 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 222 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 223 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 224 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 225 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 226 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 227 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 228 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 229 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 230 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 231 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 232 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 233 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 234 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 235 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 236 >; 237 }; 238 239 pinctrl_gpio_led: gpioledgrp { 240 fsl,pins = < 241 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 242 >; 243 }; 244 245 pinctrl_i2c1: i2c1grp { 246 fsl,pins = < 247 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 248 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 249 >; 250 }; 251 252 pinctrl_pmic: pmicirq { 253 fsl,pins = < 254 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 255 >; 256 }; 257 258 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { 259 fsl,pins = < 260 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 261 >; 262 }; 263 264 pinctrl_uart2: uart2grp { 265 fsl,pins = < 266 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 267 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 268 >; 269 }; 270 271 pinctrl_usdhc2_gpio: usdhc2grpgpio { 272 fsl,pins = < 273 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 274 >; 275 }; 276 277 pinctrl_usdhc2: usdhc2grp { 278 fsl,pins = < 279 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 280 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 281 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 282 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 283 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 284 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 285 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 286 >; 287 }; 288 289 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 290 fsl,pins = < 291 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 292 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 293 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 294 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 295 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 296 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 297 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 298 >; 299 }; 300 301 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 302 fsl,pins = < 303 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 304 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 305 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 306 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 307 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 308 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 309 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 310 >; 311 }; 312 313 pinctrl_usdhc3: usdhc3grp { 314 fsl,pins = < 315 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 316 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 317 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 318 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 319 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 320 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 321 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 322 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 323 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 324 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 325 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 326 >; 327 }; 328 329 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 330 fsl,pins = < 331 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 332 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 333 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 334 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 335 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 336 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 337 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 338 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 339 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 340 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 341 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 342 >; 343 }; 344 345 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 346 fsl,pins = < 347 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 348 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 349 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 350 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 351 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 352 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 353 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 354 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 355 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 356 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 357 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 358 >; 359 }; 360 361 pinctrl_wdog: wdoggrp { 362 fsl,pins = < 363 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 364 >; 365 }; 366}; 367