1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx8mm.dtsi" 10 11/ { 12 model = "FSL i.MX8MM EVK board"; 13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; 14 15 aliases { 16 spi0 = &flexspi; 17 }; 18 19 chosen { 20 stdout-path = &uart2; 21 }; 22 23 memory@40000000 { 24 device_type = "memory"; 25 reg = <0x0 0x40000000 0 0x80000000>; 26 }; 27 28 leds { 29 compatible = "gpio-leds"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&pinctrl_gpio_led>; 32 33 status { 34 label = "status"; 35 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 36 default-state = "on"; 37 }; 38 }; 39 40 reg_usdhc2_vmmc: regulator-usdhc2 { 41 compatible = "regulator-fixed"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 44 regulator-name = "VSD_3V3"; 45 regulator-min-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>; 47 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 48 enable-active-high; 49 }; 50 51 wm8524: audio-codec { 52 #sound-dai-cells = <0>; 53 compatible = "wlf,wm8524"; 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_gpio_wlf>; 56 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 57 }; 58 59 sound-wm8524 { 60 compatible = "simple-audio-card"; 61 simple-audio-card,name = "wm8524-audio"; 62 simple-audio-card,format = "i2s"; 63 simple-audio-card,frame-master = <&cpudai>; 64 simple-audio-card,bitclock-master = <&cpudai>; 65 simple-audio-card,widgets = 66 "Line", "Left Line Out Jack", 67 "Line", "Right Line Out Jack"; 68 simple-audio-card,routing = 69 "Left Line Out Jack", "LINEVOUTL", 70 "Right Line Out Jack", "LINEVOUTR"; 71 72 cpudai: simple-audio-card,cpu { 73 sound-dai = <&sai3>; 74 dai-tdm-slot-num = <2>; 75 dai-tdm-slot-width = <32>; 76 }; 77 78 simple-audio-card,codec { 79 sound-dai = <&wm8524>; 80 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 81 }; 82 }; 83}; 84 85&A53_0 { 86 cpu-supply = <&buck2_reg>; 87}; 88 89&A53_1 { 90 cpu-supply = <&buck2_reg>; 91}; 92 93&A53_2 { 94 cpu-supply = <&buck2_reg>; 95}; 96 97&A53_3 { 98 cpu-supply = <&buck2_reg>; 99}; 100 101&ddrc { 102 operating-points-v2 = <&ddrc_opp_table>; 103 104 ddrc_opp_table: opp-table { 105 compatible = "operating-points-v2"; 106 107 opp-25M { 108 opp-hz = /bits/ 64 <25000000>; 109 }; 110 111 opp-100M { 112 opp-hz = /bits/ 64 <100000000>; 113 }; 114 115 opp-750M { 116 opp-hz = /bits/ 64 <750000000>; 117 }; 118 }; 119}; 120 121&fec1 { 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_fec1>; 124 phy-mode = "rgmii-id"; 125 phy-handle = <ðphy0>; 126 fsl,magic-packet; 127 status = "okay"; 128 129 mdio { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 ethphy0: ethernet-phy@0 { 134 compatible = "ethernet-phy-ieee802.3-c22"; 135 reg = <0>; 136 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 137 reset-assert-us = <10000>; 138 }; 139 }; 140}; 141 142&flexspi { 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_flexspi>; 145 status = "okay"; 146 147 flash@0 { 148 reg = <0>; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 compatible = "jedec,spi-nor"; 152 spi-max-frequency = <80000000>; 153 spi-tx-bus-width = <4>; 154 spi-rx-bus-width = <4>; 155 }; 156}; 157 158&i2c1 { 159 clock-frequency = <400000>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_i2c1>; 162 status = "okay"; 163 164 pmic@4b { 165 compatible = "rohm,bd71847"; 166 reg = <0x4b>; 167 pinctrl-0 = <&pinctrl_pmic>; 168 interrupt-parent = <&gpio1>; 169 interrupts = <3 GPIO_ACTIVE_LOW>; 170 rohm,reset-snvs-powered; 171 172 regulators { 173 buck1_reg: BUCK1 { 174 regulator-name = "buck1"; 175 regulator-min-microvolt = <700000>; 176 regulator-max-microvolt = <1300000>; 177 regulator-boot-on; 178 regulator-always-on; 179 regulator-ramp-delay = <1250>; 180 }; 181 182 buck2_reg: BUCK2 { 183 regulator-name = "buck2"; 184 regulator-min-microvolt = <700000>; 185 regulator-max-microvolt = <1300000>; 186 regulator-boot-on; 187 regulator-always-on; 188 regulator-ramp-delay = <1250>; 189 rohm,dvs-run-voltage = <1000000>; 190 rohm,dvs-idle-voltage = <900000>; 191 }; 192 193 buck3_reg: BUCK3 { 194 // BUCK5 in datasheet 195 regulator-name = "buck3"; 196 regulator-min-microvolt = <700000>; 197 regulator-max-microvolt = <1350000>; 198 regulator-boot-on; 199 regulator-always-on; 200 }; 201 202 buck4_reg: BUCK4 { 203 // BUCK6 in datasheet 204 regulator-name = "buck4"; 205 regulator-min-microvolt = <3000000>; 206 regulator-max-microvolt = <3300000>; 207 regulator-boot-on; 208 regulator-always-on; 209 }; 210 211 buck5_reg: BUCK5 { 212 // BUCK7 in datasheet 213 regulator-name = "buck5"; 214 regulator-min-microvolt = <1605000>; 215 regulator-max-microvolt = <1995000>; 216 regulator-boot-on; 217 regulator-always-on; 218 }; 219 220 buck6_reg: BUCK6 { 221 // BUCK8 in datasheet 222 regulator-name = "buck6"; 223 regulator-min-microvolt = <800000>; 224 regulator-max-microvolt = <1400000>; 225 regulator-boot-on; 226 regulator-always-on; 227 }; 228 229 ldo1_reg: LDO1 { 230 regulator-name = "ldo1"; 231 regulator-min-microvolt = <1600000>; 232 regulator-max-microvolt = <3300000>; 233 regulator-boot-on; 234 regulator-always-on; 235 }; 236 237 ldo2_reg: LDO2 { 238 regulator-name = "ldo2"; 239 regulator-min-microvolt = <800000>; 240 regulator-max-microvolt = <900000>; 241 regulator-boot-on; 242 regulator-always-on; 243 }; 244 245 ldo3_reg: LDO3 { 246 regulator-name = "ldo3"; 247 regulator-min-microvolt = <1800000>; 248 regulator-max-microvolt = <3300000>; 249 regulator-boot-on; 250 regulator-always-on; 251 }; 252 253 ldo4_reg: LDO4 { 254 regulator-name = "ldo4"; 255 regulator-min-microvolt = <900000>; 256 regulator-max-microvolt = <1800000>; 257 regulator-boot-on; 258 regulator-always-on; 259 }; 260 261 ldo6_reg: LDO6 { 262 regulator-name = "ldo6"; 263 regulator-min-microvolt = <900000>; 264 regulator-max-microvolt = <1800000>; 265 regulator-boot-on; 266 regulator-always-on; 267 }; 268 }; 269 }; 270}; 271 272&i2c2 { 273 clock-frequency = <400000>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_i2c2>; 276 status = "okay"; 277 278 ptn5110: tcpc@50 { 279 compatible = "nxp,ptn5110"; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_typec1>; 282 reg = <0x50>; 283 interrupt-parent = <&gpio2>; 284 interrupts = <11 8>; 285 status = "okay"; 286 287 port { 288 typec1_dr_sw: endpoint { 289 remote-endpoint = <&usb1_drd_sw>; 290 }; 291 }; 292 293 typec1_con: connector { 294 compatible = "usb-c-connector"; 295 label = "USB-C"; 296 power-role = "dual"; 297 data-role = "dual"; 298 try-power-role = "sink"; 299 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 300 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 301 PDO_VAR(5000, 20000, 3000)>; 302 op-sink-microwatt = <15000000>; 303 self-powered; 304 }; 305 }; 306}; 307 308&i2c3 { 309 clock-frequency = <400000>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_i2c3>; 312 status = "okay"; 313 314 pca6416: gpio@20 { 315 compatible = "ti,tca6416"; 316 reg = <0x20>; 317 gpio-controller; 318 #gpio-cells = <2>; 319 }; 320}; 321 322&sai3 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_sai3>; 325 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 326 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 327 assigned-clock-rates = <24576000>; 328 status = "okay"; 329}; 330 331&snvs_pwrkey { 332 status = "okay"; 333}; 334 335&uart2 { /* console */ 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_uart2>; 338 status = "okay"; 339}; 340 341&usbotg1 { 342 dr_mode = "otg"; 343 hnp-disable; 344 srp-disable; 345 adp-disable; 346 usb-role-switch; 347 samsung,picophy-pre-emp-curr-control = <3>; 348 samsung,picophy-dc-vol-level-adjust = <7>; 349 status = "okay"; 350 351 port { 352 usb1_drd_sw: endpoint { 353 remote-endpoint = <&typec1_dr_sw>; 354 }; 355 }; 356}; 357 358&usdhc2 { 359 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 360 assigned-clock-rates = <200000000>; 361 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 362 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 363 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 364 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 365 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 366 bus-width = <4>; 367 vmmc-supply = <®_usdhc2_vmmc>; 368 status = "okay"; 369}; 370 371&usdhc3 { 372 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 373 assigned-clock-rates = <400000000>; 374 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 375 pinctrl-0 = <&pinctrl_usdhc3>; 376 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 377 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 378 bus-width = <8>; 379 non-removable; 380 status = "okay"; 381}; 382 383&wdog1 { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_wdog>; 386 fsl,ext-reset-output; 387 status = "okay"; 388}; 389 390&iomuxc { 391 pinctrl_fec1: fec1grp { 392 fsl,pins = < 393 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 394 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 395 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 396 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 397 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 398 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 399 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 400 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 401 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 402 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 403 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 404 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 405 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 406 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 407 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 408 >; 409 }; 410 411 pinctrl_gpio_led: gpioledgrp { 412 fsl,pins = < 413 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 414 >; 415 }; 416 417 pinctrl_gpio_wlf: gpiowlfgrp { 418 fsl,pins = < 419 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 420 >; 421 }; 422 423 pinctrl_i2c1: i2c1grp { 424 fsl,pins = < 425 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 426 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 427 >; 428 }; 429 430 pinctrl_i2c2: i2c2grp { 431 fsl,pins = < 432 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 433 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 434 >; 435 }; 436 437 pinctrl_i2c3: i2c3grp { 438 fsl,pins = < 439 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 440 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 441 >; 442 }; 443 444 pinctrl_flexspi: flexspigrp { 445 fsl,pins = < 446 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 447 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 448 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 449 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 450 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 451 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 452 >; 453 }; 454 455 pinctrl_pmic: pmicirq { 456 fsl,pins = < 457 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 458 >; 459 }; 460 461 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { 462 fsl,pins = < 463 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 464 >; 465 }; 466 467 pinctrl_sai3: sai3grp { 468 fsl,pins = < 469 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 470 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 471 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 472 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 473 >; 474 }; 475 476 pinctrl_typec1: typec1grp { 477 fsl,pins = < 478 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 479 >; 480 }; 481 482 pinctrl_uart2: uart2grp { 483 fsl,pins = < 484 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 485 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 486 >; 487 }; 488 489 pinctrl_usdhc2_gpio: usdhc2grpgpio { 490 fsl,pins = < 491 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 492 >; 493 }; 494 495 pinctrl_usdhc2: usdhc2grp { 496 fsl,pins = < 497 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 498 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 499 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 500 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 501 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 502 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 503 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 504 >; 505 }; 506 507 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 508 fsl,pins = < 509 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 510 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 511 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 512 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 513 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 514 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 515 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 516 >; 517 }; 518 519 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 520 fsl,pins = < 521 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 522 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 523 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 524 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 525 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 526 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 527 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 528 >; 529 }; 530 531 pinctrl_usdhc3: usdhc3grp { 532 fsl,pins = < 533 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 534 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 535 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 536 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 537 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 538 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 539 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 540 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 541 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 542 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 543 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 544 >; 545 }; 546 547 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 548 fsl,pins = < 549 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 550 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 551 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 552 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 553 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 554 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 555 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 556 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 557 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 558 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 559 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 560 >; 561 }; 562 563 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 564 fsl,pins = < 565 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 566 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 567 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 568 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 569 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 570 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 571 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 572 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 573 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 574 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 575 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 576 >; 577 }; 578 579 pinctrl_wdog: wdoggrp { 580 fsl,pins = < 581 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 582 >; 583 }; 584}; 585