1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12	model = "FSL i.MX8MM EVK board";
13	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
14
15	chosen {
16		stdout-path = &uart2;
17	};
18
19	leds {
20		compatible = "gpio-leds";
21		pinctrl-names = "default";
22		pinctrl-0 = <&pinctrl_gpio_led>;
23
24		status {
25			label = "status";
26			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
27			default-state = "on";
28		};
29	};
30
31	reg_usdhc2_vmmc: regulator-usdhc2 {
32		compatible = "regulator-fixed";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35		regulator-name = "VSD_3V3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39		enable-active-high;
40	};
41
42	wm8524: audio-codec {
43		#sound-dai-cells = <0>;
44		compatible = "wlf,wm8524";
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_gpio_wlf>;
47		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
48	};
49
50	sound-wm8524 {
51		compatible = "simple-audio-card";
52		simple-audio-card,name = "wm8524-audio";
53		simple-audio-card,format = "i2s";
54		simple-audio-card,frame-master = <&cpudai>;
55		simple-audio-card,bitclock-master = <&cpudai>;
56		simple-audio-card,widgets =
57			"Line", "Left Line Out Jack",
58			"Line", "Right Line Out Jack";
59		simple-audio-card,routing =
60			"Left Line Out Jack", "LINEVOUTL",
61			"Right Line Out Jack", "LINEVOUTR";
62
63		cpudai: simple-audio-card,cpu {
64			sound-dai = <&sai3>;
65		};
66
67		simple-audio-card,codec {
68			sound-dai = <&wm8524>;
69			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
70		};
71	};
72};
73
74&A53_0 {
75	cpu-supply = <&buck2_reg>;
76};
77
78&fec1 {
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_fec1>;
81	phy-mode = "rgmii-id";
82	phy-handle = <&ethphy0>;
83	fsl,magic-packet;
84	status = "okay";
85
86	mdio {
87		#address-cells = <1>;
88		#size-cells = <0>;
89
90		ethphy0: ethernet-phy@0 {
91			compatible = "ethernet-phy-ieee802.3-c22";
92			reg = <0>;
93		};
94	};
95};
96
97&i2c1 {
98	clock-frequency = <400000>;
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_i2c1>;
101	status = "okay";
102
103	pmic@4b {
104		compatible = "rohm,bd71847";
105		reg = <0x4b>;
106		pinctrl-0 = <&pinctrl_pmic>;
107		interrupt-parent = <&gpio1>;
108		interrupts = <3 GPIO_ACTIVE_LOW>;
109		rohm,reset-snvs-powered;
110
111		regulators {
112			buck1_reg: BUCK1 {
113				regulator-name = "BUCK1";
114				regulator-min-microvolt = <700000>;
115				regulator-max-microvolt = <1300000>;
116				regulator-boot-on;
117				regulator-always-on;
118				regulator-ramp-delay = <1250>;
119			};
120
121			buck2_reg: BUCK2 {
122				regulator-name = "BUCK2";
123				regulator-min-microvolt = <700000>;
124				regulator-max-microvolt = <1300000>;
125				regulator-boot-on;
126				regulator-always-on;
127				regulator-ramp-delay = <1250>;
128				rohm,dvs-run-voltage = <1000000>;
129				rohm,dvs-idle-voltage = <900000>;
130			};
131
132			buck3_reg: BUCK3 {
133				// BUCK5 in datasheet
134				regulator-name = "BUCK3";
135				regulator-min-microvolt = <700000>;
136				regulator-max-microvolt = <1350000>;
137				regulator-boot-on;
138				regulator-always-on;
139			};
140
141			buck4_reg: BUCK4 {
142				// BUCK6 in datasheet
143				regulator-name = "BUCK4";
144				regulator-min-microvolt = <3000000>;
145				regulator-max-microvolt = <3300000>;
146				regulator-boot-on;
147				regulator-always-on;
148			};
149
150			buck5_reg: BUCK5 {
151				// BUCK7 in datasheet
152				regulator-name = "BUCK5";
153				regulator-min-microvolt = <1605000>;
154				regulator-max-microvolt = <1995000>;
155				regulator-boot-on;
156				regulator-always-on;
157			};
158
159			buck6_reg: BUCK6 {
160				// BUCK8 in datasheet
161				regulator-name = "BUCK6";
162				regulator-min-microvolt = <800000>;
163				regulator-max-microvolt = <1400000>;
164				regulator-boot-on;
165				regulator-always-on;
166			};
167
168			ldo1_reg: LDO1 {
169				regulator-name = "LDO1";
170				regulator-min-microvolt = <3000000>;
171				regulator-max-microvolt = <3300000>;
172				regulator-boot-on;
173				regulator-always-on;
174			};
175
176			ldo2_reg: LDO2 {
177				regulator-name = "LDO2";
178				regulator-min-microvolt = <900000>;
179				regulator-max-microvolt = <900000>;
180				regulator-boot-on;
181				regulator-always-on;
182			};
183
184			ldo3_reg: LDO3 {
185				regulator-name = "LDO3";
186				regulator-min-microvolt = <1800000>;
187				regulator-max-microvolt = <3300000>;
188				regulator-boot-on;
189				regulator-always-on;
190			};
191
192			ldo4_reg: LDO4 {
193				regulator-name = "LDO4";
194				regulator-min-microvolt = <900000>;
195				regulator-max-microvolt = <1800000>;
196				regulator-boot-on;
197				regulator-always-on;
198			};
199
200			ldo6_reg: LDO6 {
201				regulator-name = "LDO6";
202				regulator-min-microvolt = <900000>;
203				regulator-max-microvolt = <1800000>;
204				regulator-boot-on;
205				regulator-always-on;
206			};
207		};
208	};
209};
210
211&i2c2 {
212	clock-frequency = <400000>;
213	pinctrl-names = "default";
214	pinctrl-0 = <&pinctrl_i2c2>;
215	status = "okay";
216
217	ptn5110: tcpc@50 {
218		compatible = "nxp,ptn5110";
219		pinctrl-names = "default";
220		pinctrl-0 = <&pinctrl_typec1>;
221		reg = <0x50>;
222		interrupt-parent = <&gpio2>;
223		interrupts = <11 8>;
224		status = "okay";
225
226		port {
227			typec1_dr_sw: endpoint {
228				remote-endpoint = <&usb1_drd_sw>;
229			};
230		};
231
232		typec1_con: connector {
233			compatible = "usb-c-connector";
234			label = "USB-C";
235			power-role = "dual";
236			data-role = "dual";
237			try-power-role = "sink";
238			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
239			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
240				     PDO_VAR(5000, 20000, 3000)>;
241			op-sink-microwatt = <15000000>;
242			self-powered;
243		};
244	};
245};
246
247&i2c3 {
248	clock-frequency = <400000>;
249	pinctrl-names = "default";
250	pinctrl-0 = <&pinctrl_i2c3>;
251	status = "okay";
252};
253
254&sai3 {
255	pinctrl-names = "default";
256	pinctrl-0 = <&pinctrl_sai3>;
257	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
258	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
259	assigned-clock-rates = <24576000>;
260	status = "okay";
261};
262
263&snvs_pwrkey {
264	status = "okay";
265};
266
267&uart2 { /* console */
268	pinctrl-names = "default";
269	pinctrl-0 = <&pinctrl_uart2>;
270	status = "okay";
271};
272
273&usbotg1 {
274	dr_mode = "otg";
275	hnp-disable;
276	srp-disable;
277	adp-disable;
278	usb-role-switch;
279	status = "okay";
280
281	port {
282		usb1_drd_sw: endpoint {
283			remote-endpoint = <&typec1_dr_sw>;
284		};
285	};
286};
287
288&usdhc2 {
289	pinctrl-names = "default", "state_100mhz", "state_200mhz";
290	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
291	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
292	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
293	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
294	bus-width = <4>;
295	vmmc-supply = <&reg_usdhc2_vmmc>;
296	status = "okay";
297};
298
299&usdhc3 {
300	pinctrl-names = "default", "state_100mhz", "state_200mhz";
301	pinctrl-0 = <&pinctrl_usdhc3>;
302	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
303	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
304	bus-width = <8>;
305	non-removable;
306	status = "okay";
307};
308
309&wdog1 {
310	pinctrl-names = "default";
311	pinctrl-0 = <&pinctrl_wdog>;
312	fsl,ext-reset-output;
313	status = "okay";
314};
315
316&iomuxc {
317	pinctrl-names = "default";
318
319	pinctrl_fec1: fec1grp {
320		fsl,pins = <
321			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
322			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
323			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
324			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
325			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
326			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
327			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
328			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
329			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
330			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
331			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
332			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
333			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
334			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
335			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
336		>;
337	};
338
339	pinctrl_gpio_led: gpioledgrp {
340		fsl,pins = <
341			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
342		>;
343	};
344
345	pinctrl_gpio_wlf: gpiowlfgrp {
346		fsl,pins = <
347			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
348		>;
349	};
350
351	pinctrl_i2c1: i2c1grp {
352		fsl,pins = <
353			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
354			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
355		>;
356	};
357
358	pinctrl_i2c2: i2c2grp {
359		fsl,pins = <
360			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
361			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
362		>;
363	};
364
365	pinctrl_i2c3: i2c3grp {
366		fsl,pins = <
367			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
368			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
369		>;
370	};
371
372	pinctrl_pmic: pmicirq {
373		fsl,pins = <
374			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
375		>;
376	};
377
378	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
379		fsl,pins = <
380			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
381		>;
382	};
383
384	pinctrl_sai3: sai3grp {
385		fsl,pins = <
386			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
387			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
388			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
389			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
390		>;
391	};
392
393	pinctrl_typec1: typec1grp {
394		fsl,pins = <
395			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
396		>;
397	};
398
399	pinctrl_uart2: uart2grp {
400		fsl,pins = <
401			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
402			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
403		>;
404	};
405
406	pinctrl_usdhc2_gpio: usdhc2grpgpio {
407		fsl,pins = <
408			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
409		>;
410	};
411
412	pinctrl_usdhc2: usdhc2grp {
413		fsl,pins = <
414			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
415			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
416			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
417			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
418			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
419			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
420			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
421		>;
422	};
423
424	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
425		fsl,pins = <
426			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
427			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
428			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
429			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
430			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
431			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
432			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
433		>;
434	};
435
436	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
437		fsl,pins = <
438			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
439			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
440			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
441			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
442			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
443			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
444			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
445		>;
446	};
447
448	pinctrl_usdhc3: usdhc3grp {
449		fsl,pins = <
450			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
451			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
452			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
453			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
454			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
455			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
456			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
457			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
458			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
459			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
460			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
461		>;
462	};
463
464	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
465		fsl,pins = <
466			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
467			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
468			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
469			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
470			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
471			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
472			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
473			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
474			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
475			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
476			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
477		>;
478	};
479
480	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
481		fsl,pins = <
482			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
483			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
484			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
485			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
486			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
487			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
488			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
489			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
490			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
491			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
492			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
493		>;
494	};
495
496	pinctrl_wdog: wdoggrp {
497		fsl,pins = <
498			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
499		>;
500	};
501};
502