1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx8mm.dtsi" 10 11/ { 12 model = "FSL i.MX8MM EVK board"; 13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 leds { 20 compatible = "gpio-leds"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_gpio_led>; 23 24 status { 25 label = "status"; 26 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 27 default-state = "on"; 28 }; 29 }; 30 31 reg_usdhc2_vmmc: regulator-usdhc2 { 32 compatible = "regulator-fixed"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 35 regulator-name = "VSD_3V3"; 36 regulator-min-microvolt = <3300000>; 37 regulator-max-microvolt = <3300000>; 38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 39 enable-active-high; 40 }; 41 42 wm8524: audio-codec { 43 #sound-dai-cells = <0>; 44 compatible = "wlf,wm8524"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_gpio_wlf>; 47 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 48 }; 49 50 sound-wm8524 { 51 compatible = "simple-audio-card"; 52 simple-audio-card,name = "wm8524-audio"; 53 simple-audio-card,format = "i2s"; 54 simple-audio-card,frame-master = <&cpudai>; 55 simple-audio-card,bitclock-master = <&cpudai>; 56 simple-audio-card,widgets = 57 "Line", "Left Line Out Jack", 58 "Line", "Right Line Out Jack"; 59 simple-audio-card,routing = 60 "Left Line Out Jack", "LINEVOUTL", 61 "Right Line Out Jack", "LINEVOUTR"; 62 63 cpudai: simple-audio-card,cpu { 64 sound-dai = <&sai3>; 65 dai-tdm-slot-num = <2>; 66 dai-tdm-slot-width = <32>; 67 }; 68 69 simple-audio-card,codec { 70 sound-dai = <&wm8524>; 71 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 72 }; 73 }; 74}; 75 76&A53_0 { 77 cpu-supply = <&buck2_reg>; 78}; 79 80&ddrc { 81 operating-points-v2 = <&ddrc_opp_table>; 82 83 ddrc_opp_table: opp-table { 84 compatible = "operating-points-v2"; 85 86 opp-25M { 87 opp-hz = /bits/ 64 <25000000>; 88 }; 89 90 opp-100M { 91 opp-hz = /bits/ 64 <100000000>; 92 }; 93 94 opp-750M { 95 opp-hz = /bits/ 64 <750000000>; 96 }; 97 }; 98}; 99 100&fec1 { 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_fec1>; 103 phy-mode = "rgmii-id"; 104 phy-handle = <ðphy0>; 105 fsl,magic-packet; 106 status = "okay"; 107 108 mdio { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 ethphy0: ethernet-phy@0 { 113 compatible = "ethernet-phy-ieee802.3-c22"; 114 reg = <0>; 115 }; 116 }; 117}; 118 119&i2c1 { 120 clock-frequency = <400000>; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_i2c1>; 123 status = "okay"; 124 125 pmic@4b { 126 compatible = "rohm,bd71847"; 127 reg = <0x4b>; 128 pinctrl-0 = <&pinctrl_pmic>; 129 interrupt-parent = <&gpio1>; 130 interrupts = <3 GPIO_ACTIVE_LOW>; 131 rohm,reset-snvs-powered; 132 133 regulators { 134 buck1_reg: BUCK1 { 135 regulator-name = "BUCK1"; 136 regulator-min-microvolt = <700000>; 137 regulator-max-microvolt = <1300000>; 138 regulator-boot-on; 139 regulator-always-on; 140 regulator-ramp-delay = <1250>; 141 }; 142 143 buck2_reg: BUCK2 { 144 regulator-name = "BUCK2"; 145 regulator-min-microvolt = <700000>; 146 regulator-max-microvolt = <1300000>; 147 regulator-boot-on; 148 regulator-always-on; 149 regulator-ramp-delay = <1250>; 150 rohm,dvs-run-voltage = <1000000>; 151 rohm,dvs-idle-voltage = <900000>; 152 }; 153 154 buck3_reg: BUCK3 { 155 // BUCK5 in datasheet 156 regulator-name = "BUCK3"; 157 regulator-min-microvolt = <700000>; 158 regulator-max-microvolt = <1350000>; 159 regulator-boot-on; 160 regulator-always-on; 161 }; 162 163 buck4_reg: BUCK4 { 164 // BUCK6 in datasheet 165 regulator-name = "BUCK4"; 166 regulator-min-microvolt = <3000000>; 167 regulator-max-microvolt = <3300000>; 168 regulator-boot-on; 169 regulator-always-on; 170 }; 171 172 buck5_reg: BUCK5 { 173 // BUCK7 in datasheet 174 regulator-name = "BUCK5"; 175 regulator-min-microvolt = <1605000>; 176 regulator-max-microvolt = <1995000>; 177 regulator-boot-on; 178 regulator-always-on; 179 }; 180 181 buck6_reg: BUCK6 { 182 // BUCK8 in datasheet 183 regulator-name = "BUCK6"; 184 regulator-min-microvolt = <800000>; 185 regulator-max-microvolt = <1400000>; 186 regulator-boot-on; 187 regulator-always-on; 188 }; 189 190 ldo1_reg: LDO1 { 191 regulator-name = "LDO1"; 192 regulator-min-microvolt = <3000000>; 193 regulator-max-microvolt = <3300000>; 194 regulator-boot-on; 195 regulator-always-on; 196 }; 197 198 ldo2_reg: LDO2 { 199 regulator-name = "LDO2"; 200 regulator-min-microvolt = <900000>; 201 regulator-max-microvolt = <900000>; 202 regulator-boot-on; 203 regulator-always-on; 204 }; 205 206 ldo3_reg: LDO3 { 207 regulator-name = "LDO3"; 208 regulator-min-microvolt = <1800000>; 209 regulator-max-microvolt = <3300000>; 210 regulator-boot-on; 211 regulator-always-on; 212 }; 213 214 ldo4_reg: LDO4 { 215 regulator-name = "LDO4"; 216 regulator-min-microvolt = <900000>; 217 regulator-max-microvolt = <1800000>; 218 regulator-boot-on; 219 regulator-always-on; 220 }; 221 222 ldo6_reg: LDO6 { 223 regulator-name = "LDO6"; 224 regulator-min-microvolt = <900000>; 225 regulator-max-microvolt = <1800000>; 226 regulator-boot-on; 227 regulator-always-on; 228 }; 229 }; 230 }; 231}; 232 233&i2c2 { 234 clock-frequency = <400000>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_i2c2>; 237 status = "okay"; 238 239 ptn5110: tcpc@50 { 240 compatible = "nxp,ptn5110"; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_typec1>; 243 reg = <0x50>; 244 interrupt-parent = <&gpio2>; 245 interrupts = <11 8>; 246 status = "okay"; 247 248 port { 249 typec1_dr_sw: endpoint { 250 remote-endpoint = <&usb1_drd_sw>; 251 }; 252 }; 253 254 typec1_con: connector { 255 compatible = "usb-c-connector"; 256 label = "USB-C"; 257 power-role = "dual"; 258 data-role = "dual"; 259 try-power-role = "sink"; 260 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 261 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 262 PDO_VAR(5000, 20000, 3000)>; 263 op-sink-microwatt = <15000000>; 264 self-powered; 265 }; 266 }; 267}; 268 269&i2c3 { 270 clock-frequency = <400000>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_i2c3>; 273 status = "okay"; 274 275 pca6416: gpio@20 { 276 compatible = "ti,tca6416"; 277 reg = <0x20>; 278 gpio-controller; 279 #gpio-cells = <2>; 280 }; 281}; 282 283&sai3 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_sai3>; 286 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 287 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 288 assigned-clock-rates = <24576000>; 289 status = "okay"; 290}; 291 292&snvs_pwrkey { 293 status = "okay"; 294}; 295 296&uart2 { /* console */ 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_uart2>; 299 status = "okay"; 300}; 301 302&usbotg1 { 303 dr_mode = "otg"; 304 hnp-disable; 305 srp-disable; 306 adp-disable; 307 usb-role-switch; 308 status = "okay"; 309 310 port { 311 usb1_drd_sw: endpoint { 312 remote-endpoint = <&typec1_dr_sw>; 313 }; 314 }; 315}; 316 317&usdhc2 { 318 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 319 assigned-clock-rates = <200000000>; 320 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 321 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 322 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 323 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 324 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 325 bus-width = <4>; 326 vmmc-supply = <®_usdhc2_vmmc>; 327 status = "okay"; 328}; 329 330&usdhc3 { 331 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 332 assigned-clock-rates = <400000000>; 333 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 334 pinctrl-0 = <&pinctrl_usdhc3>; 335 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 336 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 337 bus-width = <8>; 338 non-removable; 339 status = "okay"; 340}; 341 342&wdog1 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_wdog>; 345 fsl,ext-reset-output; 346 status = "okay"; 347}; 348 349&iomuxc { 350 pinctrl-names = "default"; 351 352 pinctrl_fec1: fec1grp { 353 fsl,pins = < 354 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 355 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 356 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 357 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 358 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 359 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 360 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 361 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 362 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 363 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 364 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 365 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 366 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 367 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 368 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 369 >; 370 }; 371 372 pinctrl_gpio_led: gpioledgrp { 373 fsl,pins = < 374 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 375 >; 376 }; 377 378 pinctrl_gpio_wlf: gpiowlfgrp { 379 fsl,pins = < 380 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 381 >; 382 }; 383 384 pinctrl_i2c1: i2c1grp { 385 fsl,pins = < 386 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 387 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 388 >; 389 }; 390 391 pinctrl_i2c2: i2c2grp { 392 fsl,pins = < 393 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 394 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 395 >; 396 }; 397 398 pinctrl_i2c3: i2c3grp { 399 fsl,pins = < 400 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 401 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 402 >; 403 }; 404 405 pinctrl_pmic: pmicirq { 406 fsl,pins = < 407 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 408 >; 409 }; 410 411 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { 412 fsl,pins = < 413 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 414 >; 415 }; 416 417 pinctrl_sai3: sai3grp { 418 fsl,pins = < 419 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 420 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 421 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 422 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 423 >; 424 }; 425 426 pinctrl_typec1: typec1grp { 427 fsl,pins = < 428 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 429 >; 430 }; 431 432 pinctrl_uart2: uart2grp { 433 fsl,pins = < 434 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 435 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 436 >; 437 }; 438 439 pinctrl_usdhc2_gpio: usdhc2grpgpio { 440 fsl,pins = < 441 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 442 >; 443 }; 444 445 pinctrl_usdhc2: usdhc2grp { 446 fsl,pins = < 447 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 448 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 449 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 450 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 451 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 452 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 453 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 454 >; 455 }; 456 457 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 458 fsl,pins = < 459 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 460 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 461 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 462 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 463 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 464 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 465 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 466 >; 467 }; 468 469 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 470 fsl,pins = < 471 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 472 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 473 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 474 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 475 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 476 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 477 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 478 >; 479 }; 480 481 pinctrl_usdhc3: usdhc3grp { 482 fsl,pins = < 483 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 484 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 485 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 486 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 487 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 488 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 489 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 490 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 491 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 492 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 493 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 494 >; 495 }; 496 497 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 498 fsl,pins = < 499 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 500 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 501 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 502 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 503 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 504 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 505 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 506 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 507 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 508 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 509 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 510 >; 511 }; 512 513 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 514 fsl,pins = < 515 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 516 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 517 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 518 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 519 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 520 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 521 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 522 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 523 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 524 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 525 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 526 >; 527 }; 528 529 pinctrl_wdog: wdoggrp { 530 fsl,pins = < 531 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 532 >; 533 }; 534}; 535