1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Marek Vasut <marex@denx.de> 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/net/qca-ar803x.h> 9#include <dt-bindings/phy/phy-imx8-pcie.h> 10#include "imx8mm.dtsi" 11 12/ { 13 model = "Data Modul i.MX8M Mini eDM SBC"; 14 compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm"; 15 16 aliases { 17 rtc0 = &rtc; 18 rtc1 = &snvs_rtc; 19 }; 20 21 chosen { 22 stdout-path = &uart3; 23 }; 24 25 memory@40000000 { 26 device_type = "memory"; 27 /* There are 1/2/4 GiB options, adjusted by bootloader. */ 28 reg = <0x0 0x40000000 0 0x40000000>; 29 }; 30 31 backlight: backlight { 32 compatible = "pwm-backlight"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_panel_backlight>; 35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; 36 default-brightness-level = <7>; 37 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 38 pwms = <&pwm1 0 5000000 0>; 39 /* Disabled by default, unless display board plugged in. */ 40 status = "disabled"; 41 }; 42 43 clk_xtal25: clk-xtal25 { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <25000000>; 47 }; 48 49 clk_xtal32k: clk-xtal32k { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <32768>; 53 }; 54 55 panel: panel { 56 backlight = <&backlight>; 57 power-supply = <®_panel_vcc>; 58 /* Disabled by default, unless display board plugged in. */ 59 status = "disabled"; 60 }; 61 62 reg_panel_vcc: regulator-panel-vcc { 63 compatible = "regulator-fixed"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_panel_vcc_reg>; 66 regulator-name = "PANEL_VCC"; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 gpio = <&gpio3 6 0>; 70 enable-active-high; 71 /* Disabled by default, unless display board plugged in. */ 72 status = "disabled"; 73 }; 74 75 reg_usdhc2_vcc: regulator-usdhc2-vcc { 76 compatible = "regulator-fixed"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>; 79 regulator-name = "V_3V3_SD"; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 gpio = <&gpio2 19 0>; 83 enable-active-high; 84 }; 85 86 watchdog { 87 /* TPS3813 */ 88 pinctrl-names = "default"; 89 pinctrl-0 = <&pinctrl_watchdog_gpio>; 90 compatible = "linux,wdt-gpio"; 91 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 92 hw_algo = "level"; 93 /* Reset triggers in 2..3 seconds */ 94 hw_margin_ms = <1500>; 95 /* Disabled by default */ 96 status = "disabled"; 97 }; 98}; 99 100&A53_0 { 101 cpu-supply = <&buck2_reg>; 102}; 103 104&A53_1 { 105 cpu-supply = <&buck2_reg>; 106}; 107 108&A53_2 { 109 cpu-supply = <&buck2_reg>; 110}; 111 112&A53_3 { 113 cpu-supply = <&buck2_reg>; 114}; 115 116&ddrc { 117 operating-points-v2 = <&ddrc_opp_table>; 118 119 ddrc_opp_table: opp-table { 120 compatible = "operating-points-v2"; 121 122 opp-25000000 { 123 opp-hz = /bits/ 64 <25000000>; 124 }; 125 126 opp-100000000 { 127 opp-hz = /bits/ 64 <100000000>; 128 }; 129 130 opp-750000000 { 131 opp-hz = /bits/ 64 <750000000>; 132 }; 133 }; 134}; 135 136&ecspi1 { 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_ecspi1>; 139 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 140 status = "okay"; 141 142 flash@0 { /* W25Q128FVSI */ 143 compatible = "jedec,spi-nor"; 144 m25p,fast-read; 145 spi-max-frequency = <50000000>; 146 reg = <0>; 147 }; 148}; 149 150&ecspi2 { /* Feature connector SPI */ 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_ecspi2>; 153 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 154 /* Disabled by default, unless feature board plugged in. */ 155 status = "disabled"; 156}; 157 158&ecspi3 { /* Display connector SPI */ 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_ecspi3>; 161 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 162 /* Disabled by default, unless display board plugged in. */ 163 status = "disabled"; 164}; 165 166&fec1 { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_fec1>; 169 phy-mode = "rgmii-id"; 170 phy-handle = <&fec1_phy>; 171 phy-supply = <&buck4_reg>; 172 fsl,magic-packet; 173 status = "okay"; 174 175 mdio { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 179 /* Atheros AR8031 PHY */ 180 fec1_phy: ethernet-phy@0 { 181 compatible = "ethernet-phy-ieee802.3-c22"; 182 reg = <0>; 183 /* 184 * Dedicated ENET_WOL# signal is unused, the PHY 185 * can wake the SoC up via INT signal as well. 186 */ 187 interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>; 188 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 189 reset-assert-us = <10000>; 190 reset-deassert-us = <10000>; 191 qca,keep-pll-enabled; 192 vddio-supply = <&vddio>; 193 194 vddio: vddio-regulator { 195 regulator-name = "VDDIO"; 196 regulator-min-microvolt = <1800000>; 197 regulator-max-microvolt = <1800000>; 198 }; 199 200 vddh: vddh-regulator { 201 regulator-name = "VDDH"; 202 }; 203 }; 204 }; 205}; 206 207&gpio1 { 208 gpio-line-names = 209 "", "ENET_RST#", "WDOG_B#", "PMIC_INT#", 210 "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#", 211 "WDOG_KICK#", "M2-B_PCIE_CLKREQ#", 212 "USB1_OTG_ID_3V3", "ENET_WOL#", 213 "", "", "", "ENET_INT#", 214 "", "", "", "", "", "", "", "", 215 "", "", "", "", "", "", "", ""; 216}; 217 218&gpio2 { 219 gpio-line-names = 220 "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#", 221 "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#", 222 "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#", 223 "MEMCFG0", "WDOG_EN", 224 "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#", 225 "", "", "", "", 226 "", "", "", "SD2_RESET#", "", "", "", "", 227 "", "", "", "", "", "", "", ""; 228}; 229 230&gpio3 { 231 gpio-line-names = 232 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "", 233 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8", 234 "CSI_PD_1V8", "CSI_RESET_1V8#", "", "", 235 "", "", "", "", 236 "", "", "", "M2-B_WAKE_WWAN_1V8#", 237 "M2-B_RESET_1V8#", "", "", "", 238 "", "", "", "", "", "", "", ""; 239}; 240 241&gpio4 { 242 gpio-line-names = 243 "NC0", "NC1", "BOOTCFG0", "BOOTCFG1", 244 "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5", 245 "BOOTCFG6", "BOOTCFG7", "NC10", "NC11", 246 "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11", 247 "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15", 248 "NC20", "", "", "", 249 "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27", 250 "DIS_USB_DN2", "", "", ""; 251}; 252 253&gpio5 { 254 gpio-line-names = 255 "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03", 256 "GPIO5_IO04", "", "", "", 257 "", "SPI1_CS#", "", "", 258 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3", 259 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3", 260 "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "", 261 "", "SPI3_CS#", "", "", "", "", "", ""; 262}; 263 264&i2c1 { 265 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ 266 clock-frequency = <100000>; 267 pinctrl-names = "default", "gpio"; 268 pinctrl-0 = <&pinctrl_i2c1>; 269 pinctrl-1 = <&pinctrl_i2c1_gpio>; 270 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 271 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 272 status = "okay"; 273 274 pmic: pmic@4b { 275 compatible = "rohm,bd71847"; 276 reg = <0x4b>; 277 #clock-cells = <0>; 278 clocks = <&clk_xtal32k 0>; 279 clock-output-names = "clk-32k-out"; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_pmic>; 282 interrupt-parent = <&gpio1>; 283 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 284 rohm,reset-snvs-powered; 285 286 /* 287 * i.MX 8M Mini Data Sheet for Consumer Products 288 * 3.1.3 Operating ranges 289 * MIMX8MM4DVTLZAA 290 */ 291 regulators { 292 /* VDD_SOC */ 293 buck1_reg: BUCK1 { 294 regulator-name = "buck1"; 295 regulator-min-microvolt = <850000>; 296 regulator-max-microvolt = <850000>; 297 regulator-boot-on; 298 regulator-always-on; 299 regulator-ramp-delay = <1250>; 300 }; 301 302 /* VDD_ARM */ 303 buck2_reg: BUCK2 { 304 regulator-name = "buck2"; 305 regulator-min-microvolt = <850000>; 306 regulator-max-microvolt = <1050000>; 307 regulator-boot-on; 308 regulator-always-on; 309 regulator-ramp-delay = <1250>; 310 rohm,dvs-run-voltage = <1000000>; 311 rohm,dvs-idle-voltage = <950000>; 312 }; 313 314 /* VDD_DRAM, BUCK5 */ 315 buck3_reg: BUCK3 { 316 regulator-name = "buck3"; 317 /* 1.5 GHz DDR bus clock */ 318 regulator-min-microvolt = <900000>; 319 regulator-max-microvolt = <1000000>; 320 regulator-boot-on; 321 regulator-always-on; 322 }; 323 324 /* 3V3_VDD, BUCK6 */ 325 buck4_reg: BUCK4 { 326 regulator-name = "buck4"; 327 regulator-min-microvolt = <3300000>; 328 regulator-max-microvolt = <3300000>; 329 regulator-boot-on; 330 regulator-always-on; 331 }; 332 333 /* 1V8_VDD, BUCK7 */ 334 buck5_reg: BUCK5 { 335 regulator-name = "buck5"; 336 regulator-min-microvolt = <1800000>; 337 regulator-max-microvolt = <1800000>; 338 regulator-boot-on; 339 regulator-always-on; 340 }; 341 342 /* 1V1_NVCC_DRAM, BUCK8 */ 343 buck6_reg: BUCK6 { 344 regulator-name = "buck6"; 345 regulator-min-microvolt = <1100000>; 346 regulator-max-microvolt = <1100000>; 347 regulator-boot-on; 348 regulator-always-on; 349 }; 350 351 /* 1V8_NVCC_SNVS */ 352 ldo1_reg: LDO1 { 353 regulator-name = "ldo1"; 354 regulator-min-microvolt = <1800000>; 355 regulator-max-microvolt = <1800000>; 356 regulator-boot-on; 357 regulator-always-on; 358 }; 359 360 /* 0V8_VDD_SNVS */ 361 ldo2_reg: LDO2 { 362 regulator-name = "ldo2"; 363 regulator-min-microvolt = <800000>; 364 regulator-max-microvolt = <800000>; 365 regulator-boot-on; 366 regulator-always-on; 367 }; 368 369 /* 1V8_VDDA */ 370 ldo3_reg: LDO3 { 371 regulator-name = "ldo3"; 372 regulator-min-microvolt = <1800000>; 373 regulator-max-microvolt = <1800000>; 374 regulator-boot-on; 375 regulator-always-on; 376 }; 377 378 /* 0V9_VDD_PHY */ 379 ldo4_reg: LDO4 { 380 regulator-name = "ldo4"; 381 regulator-min-microvolt = <900000>; 382 regulator-max-microvolt = <900000>; 383 regulator-boot-on; 384 regulator-always-on; 385 }; 386 387 /* 1V2_VDD_PHY */ 388 ldo6_reg: LDO6 { 389 regulator-name = "ldo6"; 390 regulator-min-microvolt = <1200000>; 391 regulator-max-microvolt = <1200000>; 392 regulator-boot-on; 393 regulator-always-on; 394 }; 395 }; 396 }; 397}; 398 399&i2c2 { 400 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ 401 clock-frequency = <100000>; 402 pinctrl-names = "default", "gpio"; 403 pinctrl-0 = <&pinctrl_i2c2>; 404 pinctrl-1 = <&pinctrl_i2c2_gpio>; 405 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 406 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 407 status = "okay"; 408 409 usb-hub@2c { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_usb_hub>; 412 compatible = "microchip,usb2514bi"; 413 reg = <0x2c>; 414 individual-port-switching; 415 reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 416 self-powered; 417 }; 418 419 eeprom: eeprom@50 { 420 compatible = "atmel,24c32"; 421 reg = <0x50>; 422 pagesize = <32>; 423 }; 424 425 rtc: rtc@68 { 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pinctrl_rtc>; 428 compatible = "st,m41t62"; 429 reg = <0x68>; 430 interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>; 431 }; 432 433 pcieclk: clk@6a { 434 compatible = "renesas,9fgv0241"; 435 reg = <0x6a>; 436 clocks = <&clk_xtal25>; 437 #clock-cells = <1>; 438 }; 439}; 440 441&i2c3 { /* Display connector I2C */ 442 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ 443 clock-frequency = <320000>; 444 pinctrl-names = "default", "gpio"; 445 pinctrl-0 = <&pinctrl_i2c3>; 446 pinctrl-1 = <&pinctrl_i2c3_gpio>; 447 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 448 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 449 status = "okay"; 450}; 451 452&i2c4 { /* Feature connector I2C */ 453 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ 454 clock-frequency = <320000>; 455 pinctrl-names = "default", "gpio"; 456 pinctrl-0 = <&pinctrl_i2c4>; 457 pinctrl-1 = <&pinctrl_i2c4_gpio>; 458 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 459 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 460 status = "okay"; 461}; 462 463&iomuxc { 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>, 466 <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>, 467 <&pinctrl_panel_expansion>; 468 469 pinctrl_ecspi1: ecspi1-grp { 470 fsl,pins = < 471 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44 472 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44 473 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44 474 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 475 >; 476 }; 477 478 pinctrl_ecspi2: ecspi2-grp { 479 fsl,pins = < 480 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44 481 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44 482 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44 483 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 484 >; 485 }; 486 487 pinctrl_ecspi3: ecspi3-grp { 488 fsl,pins = < 489 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44 490 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44 491 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44 492 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40 493 >; 494 }; 495 496 pinctrl_fec1: fec1-grp { 497 fsl,pins = < 498 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 499 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 500 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 501 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 502 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 503 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 504 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 505 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 506 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 507 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 508 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 509 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 510 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 511 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 512 /* ENET_RST# */ 513 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6 514 /* ENET_WOL# */ 515 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090 516 /* ENET_INT# */ 517 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090 518 >; 519 }; 520 521 pinctrl_hog_feature: hog-feature-grp { 522 fsl,pins = < 523 /* GPIO4_IO27 */ 524 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006 525 /* GPIO5_IO03 */ 526 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006 527 /* GPIO5_IO04 */ 528 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006 529 530 /* CAN_INT# */ 531 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090 532 /* CAN_RST# */ 533 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26 534 >; 535 }; 536 537 pinctrl_hog_panel: hog-panel-grp { 538 fsl,pins = < 539 /* GRAPHICS_GPIO0_1V8 */ 540 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26 541 >; 542 }; 543 544 pinctrl_hog_misc: hog-misc-grp { 545 fsl,pins = < 546 /* PG_V_IN_VAR# */ 547 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000 548 /* CSI_PD_1V8 */ 549 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0 550 /* CSI_RESET_1V8# */ 551 MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0 552 553 /* DIS_USB_DN1 */ 554 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0 555 /* DIS_USB_DN2 */ 556 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0 557 558 /* EEPROM_WP_1V8# */ 559 MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100 560 /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */ 561 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 562 /* GRAPHICS_PRSNT_1V8# */ 563 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000 564 565 /* CLK_CCM_CLKO1_3V3 */ 566 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10 567 >; 568 }; 569 570 pinctrl_hog_sbc: hog-sbc-grp { 571 fsl,pins = < 572 /* MEMCFG[0..2] straps */ 573 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140 574 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140 575 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140 576 577 /* BOOT_CFG[0..15] straps */ 578 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000 579 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000 580 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000 581 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000 582 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000 583 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000 584 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000 585 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000 586 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000 587 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000 588 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000 589 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000 590 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000 591 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000 592 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000 593 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000 594 595 /* Not connected pins */ 596 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0 597 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0 598 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0 599 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0 600 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0 601 >; 602 }; 603 604 pinctrl_i2c1: i2c1-grp { 605 fsl,pins = < 606 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084 607 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084 608 >; 609 }; 610 611 pinctrl_i2c1_gpio: i2c1-gpio-grp { 612 fsl,pins = < 613 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84 614 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84 615 >; 616 }; 617 618 pinctrl_i2c2: i2c2-grp { 619 fsl,pins = < 620 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084 621 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084 622 >; 623 }; 624 625 pinctrl_i2c2_gpio: i2c2-gpio-grp { 626 fsl,pins = < 627 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84 628 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84 629 >; 630 }; 631 632 pinctrl_i2c3: i2c3-grp { 633 fsl,pins = < 634 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084 635 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084 636 >; 637 }; 638 639 pinctrl_i2c3_gpio: i2c3-gpio-grp { 640 fsl,pins = < 641 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84 642 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84 643 >; 644 }; 645 646 pinctrl_i2c4: i2c4-grp { 647 fsl,pins = < 648 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084 649 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084 650 >; 651 }; 652 653 pinctrl_i2c4_gpio: i2c4-gpio-grp { 654 fsl,pins = < 655 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84 656 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84 657 >; 658 }; 659 660 pinctrl_panel_backlight: panel-backlight-grp { 661 fsl,pins = < 662 /* BL_ENABLE_1V8 */ 663 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104 664 >; 665 }; 666 667 pinctrl_panel_expansion: panel-expansion-grp { 668 fsl,pins = < 669 /* DSI_RESET_1V8# */ 670 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2 671 /* DSI_IRQ_1V8# */ 672 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090 673 >; 674 }; 675 676 pinctrl_panel_vcc_reg: panel-vcc-grp { 677 fsl,pins = < 678 /* TFT_ENABLE_1V8 */ 679 MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104 680 >; 681 }; 682 683 pinctrl_panel_pwm: panel-pwm-grp { 684 fsl,pins = < 685 /* BL_PWM_3V3 */ 686 MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12 687 >; 688 }; 689 690 pinctrl_pcie0: pcie-grp { 691 fsl,pins = < 692 /* M2-B_RESET_1V8# */ 693 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102 694 /* M2-B_PCIE_RST# */ 695 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2 696 /* M2-B_FULL_CARD_PWROFF_1V8# */ 697 MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102 698 /* M2-B_W_DISABLE1_WWAN_1V8# */ 699 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102 700 /* M2-B_W_DISABLE2_GPS_1V8# */ 701 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102 702 /* CLK_M2_32K768 */ 703 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14 704 /* M2-B_WAKE_WWAN_1V8# */ 705 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140 706 /* M2-B_PCIE_WAKE# */ 707 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140 708 /* M2-B_PCIE_CLKREQ# */ 709 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140 710 >; 711 }; 712 713 pinctrl_pmic: pmic-grp { 714 fsl,pins = < 715 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090 716 >; 717 }; 718 719 pinctrl_rtc: rtc-grp { 720 fsl,pins = < 721 /* RTC_IRQ# */ 722 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090 723 >; 724 }; 725 726 pinctrl_sai5: sai5-grp { 727 fsl,pins = < 728 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100 729 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0 730 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100 731 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100 732 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100 733 >; 734 }; 735 736 pinctrl_uart1: uart1-grp { 737 fsl,pins = < 738 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90 739 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90 740 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50 741 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50 742 >; 743 }; 744 745 pinctrl_uart2: uart2-grp { 746 fsl,pins = < 747 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50 748 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90 749 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50 750 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90 751 >; 752 }; 753 754 pinctrl_uart3: uart3-grp { 755 fsl,pins = < 756 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 757 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 758 >; 759 }; 760 761 pinctrl_uart4: uart4-grp { 762 fsl,pins = < 763 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40 764 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40 765 >; 766 }; 767 768 pinctrl_usb_hub: usb-hub-grp { 769 fsl,pins = < 770 /* USBHUB_RESET# */ 771 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4 772 >; 773 }; 774 775 pinctrl_usb_otg1: usb-otg1-grp { 776 fsl,pins = < 777 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000 778 MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4 779 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090 780 >; 781 }; 782 783 pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp { 784 fsl,pins = < 785 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4 786 >; 787 }; 788 789 pinctrl_usdhc2: usdhc2-grp { 790 fsl,pins = < 791 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 792 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 793 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 794 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 795 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 796 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 797 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 798 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 799 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 800 >; 801 }; 802 803 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 804 fsl,pins = < 805 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 806 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 807 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 808 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 809 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 810 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 811 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 812 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 813 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 814 >; 815 }; 816 817 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 818 fsl,pins = < 819 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 820 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 821 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 822 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 823 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 824 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 825 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 826 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 827 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 828 >; 829 }; 830 831 pinctrl_usdhc3: usdhc3-grp { 832 fsl,pins = < 833 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 834 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 835 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 836 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 837 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 838 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 839 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 840 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 841 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 842 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 843 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 844 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 845 >; 846 }; 847 848 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 849 fsl,pins = < 850 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 851 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 852 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 853 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 854 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 855 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 856 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 857 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 858 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 859 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 860 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 861 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 862 >; 863 }; 864 865 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 866 fsl,pins = < 867 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 868 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 869 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 870 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 871 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 872 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 873 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 874 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 875 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 876 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 877 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 878 MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 879 >; 880 }; 881 882 pinctrl_watchdog_gpio: watchdog-gpio-grp { 883 fsl,pins = < 884 /* WDOG_B# */ 885 MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26 886 /* WDOG_EN -- ungate WDT RESET# signal propagation */ 887 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6 888 /* WDOG_KICK# / WDI */ 889 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26 890 >; 891 }; 892}; 893 894&pcie_phy { 895 fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */ 896 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 897 fsl,tx-deemph-gen1 = <0x2d>; 898 fsl,tx-deemph-gen2 = <0xf>; 899 clocks = <&pcieclk 0>; 900 status = "okay"; 901}; 902 903&pcie0 { 904 pinctrl-names = "default"; 905 pinctrl-0 = <&pinctrl_pcie0>; 906 reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; 907 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 908 <&pcieclk 0>; 909 clock-names = "pcie", "pcie_aux", "pcie_bus"; 910 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 911 <&clk IMX8MM_CLK_PCIE1_CTRL>; 912 assigned-clock-rates = <10000000>, <250000000>; 913 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 914 <&clk IMX8MM_SYS_PLL2_250M>; 915 status = "okay"; 916}; 917 918&pwm1 { 919 pinctrl-names = "default"; 920 pinctrl-0 = <&pinctrl_panel_pwm>; 921 /* Disabled by default, unless display board plugged in. */ 922 status = "disabled"; 923}; 924 925&sai5 { 926 pinctrl-names = "default"; 927 pinctrl-0 = <&pinctrl_sai5>; 928 fsl,sai-mclk-direction-output; 929 /* Input into codec PLL */ 930 assigned-clocks = <&clk IMX8MM_CLK_SAI5>; 931 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; 932 assigned-clock-rates = <22579200>; 933 /* Disabled by default, unless display board plugged in. */ 934 status = "disabled"; 935}; 936 937&snvs_rtc { 938 clocks = <&pmic>; 939}; 940 941&uart1 { 942 pinctrl-names = "default"; 943 pinctrl-0 = <&pinctrl_uart1>; 944 uart-has-rtscts; 945 status = "disabled"; 946}; 947 948&uart2 { 949 pinctrl-names = "default"; 950 pinctrl-0 = <&pinctrl_uart2>; 951 status = "disabled"; 952}; 953 954&uart3 { /* A53 Debug */ 955 pinctrl-names = "default"; 956 pinctrl-0 = <&pinctrl_uart3>; 957 status = "okay"; 958}; 959 960&uart4 { /* M4 Debug */ 961 pinctrl-names = "default"; 962 pinctrl-0 = <&pinctrl_uart4>; 963 /* UART4 is reserved for CM and RDC blocks CA access to UART4. */ 964 status = "disabled"; 965}; 966 967&usbotg1 { 968 pinctrl-names = "default"; 969 pinctrl-0 = <&pinctrl_usb_otg1>; 970 dr_mode = "otg"; 971 status = "okay"; 972}; 973 974&usbotg2 { 975 disable-over-current; 976 dr_mode = "host"; 977 status = "okay"; 978}; 979 980&usdhc2 { /* MicroSD */ 981 assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>; 982 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 983 pinctrl-0 = <&pinctrl_usdhc2>; 984 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 985 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 986 bus-width = <4>; 987 vmmc-supply = <®_usdhc2_vcc>; 988 status = "okay"; 989}; 990 991&usdhc3 { /* eMMC */ 992 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 993 assigned-clock-rates = <400000000>; 994 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 995 pinctrl-0 = <&pinctrl_usdhc3>; 996 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 997 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 998 bus-width = <8>; 999 non-removable; 1000 vmmc-supply = <&buck4_reg>; 1001 vqmmc-supply = <&buck5_reg>; 1002 status = "okay"; 1003}; 1004 1005&wdog1 { 1006 status = "okay"; 1007}; 1008