1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6/ {
7	aliases {
8		rtc0 = &rtc;
9		rtc1 = &snvs_rtc;
10	};
11
12	usdhc1_pwrseq: usdhc1_pwrseq {
13		compatible = "mmc-pwrseq-simple";
14		pinctrl-names = "default";
15		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
16		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
17		clocks = <&osc_32k>;
18		clock-names = "ext_clock";
19		post-power-on-delay-ms = <80>;
20	};
21
22	memory@40000000 {
23		device_type = "memory";
24		reg = <0x0 0x40000000 0 0x80000000>;
25	};
26};
27
28&A53_0 {
29	cpu-supply = <&buck2_reg>;
30};
31
32&A53_1 {
33	cpu-supply = <&buck2_reg>;
34};
35
36&A53_2 {
37	cpu-supply = <&buck2_reg>;
38};
39
40&A53_3 {
41	cpu-supply = <&buck2_reg>;
42};
43
44&ddrc {
45	operating-points-v2 = <&ddrc_opp_table>;
46
47	ddrc_opp_table: opp-table {
48		compatible = "operating-points-v2";
49
50		opp-25M {
51			opp-hz = /bits/ 64 <25000000>;
52		};
53
54		opp-100M {
55			opp-hz = /bits/ 64 <100000000>;
56		};
57
58		opp-750M {
59			opp-hz = /bits/ 64 <750000000>;
60		};
61	};
62};
63
64&fec1 {
65	pinctrl-names = "default";
66	pinctrl-0 = <&pinctrl_fec1>;
67	phy-mode = "rgmii-id";
68	phy-handle = <&ethphy0>;
69	fsl,magic-packet;
70	status = "okay";
71
72	mdio {
73		#address-cells = <1>;
74		#size-cells = <0>;
75
76		ethphy0: ethernet-phy@0 {
77			compatible = "ethernet-phy-ieee802.3-c22";
78			reg = <0>;
79		};
80	};
81};
82
83&flexspi {
84	pinctrl-names = "default";
85	pinctrl-0 = <&pinctrl_flexspi>;
86	status = "okay";
87
88	flash@0 {
89		reg = <0>;
90		#address-cells = <1>;
91		#size-cells = <1>;
92		compatible = "jedec,spi-nor";
93		spi-max-frequency = <80000000>;
94		spi-tx-bus-width = <4>;
95		spi-rx-bus-width = <4>;
96	};
97};
98
99&i2c1 {
100	clock-frequency = <400000>;
101	pinctrl-names = "default";
102	pinctrl-0 = <&pinctrl_i2c1>;
103	status = "okay";
104
105	pmic@4b {
106		compatible = "rohm,bd71847";
107		reg = <0x4b>;
108		pinctrl-0 = <&pinctrl_pmic>;
109		interrupt-parent = <&gpio1>;
110		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
111		rohm,reset-snvs-powered;
112
113		regulators {
114			buck1_reg: BUCK1 {
115				regulator-name = "buck1";
116				regulator-min-microvolt = <700000>;
117				regulator-max-microvolt = <1300000>;
118				regulator-boot-on;
119				regulator-always-on;
120				regulator-ramp-delay = <1250>;
121			};
122
123			buck2_reg: BUCK2 {
124				regulator-name = "buck2";
125				regulator-min-microvolt = <700000>;
126				regulator-max-microvolt = <1300000>;
127				regulator-boot-on;
128				regulator-always-on;
129				regulator-ramp-delay = <1250>;
130				rohm,dvs-run-voltage = <1000000>;
131				rohm,dvs-idle-voltage = <900000>;
132			};
133
134			buck3_reg: BUCK3 {
135				// BUCK5 in datasheet
136				regulator-name = "buck3";
137				regulator-min-microvolt = <700000>;
138				regulator-max-microvolt = <1350000>;
139				regulator-boot-on;
140				regulator-always-on;
141			};
142
143			buck4_reg: BUCK4 {
144				// BUCK6 in datasheet
145				regulator-name = "buck4";
146				regulator-min-microvolt = <3000000>;
147				regulator-max-microvolt = <3300000>;
148				regulator-boot-on;
149				regulator-always-on;
150			};
151
152			buck5_reg: BUCK5 {
153				// BUCK7 in datasheet
154				regulator-name = "buck5";
155				regulator-min-microvolt = <1605000>;
156				regulator-max-microvolt = <1995000>;
157				regulator-boot-on;
158				regulator-always-on;
159			};
160
161			buck6_reg: BUCK6 {
162				// BUCK8 in datasheet
163				regulator-name = "buck6";
164				regulator-min-microvolt = <800000>;
165				regulator-max-microvolt = <1400000>;
166				regulator-boot-on;
167				regulator-always-on;
168			};
169
170			ldo1_reg: LDO1 {
171				regulator-name = "ldo1";
172				regulator-min-microvolt = <1600000>;
173				regulator-max-microvolt = <3300000>;
174				regulator-boot-on;
175				regulator-always-on;
176			};
177
178			ldo2_reg: LDO2 {
179				regulator-name = "ldo2";
180				regulator-min-microvolt = <800000>;
181				regulator-max-microvolt = <900000>;
182				regulator-boot-on;
183				regulator-always-on;
184			};
185
186			ldo3_reg: LDO3 {
187				regulator-name = "ldo3";
188				regulator-min-microvolt = <1800000>;
189				regulator-max-microvolt = <3300000>;
190				regulator-boot-on;
191				regulator-always-on;
192			};
193
194			ldo4_reg: LDO4 {
195				regulator-name = "ldo4";
196				regulator-min-microvolt = <900000>;
197				regulator-max-microvolt = <1800000>;
198				regulator-boot-on;
199				regulator-always-on;
200			};
201
202			ldo6_reg: LDO6 {
203				regulator-name = "ldo6";
204				regulator-min-microvolt = <900000>;
205				regulator-max-microvolt = <1800000>;
206				regulator-boot-on;
207				regulator-always-on;
208			};
209		};
210	};
211};
212
213&i2c3 {
214	clock-frequency = <400000>;
215	pinctrl-names = "default";
216	pinctrl-0 = <&pinctrl_i2c3>;
217	status = "okay";
218
219	eeprom@50 {
220		compatible = "microchip,24c64", "atmel,24c64";
221		pagesize = <32>;
222		read-only;	/* Manufacturing EEPROM programmed at factory */
223		reg = <0x50>;
224	};
225
226	rtc: rtc@51 {
227		compatible = "nxp,pcf85263";
228		reg = <0x51>;
229	};
230};
231
232&uart1 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_uart1>;
235	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
236	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
237	uart-has-rtscts;
238	status = "okay";
239
240	bluetooth {
241		compatible = "brcm,bcm43438-bt";
242		shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
243		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
244		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
245		clocks = <&osc_32k>;
246		clock-names = "extclk";
247	};
248};
249
250&usdhc1 {
251	#address-cells = <1>;
252	#size-cells = <0>;
253	pinctrl-names = "default";
254	pinctrl-0 = <&pinctrl_usdhc1>;
255	bus-width = <4>;
256	non-removable;
257	cap-power-off-card;
258	pm-ignore-notify;
259	keep-power-in-suspend;
260	mmc-pwrseq = <&usdhc1_pwrseq>;
261	status = "okay";
262
263	brcmf: bcrmf@1 {
264		reg = <1>;
265		compatible = "brcm,bcm4329-fmac";
266		pinctrl-names = "default";
267		pinctrl-0 = <&pinctrl_wlan>;
268		interrupt-parent = <&gpio2>;
269		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
270		interrupt-names = "host-wake";
271	};
272};
273
274&usdhc3 {
275	pinctrl-names = "default", "state_100mhz", "state_200mhz";
276	pinctrl-0 = <&pinctrl_usdhc3>;
277	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
278	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
279	bus-width = <8>;
280	non-removable;
281	status = "okay";
282};
283
284&wdog1 {
285	pinctrl-names = "default";
286	pinctrl-0 = <&pinctrl_wdog>;
287	fsl,ext-reset-output;
288	status = "okay";
289};
290
291&iomuxc {
292	pinctrl_fec1: fec1grp {
293		fsl,pins = <
294			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
295			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
296			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
297			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
298			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
299			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
300			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
301			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
302			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
303			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
304			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
305			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
306			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
307			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
308			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
309		>;
310	};
311
312	pinctrl_i2c1: i2c1grp {
313		fsl,pins = <
314			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
315			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
316		>;
317	};
318
319	pinctrl_i2c3: i2c3grp {
320		fsl,pins = <
321			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
322			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
323		>;
324	};
325
326	pinctrl_flexspi: flexspigrp {
327		fsl,pins = <
328			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
329			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
330			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
331			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
332			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
333			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
334		>;
335	};
336
337	pinctrl_pmic: pmicirqgrp {
338		fsl,pins = <
339			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
340		>;
341	};
342
343	pinctrl_uart1: uart1grp {
344		fsl,pins = <
345			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
346			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
347			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
348			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
349			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
350			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x19
351			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x19
352			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
353		>;
354	};
355
356	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
357		fsl,pins = <
358			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
359		>;
360	};
361
362	pinctrl_usdhc1: usdhc1grp {
363		fsl,pins = <
364			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
365			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
366			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
367			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
368			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
369			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
370		>;
371	};
372
373	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
374		fsl,pins = <
375			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
376			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
377			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
378			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
379			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
380			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
381		>;
382	};
383
384	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
385		fsl,pins = <
386			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
387			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
388			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
389			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
390			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
391			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
392		>;
393	};
394
395	pinctrl_usdhc3: usdhc3grp {
396		fsl,pins = <
397			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
398			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
399			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
400			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
401			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
402			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
403			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
404			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
405			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
406			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
407			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
408		>;
409	};
410
411	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
412		fsl,pins = <
413			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
414			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
415			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
416			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
417			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
418			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
419			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
420			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
421			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
422			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
423			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
424		>;
425	};
426
427	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
428		fsl,pins = <
429			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
430			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
431			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
432			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
433			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
434			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
435			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
436			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
437			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
438			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
439			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
440		>;
441	};
442
443	pinctrl_wdog: wdoggrp {
444		fsl,pins = <
445			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
446		>;
447	};
448
449	pinctrl_wlan: wlangrp {
450		fsl,pins = <
451			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x111
452		>;
453	};
454};
455