1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6/ { 7 usdhc1_pwrseq: usdhc1_pwrseq { 8 compatible = "mmc-pwrseq-simple"; 9 pinctrl-names = "default"; 10 pinctrl-0 = <&pinctrl_usdhc1_gpio>; 11 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 12 clocks = <&osc_32k>; 13 clock-names = "ext_clock"; 14 post-power-on-delay-ms = <80>; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21}; 22 23&A53_0 { 24 cpu-supply = <&buck2_reg>; 25}; 26 27&A53_1 { 28 cpu-supply = <&buck2_reg>; 29}; 30 31&A53_2 { 32 cpu-supply = <&buck2_reg>; 33}; 34 35&A53_3 { 36 cpu-supply = <&buck2_reg>; 37}; 38 39&ddrc { 40 operating-points-v2 = <&ddrc_opp_table>; 41 42 ddrc_opp_table: opp-table { 43 compatible = "operating-points-v2"; 44 45 opp-25M { 46 opp-hz = /bits/ 64 <25000000>; 47 }; 48 49 opp-100M { 50 opp-hz = /bits/ 64 <100000000>; 51 }; 52 53 opp-750M { 54 opp-hz = /bits/ 64 <750000000>; 55 }; 56 }; 57}; 58 59&fec1 { 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_fec1>; 62 phy-mode = "rgmii-id"; 63 phy-handle = <ðphy0>; 64 fsl,magic-packet; 65 status = "okay"; 66 67 mdio { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 ethphy0: ethernet-phy@0 { 72 compatible = "ethernet-phy-ieee802.3-c22"; 73 reg = <0>; 74 }; 75 }; 76}; 77 78&flexspi { 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_flexspi>; 81 status = "okay"; 82 83 flash@0 { 84 reg = <0>; 85 #address-cells = <1>; 86 #size-cells = <1>; 87 compatible = "jedec,spi-nor"; 88 spi-max-frequency = <80000000>; 89 spi-tx-bus-width = <4>; 90 spi-rx-bus-width = <4>; 91 }; 92}; 93 94&i2c1 { 95 clock-frequency = <400000>; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_i2c1>; 98 status = "okay"; 99 100 pmic@4b { 101 compatible = "rohm,bd71847"; 102 reg = <0x4b>; 103 pinctrl-0 = <&pinctrl_pmic>; 104 interrupt-parent = <&gpio1>; 105 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 106 rohm,reset-snvs-powered; 107 108 regulators { 109 buck1_reg: BUCK1 { 110 regulator-name = "buck1"; 111 regulator-min-microvolt = <700000>; 112 regulator-max-microvolt = <1300000>; 113 regulator-boot-on; 114 regulator-always-on; 115 regulator-ramp-delay = <1250>; 116 }; 117 118 buck2_reg: BUCK2 { 119 regulator-name = "buck2"; 120 regulator-min-microvolt = <700000>; 121 regulator-max-microvolt = <1300000>; 122 regulator-boot-on; 123 regulator-always-on; 124 regulator-ramp-delay = <1250>; 125 rohm,dvs-run-voltage = <1000000>; 126 rohm,dvs-idle-voltage = <900000>; 127 }; 128 129 buck3_reg: BUCK3 { 130 // BUCK5 in datasheet 131 regulator-name = "buck3"; 132 regulator-min-microvolt = <700000>; 133 regulator-max-microvolt = <1350000>; 134 regulator-boot-on; 135 regulator-always-on; 136 }; 137 138 buck4_reg: BUCK4 { 139 // BUCK6 in datasheet 140 regulator-name = "buck4"; 141 regulator-min-microvolt = <3000000>; 142 regulator-max-microvolt = <3300000>; 143 regulator-boot-on; 144 regulator-always-on; 145 }; 146 147 buck5_reg: BUCK5 { 148 // BUCK7 in datasheet 149 regulator-name = "buck5"; 150 regulator-min-microvolt = <1605000>; 151 regulator-max-microvolt = <1995000>; 152 regulator-boot-on; 153 regulator-always-on; 154 }; 155 156 buck6_reg: BUCK6 { 157 // BUCK8 in datasheet 158 regulator-name = "buck6"; 159 regulator-min-microvolt = <800000>; 160 regulator-max-microvolt = <1400000>; 161 regulator-boot-on; 162 regulator-always-on; 163 }; 164 165 ldo1_reg: LDO1 { 166 regulator-name = "ldo1"; 167 regulator-min-microvolt = <1600000>; 168 regulator-max-microvolt = <3300000>; 169 regulator-boot-on; 170 regulator-always-on; 171 }; 172 173 ldo2_reg: LDO2 { 174 regulator-name = "ldo2"; 175 regulator-min-microvolt = <800000>; 176 regulator-max-microvolt = <900000>; 177 regulator-boot-on; 178 regulator-always-on; 179 }; 180 181 ldo3_reg: LDO3 { 182 regulator-name = "ldo3"; 183 regulator-min-microvolt = <1800000>; 184 regulator-max-microvolt = <3300000>; 185 regulator-boot-on; 186 regulator-always-on; 187 }; 188 189 ldo4_reg: LDO4 { 190 regulator-name = "ldo4"; 191 regulator-min-microvolt = <900000>; 192 regulator-max-microvolt = <1800000>; 193 regulator-boot-on; 194 regulator-always-on; 195 }; 196 197 ldo6_reg: LDO6 { 198 regulator-name = "ldo6"; 199 regulator-min-microvolt = <900000>; 200 regulator-max-microvolt = <1800000>; 201 regulator-boot-on; 202 regulator-always-on; 203 }; 204 }; 205 }; 206}; 207 208&i2c3 { 209 clock-frequency = <400000>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_i2c3>; 212 status = "okay"; 213 214 eeprom@50 { 215 compatible = "microchip,24c64", "atmel,24c64"; 216 pagesize = <32>; 217 read-only; /* Manufacturing EEPROM programmed at factory */ 218 reg = <0x50>; 219 }; 220 221 rtc@51 { 222 compatible = "nxp,pcf85263"; 223 reg = <0x51>; 224 }; 225}; 226 227&uart1 { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_uart1>; 230 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 231 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 232 uart-has-rtscts; 233 status = "okay"; 234 235 bluetooth { 236 compatible = "brcm,bcm43438-bt"; 237 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 238 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 239 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 240 clocks = <&osc_32k>; 241 clock-names = "extclk"; 242 }; 243}; 244 245&usdhc1 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_usdhc1>; 250 bus-width = <4>; 251 non-removable; 252 cap-power-off-card; 253 pm-ignore-notify; 254 keep-power-in-suspend; 255 mmc-pwrseq = <&usdhc1_pwrseq>; 256 status = "okay"; 257 258 brcmf: bcrmf@1 { 259 reg = <1>; 260 compatible = "brcm,bcm4329-fmac"; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_wlan>; 263 interrupt-parent = <&gpio2>; 264 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "host-wake"; 266 }; 267}; 268 269&usdhc3 { 270 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 271 pinctrl-0 = <&pinctrl_usdhc3>; 272 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 273 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 274 bus-width = <8>; 275 non-removable; 276 status = "okay"; 277}; 278 279&wdog1 { 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_wdog>; 282 fsl,ext-reset-output; 283 status = "okay"; 284}; 285 286&iomuxc { 287 pinctrl_fec1: fec1grp { 288 fsl,pins = < 289 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 290 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 291 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 292 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 293 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 294 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 295 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 296 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 297 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 298 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 299 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 300 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 301 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 302 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 303 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 304 >; 305 }; 306 307 pinctrl_i2c1: i2c1grp { 308 fsl,pins = < 309 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 310 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 311 >; 312 }; 313 314 pinctrl_i2c3: i2c3grp { 315 fsl,pins = < 316 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 317 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 318 >; 319 }; 320 321 pinctrl_flexspi: flexspigrp { 322 fsl,pins = < 323 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 324 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 325 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 326 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 327 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 328 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 329 >; 330 }; 331 332 pinctrl_pmic: pmicirqgrp { 333 fsl,pins = < 334 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 335 >; 336 }; 337 338 pinctrl_uart1: uart1grp { 339 fsl,pins = < 340 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 341 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 342 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 343 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 344 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 345 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 346 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 347 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 348 >; 349 }; 350 351 pinctrl_usdhc1_gpio: usdhc1gpiogrp { 352 fsl,pins = < 353 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 354 >; 355 }; 356 357 pinctrl_usdhc1: usdhc1grp { 358 fsl,pins = < 359 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 360 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 361 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 362 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 363 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 364 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 365 >; 366 }; 367 368 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 369 fsl,pins = < 370 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 371 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 372 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 373 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 374 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 375 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 376 >; 377 }; 378 379 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 380 fsl,pins = < 381 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 382 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 383 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 384 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 385 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 386 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 387 >; 388 }; 389 390 pinctrl_usdhc3: usdhc3grp { 391 fsl,pins = < 392 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 393 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 394 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 395 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 396 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 397 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 398 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 399 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 400 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 401 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 402 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 403 >; 404 }; 405 406 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 407 fsl,pins = < 408 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 409 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 410 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 411 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 412 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 413 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 414 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 415 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 416 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 417 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 418 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 419 >; 420 }; 421 422 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 423 fsl,pins = < 424 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 425 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 426 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 427 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 428 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 429 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 430 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 431 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 432 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 433 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 434 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 435 >; 436 }; 437 438 pinctrl_wdog: wdoggrp { 439 fsl,pins = < 440 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 441 >; 442 }; 443 444 pinctrl_wlan: wlangrp { 445 fsl,pins = < 446 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 447 >; 448 }; 449}; 450