1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6/ { 7 usdhc1_pwrseq: usdhc1_pwrseq { 8 compatible = "mmc-pwrseq-simple"; 9 pinctrl-names = "default"; 10 pinctrl-0 = <&pinctrl_usdhc1_gpio>; 11 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 12 clocks = <&osc_32k>; 13 clock-names = "ext_clock"; 14 post-power-on-delay-ms = <80>; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21}; 22 23&A53_0 { 24 cpu-supply = <&buck2_reg>; 25}; 26 27&A53_1 { 28 cpu-supply = <&buck2_reg>; 29}; 30 31&A53_2 { 32 cpu-supply = <&buck2_reg>; 33}; 34 35&A53_3 { 36 cpu-supply = <&buck2_reg>; 37}; 38 39&ddrc { 40 operating-points-v2 = <&ddrc_opp_table>; 41 42 ddrc_opp_table: opp-table { 43 compatible = "operating-points-v2"; 44 45 opp-25M { 46 opp-hz = /bits/ 64 <25000000>; 47 }; 48 49 opp-100M { 50 opp-hz = /bits/ 64 <100000000>; 51 }; 52 53 opp-750M { 54 opp-hz = /bits/ 64 <750000000>; 55 }; 56 }; 57}; 58 59&fec1 { 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_fec1>; 62 phy-mode = "rgmii-id"; 63 phy-handle = <ðphy0>; 64 fsl,magic-packet; 65 status = "okay"; 66 67 mdio { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 ethphy0: ethernet-phy@0 { 72 compatible = "ethernet-phy-ieee802.3-c22"; 73 reg = <0>; 74 }; 75 }; 76}; 77 78&i2c1 { 79 clock-frequency = <400000>; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_i2c1>; 82 status = "okay"; 83 84 pmic@4b { 85 compatible = "rohm,bd71847"; 86 reg = <0x4b>; 87 pinctrl-0 = <&pinctrl_pmic>; 88 interrupt-parent = <&gpio1>; 89 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 90 rohm,reset-snvs-powered; 91 92 regulators { 93 buck1_reg: BUCK1 { 94 regulator-name = "buck1"; 95 regulator-min-microvolt = <700000>; 96 regulator-max-microvolt = <1300000>; 97 regulator-boot-on; 98 regulator-always-on; 99 regulator-ramp-delay = <1250>; 100 }; 101 102 buck2_reg: BUCK2 { 103 regulator-name = "buck2"; 104 regulator-min-microvolt = <700000>; 105 regulator-max-microvolt = <1300000>; 106 regulator-boot-on; 107 regulator-always-on; 108 regulator-ramp-delay = <1250>; 109 rohm,dvs-run-voltage = <1000000>; 110 rohm,dvs-idle-voltage = <900000>; 111 }; 112 113 buck3_reg: BUCK3 { 114 // BUCK5 in datasheet 115 regulator-name = "buck3"; 116 regulator-min-microvolt = <700000>; 117 regulator-max-microvolt = <1350000>; 118 regulator-boot-on; 119 regulator-always-on; 120 }; 121 122 buck4_reg: BUCK4 { 123 // BUCK6 in datasheet 124 regulator-name = "buck4"; 125 regulator-min-microvolt = <3000000>; 126 regulator-max-microvolt = <3300000>; 127 regulator-boot-on; 128 regulator-always-on; 129 }; 130 131 buck5_reg: BUCK5 { 132 // BUCK7 in datasheet 133 regulator-name = "buck5"; 134 regulator-min-microvolt = <1605000>; 135 regulator-max-microvolt = <1995000>; 136 regulator-boot-on; 137 regulator-always-on; 138 }; 139 140 buck6_reg: BUCK6 { 141 // BUCK8 in datasheet 142 regulator-name = "buck6"; 143 regulator-min-microvolt = <800000>; 144 regulator-max-microvolt = <1400000>; 145 regulator-boot-on; 146 regulator-always-on; 147 }; 148 149 ldo1_reg: LDO1 { 150 regulator-name = "ldo1"; 151 regulator-min-microvolt = <1600000>; 152 regulator-max-microvolt = <3300000>; 153 regulator-boot-on; 154 regulator-always-on; 155 }; 156 157 ldo2_reg: LDO2 { 158 regulator-name = "ldo2"; 159 regulator-min-microvolt = <800000>; 160 regulator-max-microvolt = <900000>; 161 regulator-boot-on; 162 regulator-always-on; 163 }; 164 165 ldo3_reg: LDO3 { 166 regulator-name = "ldo3"; 167 regulator-min-microvolt = <1800000>; 168 regulator-max-microvolt = <3300000>; 169 regulator-boot-on; 170 regulator-always-on; 171 }; 172 173 ldo4_reg: LDO4 { 174 regulator-name = "ldo4"; 175 regulator-min-microvolt = <900000>; 176 regulator-max-microvolt = <1800000>; 177 regulator-boot-on; 178 regulator-always-on; 179 }; 180 181 ldo6_reg: LDO6 { 182 regulator-name = "ldo6"; 183 regulator-min-microvolt = <900000>; 184 regulator-max-microvolt = <1800000>; 185 regulator-boot-on; 186 regulator-always-on; 187 }; 188 }; 189 }; 190}; 191 192&i2c3 { 193 clock-frequency = <400000>; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_i2c3>; 196 status = "okay"; 197 198 eeprom@50 { 199 compatible = "microchip,24c64", "atmel,24c64"; 200 pagesize = <32>; 201 read-only; /* Manufacturing EEPROM programmed at factory */ 202 reg = <0x50>; 203 }; 204 205 rtc@51 { 206 compatible = "nxp,pcf85263"; 207 reg = <0x51>; 208 }; 209}; 210 211&uart1 { 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_uart1>; 214 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 215 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 216 uart-has-rtscts; 217 status = "okay"; 218 219 bluetooth { 220 compatible = "brcm,bcm43438-bt"; 221 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 222 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 223 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 224 clocks = <&osc_32k>; 225 clock-names = "extclk"; 226 }; 227}; 228 229&usdhc1 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_usdhc1>; 234 bus-width = <4>; 235 non-removable; 236 cap-power-off-card; 237 pm-ignore-notify; 238 keep-power-in-suspend; 239 mmc-pwrseq = <&usdhc1_pwrseq>; 240 status = "okay"; 241 242 brcmf: bcrmf@1 { 243 reg = <1>; 244 compatible = "brcm,bcm4329-fmac"; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_wlan>; 247 interrupt-parent = <&gpio2>; 248 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-names = "host-wake"; 250 }; 251}; 252 253&usdhc3 { 254 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 255 pinctrl-0 = <&pinctrl_usdhc3>; 256 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 257 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 258 bus-width = <8>; 259 non-removable; 260 status = "okay"; 261}; 262 263&wdog1 { 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_wdog>; 266 fsl,ext-reset-output; 267 status = "okay"; 268}; 269 270&iomuxc { 271 pinctrl_fec1: fec1grp { 272 fsl,pins = < 273 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 274 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 275 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 276 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 277 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 278 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 279 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 280 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 281 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 282 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 283 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 284 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 285 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 286 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 287 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 288 >; 289 }; 290 291 pinctrl_i2c1: i2c1grp { 292 fsl,pins = < 293 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 294 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 295 >; 296 }; 297 298 pinctrl_i2c3: i2c3grp { 299 fsl,pins = < 300 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 301 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 302 >; 303 }; 304 305 pinctrl_pmic: pmicirqgrp { 306 fsl,pins = < 307 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 308 >; 309 }; 310 311 pinctrl_uart1: uart1grp { 312 fsl,pins = < 313 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 314 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 315 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 316 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 317 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 318 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 319 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 320 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 321 >; 322 }; 323 324 pinctrl_usdhc1_gpio: usdhc1gpiogrp { 325 fsl,pins = < 326 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 327 >; 328 }; 329 330 pinctrl_usdhc1: usdhc1grp { 331 fsl,pins = < 332 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 333 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 334 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 335 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 336 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 337 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 338 >; 339 }; 340 341 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 342 fsl,pins = < 343 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 344 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 345 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 346 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 347 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 348 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 349 >; 350 }; 351 352 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 353 fsl,pins = < 354 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 355 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 356 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 357 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 358 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 359 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 360 >; 361 }; 362 363 pinctrl_usdhc3: usdhc3grp { 364 fsl,pins = < 365 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 366 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 367 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 368 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 369 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 370 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 371 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 372 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 373 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 374 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 375 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 376 >; 377 }; 378 379 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 380 fsl,pins = < 381 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 382 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 383 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 384 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 385 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 386 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 387 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 388 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 389 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 390 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 391 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 392 >; 393 }; 394 395 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 396 fsl,pins = < 397 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 398 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 399 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 400 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 401 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 402 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 403 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 404 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 405 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 406 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 407 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 408 >; 409 }; 410 411 pinctrl_wdog: wdoggrp { 412 fsl,pins = < 413 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 414 >; 415 }; 416 417 pinctrl_wlan: wlangrp { 418 fsl,pins = < 419 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 420 >; 421 }; 422}; 423