1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6/ {
7	aliases {
8		rtc0 = &rtc;
9		rtc1 = &snvs_rtc;
10	};
11
12	usdhc1_pwrseq: usdhc1_pwrseq {
13		compatible = "mmc-pwrseq-simple";
14		pinctrl-names = "default";
15		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
16		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
17		clocks = <&osc_32k>;
18		clock-names = "ext_clock";
19		post-power-on-delay-ms = <80>;
20	};
21
22	memory@40000000 {
23		device_type = "memory";
24		reg = <0x0 0x40000000 0 0x80000000>;
25	};
26};
27
28&A53_0 {
29	cpu-supply = <&buck2_reg>;
30};
31
32&A53_1 {
33	cpu-supply = <&buck2_reg>;
34};
35
36&A53_2 {
37	cpu-supply = <&buck2_reg>;
38};
39
40&A53_3 {
41	cpu-supply = <&buck2_reg>;
42};
43
44&ddrc {
45	operating-points-v2 = <&ddrc_opp_table>;
46
47	ddrc_opp_table: opp-table {
48		compatible = "operating-points-v2";
49
50		opp-25M {
51			opp-hz = /bits/ 64 <25000000>;
52		};
53
54		opp-100M {
55			opp-hz = /bits/ 64 <100000000>;
56		};
57
58		opp-750M {
59			opp-hz = /bits/ 64 <750000000>;
60		};
61	};
62};
63
64&fec1 {
65	pinctrl-names = "default";
66	pinctrl-0 = <&pinctrl_fec1>;
67	phy-mode = "rgmii-id";
68	phy-handle = <&ethphy0>;
69	fsl,magic-packet;
70	status = "okay";
71
72	mdio {
73		#address-cells = <1>;
74		#size-cells = <0>;
75
76		ethphy0: ethernet-phy@0 {
77			compatible = "ethernet-phy-ieee802.3-c22";
78			reg = <0>;
79		};
80	};
81};
82
83&flexspi {
84	pinctrl-names = "default";
85	pinctrl-0 = <&pinctrl_flexspi>;
86	status = "okay";
87
88	flash@0 {
89		reg = <0>;
90		#address-cells = <1>;
91		#size-cells = <1>;
92		compatible = "jedec,spi-nor";
93		spi-max-frequency = <80000000>;
94		spi-tx-bus-width = <4>;
95		spi-rx-bus-width = <4>;
96	};
97};
98
99&i2c1 {
100	clock-frequency = <400000>;
101	pinctrl-names = "default";
102	pinctrl-0 = <&pinctrl_i2c1>;
103	status = "okay";
104
105	pmic@4b {
106		compatible = "rohm,bd71847";
107		reg = <0x4b>;
108		pinctrl-0 = <&pinctrl_pmic>;
109		interrupt-parent = <&gpio1>;
110		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
111		rohm,reset-snvs-powered;
112
113		#clock-cells = <0>;
114		clocks = <&osc_32k 0>;
115		clock-output-names = "clk-32k-out";
116
117		regulators {
118			buck1_reg: BUCK1 {
119				regulator-name = "buck1";
120				regulator-min-microvolt = <700000>;
121				regulator-max-microvolt = <1300000>;
122				regulator-boot-on;
123				regulator-always-on;
124				regulator-ramp-delay = <1250>;
125			};
126
127			buck2_reg: BUCK2 {
128				regulator-name = "buck2";
129				regulator-min-microvolt = <700000>;
130				regulator-max-microvolt = <1300000>;
131				regulator-boot-on;
132				regulator-always-on;
133				regulator-ramp-delay = <1250>;
134				rohm,dvs-run-voltage = <1000000>;
135				rohm,dvs-idle-voltage = <900000>;
136			};
137
138			buck3_reg: BUCK3 {
139				// BUCK5 in datasheet
140				regulator-name = "buck3";
141				regulator-min-microvolt = <700000>;
142				regulator-max-microvolt = <1350000>;
143				regulator-boot-on;
144				regulator-always-on;
145			};
146
147			buck4_reg: BUCK4 {
148				// BUCK6 in datasheet
149				regulator-name = "buck4";
150				regulator-min-microvolt = <3000000>;
151				regulator-max-microvolt = <3300000>;
152				regulator-boot-on;
153				regulator-always-on;
154			};
155
156			buck5_reg: BUCK5 {
157				// BUCK7 in datasheet
158				regulator-name = "buck5";
159				regulator-min-microvolt = <1605000>;
160				regulator-max-microvolt = <1995000>;
161				regulator-boot-on;
162				regulator-always-on;
163			};
164
165			buck6_reg: BUCK6 {
166				// BUCK8 in datasheet
167				regulator-name = "buck6";
168				regulator-min-microvolt = <800000>;
169				regulator-max-microvolt = <1400000>;
170				regulator-boot-on;
171				regulator-always-on;
172			};
173
174			ldo1_reg: LDO1 {
175				regulator-name = "ldo1";
176				regulator-min-microvolt = <1600000>;
177				regulator-max-microvolt = <3300000>;
178				regulator-boot-on;
179				regulator-always-on;
180			};
181
182			ldo2_reg: LDO2 {
183				regulator-name = "ldo2";
184				regulator-min-microvolt = <800000>;
185				regulator-max-microvolt = <900000>;
186				regulator-boot-on;
187				regulator-always-on;
188			};
189
190			ldo3_reg: LDO3 {
191				regulator-name = "ldo3";
192				regulator-min-microvolt = <1800000>;
193				regulator-max-microvolt = <3300000>;
194				regulator-boot-on;
195				regulator-always-on;
196			};
197
198			ldo4_reg: LDO4 {
199				regulator-name = "ldo4";
200				regulator-min-microvolt = <900000>;
201				regulator-max-microvolt = <1800000>;
202				regulator-boot-on;
203				regulator-always-on;
204			};
205
206			ldo6_reg: LDO6 {
207				regulator-name = "ldo6";
208				regulator-min-microvolt = <900000>;
209				regulator-max-microvolt = <1800000>;
210				regulator-boot-on;
211				regulator-always-on;
212			};
213		};
214	};
215};
216
217&i2c3 {
218	clock-frequency = <400000>;
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_i2c3>;
221	status = "okay";
222
223	eeprom@50 {
224		compatible = "microchip,24c64", "atmel,24c64";
225		pagesize = <32>;
226		read-only;	/* Manufacturing EEPROM programmed at factory */
227		reg = <0x50>;
228	};
229
230	rtc: rtc@51 {
231		compatible = "nxp,pcf85263";
232		reg = <0x51>;
233	};
234};
235
236&uart1 {
237	pinctrl-names = "default";
238	pinctrl-0 = <&pinctrl_uart1>;
239	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
240	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
241	uart-has-rtscts;
242	status = "okay";
243
244	bluetooth {
245		compatible = "brcm,bcm43438-bt";
246		shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
247		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
248		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
249		clocks = <&osc_32k>;
250		clock-names = "extclk";
251	};
252};
253
254&usdhc1 {
255	#address-cells = <1>;
256	#size-cells = <0>;
257	pinctrl-names = "default";
258	pinctrl-0 = <&pinctrl_usdhc1>;
259	bus-width = <4>;
260	non-removable;
261	cap-power-off-card;
262	pm-ignore-notify;
263	keep-power-in-suspend;
264	mmc-pwrseq = <&usdhc1_pwrseq>;
265	status = "okay";
266
267	brcmf: bcrmf@1 {
268		reg = <1>;
269		compatible = "brcm,bcm4329-fmac";
270		pinctrl-names = "default";
271		pinctrl-0 = <&pinctrl_wlan>;
272		interrupt-parent = <&gpio2>;
273		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
274		interrupt-names = "host-wake";
275	};
276};
277
278&usdhc3 {
279	pinctrl-names = "default", "state_100mhz", "state_200mhz";
280	pinctrl-0 = <&pinctrl_usdhc3>;
281	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
282	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
283	bus-width = <8>;
284	non-removable;
285	status = "okay";
286};
287
288&wdog1 {
289	pinctrl-names = "default";
290	pinctrl-0 = <&pinctrl_wdog>;
291	fsl,ext-reset-output;
292	status = "okay";
293};
294
295&iomuxc {
296	pinctrl_fec1: fec1grp {
297		fsl,pins = <
298			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
299			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
300			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
301			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
302			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
303			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
304			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
305			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
306			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
307			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
308			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
309			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
310			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
311			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
312			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
313		>;
314	};
315
316	pinctrl_i2c1: i2c1grp {
317		fsl,pins = <
318			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
319			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
320		>;
321	};
322
323	pinctrl_i2c3: i2c3grp {
324		fsl,pins = <
325			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
326			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
327		>;
328	};
329
330	pinctrl_flexspi: flexspigrp {
331		fsl,pins = <
332			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
333			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
334			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
335			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
336			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
337			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
338		>;
339	};
340
341	pinctrl_pmic: pmicirqgrp {
342		fsl,pins = <
343			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
344		>;
345	};
346
347	pinctrl_uart1: uart1grp {
348		fsl,pins = <
349			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
350			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
351			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
352			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
353			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
354			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x19
355			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x19
356			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
357		>;
358	};
359
360	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
361		fsl,pins = <
362			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
363		>;
364	};
365
366	pinctrl_usdhc1: usdhc1grp {
367		fsl,pins = <
368			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
369			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
370			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
371			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
372			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
373			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
374		>;
375	};
376
377	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
378		fsl,pins = <
379			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
380			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
381			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
382			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
383			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
384			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
385		>;
386	};
387
388	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
389		fsl,pins = <
390			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
391			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
392			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
393			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
394			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
395			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
396		>;
397	};
398
399	pinctrl_usdhc3: usdhc3grp {
400		fsl,pins = <
401			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
402			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
403			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
404			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
405			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
406			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
407			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
408			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
409			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
410			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
411			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
412		>;
413	};
414
415	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
416		fsl,pins = <
417			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
418			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
419			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
420			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
421			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
422			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
423			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
424			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
425			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
426			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
427			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
428		>;
429	};
430
431	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
432		fsl,pins = <
433			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
434			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
435			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
436			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
437			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
438			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
439			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
440			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
441			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
442			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
443			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
444		>;
445	};
446
447	pinctrl_wdog: wdoggrp {
448		fsl,pins = <
449			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
450		>;
451	};
452
453	pinctrl_wlan: wlangrp {
454		fsl,pins = <
455			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x111
456		>;
457	};
458};
459