1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6/ { 7 usdhc1_pwrseq: usdhc1_pwrseq { 8 compatible = "mmc-pwrseq-simple"; 9 pinctrl-names = "default"; 10 pinctrl-0 = <&pinctrl_usdhc1_gpio>; 11 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 12 clocks = <&osc_32k>; 13 clock-names = "ext_clock"; 14 post-power-on-delay-ms = <80>; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21}; 22 23&A53_0 { 24 cpu-supply = <&buck2_reg>; 25}; 26 27&ddrc { 28 operating-points-v2 = <&ddrc_opp_table>; 29 30 ddrc_opp_table: opp-table { 31 compatible = "operating-points-v2"; 32 33 opp-25M { 34 opp-hz = /bits/ 64 <25000000>; 35 }; 36 37 opp-100M { 38 opp-hz = /bits/ 64 <100000000>; 39 }; 40 41 opp-750M { 42 opp-hz = /bits/ 64 <750000000>; 43 }; 44 }; 45}; 46 47&fec1 { 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_fec1>; 50 phy-mode = "rgmii-id"; 51 phy-handle = <ðphy0>; 52 fsl,magic-packet; 53 status = "okay"; 54 55 mdio { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 ethphy0: ethernet-phy@0 { 60 compatible = "ethernet-phy-ieee802.3-c22"; 61 reg = <0>; 62 }; 63 }; 64}; 65 66&i2c1 { 67 clock-frequency = <400000>; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_i2c1>; 70 status = "okay"; 71 72 pmic@4b { 73 compatible = "rohm,bd71847"; 74 reg = <0x4b>; 75 pinctrl-0 = <&pinctrl_pmic>; 76 interrupt-parent = <&gpio1>; 77 interrupts = <3 GPIO_ACTIVE_LOW>; 78 rohm,reset-snvs-powered; 79 80 regulators { 81 buck1_reg: BUCK1 { 82 regulator-name = "buck1"; 83 regulator-min-microvolt = <700000>; 84 regulator-max-microvolt = <1300000>; 85 regulator-boot-on; 86 regulator-always-on; 87 regulator-ramp-delay = <1250>; 88 }; 89 90 buck2_reg: BUCK2 { 91 regulator-name = "buck2"; 92 regulator-min-microvolt = <700000>; 93 regulator-max-microvolt = <1300000>; 94 regulator-boot-on; 95 regulator-always-on; 96 regulator-ramp-delay = <1250>; 97 rohm,dvs-run-voltage = <1000000>; 98 rohm,dvs-idle-voltage = <900000>; 99 }; 100 101 buck3_reg: BUCK3 { 102 // BUCK5 in datasheet 103 regulator-name = "buck3"; 104 regulator-min-microvolt = <700000>; 105 regulator-max-microvolt = <1350000>; 106 regulator-boot-on; 107 regulator-always-on; 108 }; 109 110 buck4_reg: BUCK4 { 111 // BUCK6 in datasheet 112 regulator-name = "buck4"; 113 regulator-min-microvolt = <3000000>; 114 regulator-max-microvolt = <3300000>; 115 regulator-boot-on; 116 regulator-always-on; 117 }; 118 119 buck5_reg: BUCK5 { 120 // BUCK7 in datasheet 121 regulator-name = "buck5"; 122 regulator-min-microvolt = <1605000>; 123 regulator-max-microvolt = <1995000>; 124 regulator-boot-on; 125 regulator-always-on; 126 }; 127 128 buck6_reg: BUCK6 { 129 // BUCK8 in datasheet 130 regulator-name = "buck6"; 131 regulator-min-microvolt = <800000>; 132 regulator-max-microvolt = <1400000>; 133 regulator-boot-on; 134 regulator-always-on; 135 }; 136 137 ldo1_reg: LDO1 { 138 regulator-name = "ldo1"; 139 regulator-min-microvolt = <1600000>; 140 regulator-max-microvolt = <3300000>; 141 regulator-boot-on; 142 regulator-always-on; 143 }; 144 145 ldo2_reg: LDO2 { 146 regulator-name = "ldo2"; 147 regulator-min-microvolt = <800000>; 148 regulator-max-microvolt = <900000>; 149 regulator-boot-on; 150 regulator-always-on; 151 }; 152 153 ldo3_reg: LDO3 { 154 regulator-name = "ldo3"; 155 regulator-min-microvolt = <1800000>; 156 regulator-max-microvolt = <3300000>; 157 regulator-boot-on; 158 regulator-always-on; 159 }; 160 161 ldo4_reg: LDO4 { 162 regulator-name = "ldo4"; 163 regulator-min-microvolt = <900000>; 164 regulator-max-microvolt = <1800000>; 165 regulator-boot-on; 166 regulator-always-on; 167 }; 168 169 ldo6_reg: LDO6 { 170 regulator-name = "ldo6"; 171 regulator-min-microvolt = <900000>; 172 regulator-max-microvolt = <1800000>; 173 regulator-boot-on; 174 regulator-always-on; 175 }; 176 }; 177 }; 178}; 179 180&i2c3 { 181 clock-frequency = <400000>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_i2c3>; 184 status = "okay"; 185 186 eeprom@50 { 187 compatible = "microchip,24c64", "atmel,24c64"; 188 pagesize = <32>; 189 read-only; /* Manufacturing EEPROM programmed at factory */ 190 reg = <0x50>; 191 }; 192 193 rtc@51 { 194 compatible = "nxp,pcf85263"; 195 reg = <0x51>; 196 }; 197}; 198 199&uart1 { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_uart1>; 202 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 203 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 204 uart-has-rtscts; 205 status = "okay"; 206 207 bluetooth { 208 compatible = "brcm,bcm43438-bt"; 209 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 210 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 211 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 212 clocks = <&osc_32k>; 213 clock-names = "extclk"; 214 }; 215}; 216 217&usdhc1 { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_usdhc1>; 222 bus-width = <4>; 223 non-removable; 224 cap-power-off-card; 225 pm-ignore-notify; 226 keep-power-in-suspend; 227 mmc-pwrseq = <&usdhc1_pwrseq>; 228 status = "okay"; 229 230 brcmf: bcrmf@1 { 231 reg = <1>; 232 compatible = "brcm,bcm4329-fmac"; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_wlan>; 235 interrupt-parent = <&gpio2>; 236 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-names = "host-wake"; 238 }; 239}; 240 241&usdhc3 { 242 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 243 pinctrl-0 = <&pinctrl_usdhc3>; 244 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 245 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 246 bus-width = <8>; 247 non-removable; 248 status = "okay"; 249}; 250 251&wdog1 { 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_wdog>; 254 fsl,ext-reset-output; 255 status = "okay"; 256}; 257 258&iomuxc { 259 pinctrl_fec1: fec1grp { 260 fsl,pins = < 261 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 262 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 263 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 264 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 265 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 266 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 267 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 268 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 269 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 270 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 271 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 272 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 273 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 274 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 275 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 276 >; 277 }; 278 279 pinctrl_i2c1: i2c1grp { 280 fsl,pins = < 281 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 282 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 283 >; 284 }; 285 286 pinctrl_i2c3: i2c3grp { 287 fsl,pins = < 288 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 289 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 290 >; 291 }; 292 293 pinctrl_pmic: pmicirqgrp { 294 fsl,pins = < 295 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 296 >; 297 }; 298 299 pinctrl_uart1: uart1grp { 300 fsl,pins = < 301 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 302 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 303 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 304 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 305 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 306 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 307 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 308 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 309 >; 310 }; 311 312 pinctrl_usdhc1_gpio: usdhc1gpiogrp { 313 fsl,pins = < 314 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 315 >; 316 }; 317 318 pinctrl_usdhc1: usdhc1grp { 319 fsl,pins = < 320 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 321 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 322 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 323 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 324 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 325 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 326 >; 327 }; 328 329 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 330 fsl,pins = < 331 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 332 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 333 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 334 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 335 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 336 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 337 >; 338 }; 339 340 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 341 fsl,pins = < 342 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 343 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 344 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 345 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 346 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 347 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 348 >; 349 }; 350 351 pinctrl_usdhc3: usdhc3grp { 352 fsl,pins = < 353 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 354 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 355 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 356 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 357 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 358 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 359 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 360 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 361 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 362 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 363 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 364 >; 365 }; 366 367 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 368 fsl,pins = < 369 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 370 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 371 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 372 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 373 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 374 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 375 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 376 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 377 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 378 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 379 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 380 >; 381 }; 382 383 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 384 fsl,pins = < 385 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 386 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 387 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 388 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 389 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 390 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 391 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 392 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 393 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 394 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 395 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 396 >; 397 }; 398 399 pinctrl_wdog: wdoggrp { 400 fsl,pins = < 401 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 402 >; 403 }; 404 405 pinctrl_wlan: wlangrp { 406 fsl,pins = < 407 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 408 >; 409 }; 410}; 411