1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6/ { 7 usdhc1_pwrseq: usdhc1_pwrseq { 8 compatible = "mmc-pwrseq-simple"; 9 pinctrl-names = "default"; 10 pinctrl-0 = <&pinctrl_usdhc1_gpio>; 11 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 12 clocks = <&osc_32k>; 13 clock-names = "ext_clock"; 14 post-power-on-delay-ms = <80>; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21}; 22 23&A53_0 { 24 cpu-supply = <&buck2_reg>; 25}; 26 27&ddrc { 28 operating-points-v2 = <&ddrc_opp_table>; 29 30 ddrc_opp_table: opp-table { 31 compatible = "operating-points-v2"; 32 33 opp-25M { 34 opp-hz = /bits/ 64 <25000000>; 35 }; 36 37 opp-100M { 38 opp-hz = /bits/ 64 <100000000>; 39 }; 40 41 opp-750M { 42 opp-hz = /bits/ 64 <750000000>; 43 }; 44 }; 45}; 46 47&fec1 { 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_fec1>; 50 phy-mode = "rgmii-id"; 51 phy-handle = <ðphy0>; 52 fsl,magic-packet; 53 status = "okay"; 54 55 mdio { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 ethphy0: ethernet-phy@0 { 60 compatible = "ethernet-phy-ieee802.3-c22"; 61 reg = <0>; 62 }; 63 }; 64}; 65 66&i2c1 { 67 clock-frequency = <400000>; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_i2c1>; 70 status = "okay"; 71 72 pmic@4b { 73 compatible = "rohm,bd71847"; 74 reg = <0x4b>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_pmic>; 77 interrupt-parent = <&gpio1>; 78 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 79 rohm,reset-snvs-powered; 80 81 regulators { 82 buck1_reg: BUCK1 { 83 regulator-name = "buck1"; 84 regulator-min-microvolt = <700000>; 85 regulator-max-microvolt = <1300000>; 86 regulator-boot-on; 87 regulator-always-on; 88 regulator-ramp-delay = <1250>; 89 }; 90 91 buck2_reg: BUCK2 { 92 regulator-name = "buck2"; 93 regulator-min-microvolt = <700000>; 94 regulator-max-microvolt = <1300000>; 95 regulator-boot-on; 96 regulator-always-on; 97 regulator-ramp-delay = <1250>; 98 rohm,dvs-run-voltage = <1000000>; 99 rohm,dvs-idle-voltage = <900000>; 100 }; 101 102 buck3_reg: BUCK3 { 103 // BUCK5 in datasheet 104 regulator-name = "buck3"; 105 regulator-min-microvolt = <700000>; 106 regulator-max-microvolt = <1350000>; 107 regulator-boot-on; 108 regulator-always-on; 109 }; 110 111 buck4_reg: BUCK4 { 112 // BUCK6 in datasheet 113 regulator-name = "buck4"; 114 regulator-min-microvolt = <3000000>; 115 regulator-max-microvolt = <3300000>; 116 regulator-boot-on; 117 regulator-always-on; 118 }; 119 120 buck5_reg: BUCK5 { 121 // BUCK7 in datasheet 122 regulator-name = "buck5"; 123 regulator-min-microvolt = <1605000>; 124 regulator-max-microvolt = <1995000>; 125 regulator-boot-on; 126 regulator-always-on; 127 }; 128 129 buck6_reg: BUCK6 { 130 // BUCK8 in datasheet 131 regulator-name = "buck6"; 132 regulator-min-microvolt = <800000>; 133 regulator-max-microvolt = <1400000>; 134 regulator-boot-on; 135 regulator-always-on; 136 }; 137 138 ldo1_reg: LDO1 { 139 regulator-name = "ldo1"; 140 regulator-min-microvolt = <1600000>; 141 regulator-max-microvolt = <3300000>; 142 regulator-boot-on; 143 regulator-always-on; 144 }; 145 146 ldo2_reg: LDO2 { 147 regulator-name = "ldo2"; 148 regulator-min-microvolt = <800000>; 149 regulator-max-microvolt = <900000>; 150 regulator-boot-on; 151 regulator-always-on; 152 }; 153 154 ldo3_reg: LDO3 { 155 regulator-name = "ldo3"; 156 regulator-min-microvolt = <1800000>; 157 regulator-max-microvolt = <3300000>; 158 regulator-boot-on; 159 regulator-always-on; 160 }; 161 162 ldo4_reg: LDO4 { 163 regulator-name = "ldo4"; 164 regulator-min-microvolt = <900000>; 165 regulator-max-microvolt = <1800000>; 166 regulator-boot-on; 167 regulator-always-on; 168 }; 169 170 ldo6_reg: LDO6 { 171 regulator-name = "ldo6"; 172 regulator-min-microvolt = <900000>; 173 regulator-max-microvolt = <1800000>; 174 regulator-boot-on; 175 regulator-always-on; 176 }; 177 }; 178 }; 179}; 180 181&i2c3 { 182 clock-frequency = <400000>; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_i2c3>; 185 status = "okay"; 186 187 eeprom@50 { 188 compatible = "microchip,24c64", "atmel,24c64"; 189 pagesize = <32>; 190 read-only; /* Manufacturing EEPROM programmed at factory */ 191 reg = <0x50>; 192 }; 193 194 rtc@51 { 195 compatible = "nxp,pcf85263"; 196 reg = <0x51>; 197 }; 198}; 199 200&uart1 { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_uart1>; 203 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 204 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 205 uart-has-rtscts; 206 status = "okay"; 207 208 bluetooth { 209 compatible = "brcm,bcm43438-bt"; 210 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 211 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 212 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 213 clocks = <&osc_32k>; 214 clock-names = "extclk"; 215 }; 216}; 217 218&usdhc1 { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_usdhc1>; 223 bus-width = <4>; 224 non-removable; 225 cap-power-off-card; 226 pm-ignore-notify; 227 keep-power-in-suspend; 228 mmc-pwrseq = <&usdhc1_pwrseq>; 229 status = "okay"; 230 231 brcmf: bcrmf@1 { 232 reg = <1>; 233 compatible = "brcm,bcm4329-fmac"; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_wlan>; 236 interrupt-parent = <&gpio2>; 237 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-names = "host-wake"; 239 }; 240}; 241 242&usdhc3 { 243 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 244 pinctrl-0 = <&pinctrl_usdhc3>; 245 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 246 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 247 bus-width = <8>; 248 non-removable; 249 status = "okay"; 250}; 251 252&wdog1 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_wdog>; 255 fsl,ext-reset-output; 256 status = "okay"; 257}; 258 259&iomuxc { 260 pinctrl_fec1: fec1grp { 261 fsl,pins = < 262 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 263 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 264 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 265 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 266 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 267 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 268 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 269 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 270 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 271 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 272 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 273 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 274 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 275 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 276 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 277 >; 278 }; 279 280 pinctrl_i2c1: i2c1grp { 281 fsl,pins = < 282 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 283 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 284 >; 285 }; 286 287 pinctrl_i2c3: i2c3grp { 288 fsl,pins = < 289 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 290 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 291 >; 292 }; 293 294 pinctrl_pmic: pmicirqgrp { 295 fsl,pins = < 296 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 297 >; 298 }; 299 300 pinctrl_uart1: uart1grp { 301 fsl,pins = < 302 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 303 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 304 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 305 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 306 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 307 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 308 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 309 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 310 >; 311 }; 312 313 pinctrl_usdhc1_gpio: usdhc1gpiogrp { 314 fsl,pins = < 315 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 316 >; 317 }; 318 319 pinctrl_usdhc1: usdhc1grp { 320 fsl,pins = < 321 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 322 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 323 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 324 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 325 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 326 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 327 >; 328 }; 329 330 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 331 fsl,pins = < 332 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 333 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 334 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 335 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 336 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 337 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 338 >; 339 }; 340 341 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 342 fsl,pins = < 343 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 344 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 345 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 346 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 347 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 348 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 349 >; 350 }; 351 352 pinctrl_usdhc3: usdhc3grp { 353 fsl,pins = < 354 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 355 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 356 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 357 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 358 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 359 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 360 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 361 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 362 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 363 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 364 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 365 >; 366 }; 367 368 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 369 fsl,pins = < 370 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 371 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 372 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 373 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 374 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 375 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 376 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 377 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 378 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 379 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 380 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 381 >; 382 }; 383 384 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 385 fsl,pins = < 386 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 387 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 388 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 389 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 390 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 391 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 392 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 393 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 394 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 395 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 396 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 397 >; 398 }; 399 400 pinctrl_wdog: wdoggrp { 401 fsl,pins = < 402 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 403 >; 404 }; 405 406 pinctrl_wlan: wlangrp { 407 fsl,pins = < 408 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 409 >; 410 }; 411}; 412