1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6#include <dt-bindings/clock/imx8-clock.h>
7#include <dt-bindings/firmware/imx/rsrc.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/pinctrl/pads-imx8dxl.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	aliases {
20		ethernet0 = &fec1;
21		ethernet1 = &eqos;
22		gpio0 = &lsio_gpio0;
23		gpio1 = &lsio_gpio1;
24		gpio2 = &lsio_gpio2;
25		gpio3 = &lsio_gpio3;
26		gpio4 = &lsio_gpio4;
27		gpio5 = &lsio_gpio5;
28		gpio6 = &lsio_gpio6;
29		gpio7 = &lsio_gpio7;
30		mu1 = &lsio_mu1;
31	};
32
33	cpus: cpus {
34		#address-cells = <2>;
35		#size-cells = <0>;
36
37		/* We have 1 clusters with 2 Cortex-A35 cores */
38		A35_0: cpu@0 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a35";
41			reg = <0x0 0x0>;
42			enable-method = "psci";
43			next-level-cache = <&A35_L2>;
44			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
45			#cooling-cells = <2>;
46			operating-points-v2 = <&a35_opp_table>;
47		};
48
49		A35_1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a35";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&A35_L2>;
55			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
56			#cooling-cells = <2>;
57			operating-points-v2 = <&a35_opp_table>;
58		};
59
60		A35_L2: l2-cache0 {
61			compatible = "cache";
62			cache-level = <2>;
63		};
64	};
65
66	a35_opp_table: opp-table {
67		compatible = "operating-points-v2";
68		opp-shared;
69
70		opp-900000000 {
71			opp-hz = /bits/ 64 <900000000>;
72			opp-microvolt = <1000000>;
73			clock-latency-ns = <150000>;
74		};
75
76		opp-1200000000 {
77			opp-hz = /bits/ 64 <1200000000>;
78			opp-microvolt = <1100000>;
79			clock-latency-ns = <150000>;
80			opp-suspend;
81		};
82	};
83
84	gic: interrupt-controller@51a00000 {
85		compatible = "arm,gic-v3";
86		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
87		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
88		#interrupt-cells = <3>;
89		interrupt-controller;
90		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
91	};
92
93	reserved-memory {
94		#address-cells = <2>;
95		#size-cells = <2>;
96		ranges;
97
98		dsp_reserved: dsp@92400000 {
99			reg = <0 0x92400000 0 0x2000000>;
100			no-map;
101		};
102	};
103
104	pmu {
105		compatible = "arm,armv8-pmuv3";
106		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
107	};
108
109	psci {
110		compatible = "arm,psci-1.0";
111		method = "smc";
112	};
113
114	system-controller {
115		compatible = "fsl,imx-scu";
116		mbox-names = "tx0",
117			     "rx0",
118			     "gip3";
119		mboxes = <&lsio_mu1 0 0
120			  &lsio_mu1 1 0
121			  &lsio_mu1 3 3>;
122
123		pd: power-controller {
124			compatible = "fsl,scu-pd";
125			#power-domain-cells = <1>;
126			wakeup-irq = <160 163 235 236 237 228 229 230 231 238
127				     239 240 166 169>;
128		};
129
130		clk: clock-controller {
131			compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
132			#clock-cells = <2>;
133			clocks = <&xtal32k &xtal24m>;
134			clock-names = "xtal_32KHz", "xtal_24Mhz";
135		};
136
137		scu_gpio: gpio {
138			compatible = "fsl,imx8qxp-sc-gpio";
139			gpio-controller;
140			#gpio-cells = <2>;
141		};
142
143		iomuxc: pinctrl {
144			compatible = "fsl,imx8dxl-iomuxc";
145		};
146
147		ocotp: ocotp {
148			compatible = "fsl,imx8qxp-scu-ocotp";
149			#address-cells = <1>;
150			#size-cells = <1>;
151
152			fec_mac0: mac@2c4 {
153				reg = <0x2c4 6>;
154			};
155
156			fec_mac1: mac@2c6 {
157				reg = <0x2c6 6>;
158			};
159		};
160
161		rtc: rtc {
162			compatible = "fsl,imx8qxp-sc-rtc";
163		};
164
165		sc_pwrkey: keys {
166			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
167			linux,keycodes = <KEY_POWER>;
168			wakeup-source;
169		};
170
171		watchdog {
172			compatible = "fsl,imx-sc-wdt";
173			timeout-sec = <60>;
174		};
175
176		tsens: thermal-sensor {
177			compatible = "fsl,imx-sc-thermal";
178			#thermal-sensor-cells = <1>;
179		};
180	};
181
182	timer {
183		compatible = "arm,armv8-timer";
184		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
185			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
186			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
187			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
188	};
189
190	thermal_zones: thermal-zones {
191		cpu-thermal0 {
192			polling-delay-passive = <250>;
193			polling-delay = <2000>;
194			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
195
196			trips {
197				cpu_alert0: trip0 {
198					temperature = <107000>;
199					hysteresis = <2000>;
200					type = "passive";
201				};
202				cpu_crit0: trip1 {
203					temperature = <127000>;
204					hysteresis = <2000>;
205					type = "critical";
206				};
207			};
208
209			cooling-maps {
210				map0 {
211					trip = <&cpu_alert0>;
212					cooling-device =
213					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
214					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
215				};
216			};
217		};
218	};
219
220	/* The two values below cannot be changed by the board */
221	xtal32k: clock-xtal32k {
222		compatible = "fixed-clock";
223		#clock-cells = <0>;
224		clock-frequency = <32768>;
225		clock-output-names = "xtal_32KHz";
226	};
227
228	xtal24m: clock-xtal24m {
229		compatible = "fixed-clock";
230		#clock-cells = <0>;
231		clock-frequency = <24000000>;
232		clock-output-names = "xtal_24MHz";
233	};
234
235	/* sorted in register address */
236	#include "imx8-ss-adma.dtsi"
237	#include "imx8-ss-conn.dtsi"
238	#include "imx8-ss-ddr.dtsi"
239	#include "imx8-ss-lsio.dtsi"
240};
241
242#include "imx8dxl-ss-adma.dtsi"
243#include "imx8dxl-ss-conn.dtsi"
244#include "imx8dxl-ss-lsio.dtsi"
245#include "imx8dxl-ss-ddr.dtsi"
246