1*f537ee7fSShenwei Wang// SPDX-License-Identifier: GPL-2.0+ 2*f537ee7fSShenwei Wang/* 3*f537ee7fSShenwei Wang * Copyright 2019~2020, 2022 NXP 4*f537ee7fSShenwei Wang */ 5*f537ee7fSShenwei Wang 6*f537ee7fSShenwei Wang&audio_ipg_clk { 7*f537ee7fSShenwei Wang clock-frequency = <160000000>; 8*f537ee7fSShenwei Wang}; 9*f537ee7fSShenwei Wang 10*f537ee7fSShenwei Wang&dma_ipg_clk { 11*f537ee7fSShenwei Wang clock-frequency = <160000000>; 12*f537ee7fSShenwei Wang}; 13*f537ee7fSShenwei Wang 14*f537ee7fSShenwei Wang&i2c0 { 15*f537ee7fSShenwei Wang compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 16*f537ee7fSShenwei Wang interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 17*f537ee7fSShenwei Wang}; 18*f537ee7fSShenwei Wang 19*f537ee7fSShenwei Wang&i2c1 { 20*f537ee7fSShenwei Wang compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 21*f537ee7fSShenwei Wang interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 22*f537ee7fSShenwei Wang}; 23*f537ee7fSShenwei Wang 24*f537ee7fSShenwei Wang&i2c2 { 25*f537ee7fSShenwei Wang compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 26*f537ee7fSShenwei Wang interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 27*f537ee7fSShenwei Wang}; 28*f537ee7fSShenwei Wang 29*f537ee7fSShenwei Wang&i2c3 { 30*f537ee7fSShenwei Wang compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 31*f537ee7fSShenwei Wang interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 32*f537ee7fSShenwei Wang}; 33*f537ee7fSShenwei Wang 34*f537ee7fSShenwei Wang&lpuart0 { 35*f537ee7fSShenwei Wang compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 36*f537ee7fSShenwei Wang interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 37*f537ee7fSShenwei Wang}; 38*f537ee7fSShenwei Wang 39*f537ee7fSShenwei Wang&lpuart1 { 40*f537ee7fSShenwei Wang compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 41*f537ee7fSShenwei Wang interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 42*f537ee7fSShenwei Wang}; 43*f537ee7fSShenwei Wang 44*f537ee7fSShenwei Wang&lpuart2 { 45*f537ee7fSShenwei Wang compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 46*f537ee7fSShenwei Wang interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 47*f537ee7fSShenwei Wang}; 48*f537ee7fSShenwei Wang 49*f537ee7fSShenwei Wang&lpuart3 { 50*f537ee7fSShenwei Wang compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 51*f537ee7fSShenwei Wang interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 52*f537ee7fSShenwei Wang}; 53