1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2020 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/clock/imx8-lpcg.h>
8#include <dt-bindings/firmware/imx/rsrc.h>
9
10lsio_subsys: bus@5d000000 {
11	compatible = "simple-bus";
12	#address-cells = <1>;
13	#size-cells = <1>;
14	ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
15
16	lsio_mem_clk: clock-lsio-mem {
17		compatible = "fixed-clock";
18		#clock-cells = <0>;
19		clock-frequency = <200000000>;
20		clock-output-names = "lsio_mem_clk";
21	};
22
23	lsio_bus_clk: clock-lsio-bus {
24		compatible = "fixed-clock";
25		#clock-cells = <0>;
26		clock-frequency = <100000000>;
27		clock-output-names = "lsio_bus_clk";
28	};
29
30	lsio_gpio0: gpio@5d080000 {
31		reg = <0x5d080000 0x10000>;
32		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
33		gpio-controller;
34		#gpio-cells = <2>;
35		interrupt-controller;
36		#interrupt-cells = <2>;
37		power-domains = <&pd IMX_SC_R_GPIO_0>;
38	};
39
40	lsio_gpio1: gpio@5d090000 {
41		reg = <0x5d090000 0x10000>;
42		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
43		gpio-controller;
44		#gpio-cells = <2>;
45		interrupt-controller;
46		#interrupt-cells = <2>;
47		power-domains = <&pd IMX_SC_R_GPIO_1>;
48	};
49
50	lsio_gpio2: gpio@5d0a0000 {
51		reg = <0x5d0a0000 0x10000>;
52		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
53		gpio-controller;
54		#gpio-cells = <2>;
55		interrupt-controller;
56		#interrupt-cells = <2>;
57		power-domains = <&pd IMX_SC_R_GPIO_2>;
58	};
59
60	lsio_gpio3: gpio@5d0b0000 {
61		reg = <0x5d0b0000 0x10000>;
62		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
63		gpio-controller;
64		#gpio-cells = <2>;
65		interrupt-controller;
66		#interrupt-cells = <2>;
67		power-domains = <&pd IMX_SC_R_GPIO_3>;
68	};
69
70	lsio_gpio4: gpio@5d0c0000 {
71		reg = <0x5d0c0000 0x10000>;
72		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
73		gpio-controller;
74		#gpio-cells = <2>;
75		interrupt-controller;
76		#interrupt-cells = <2>;
77		power-domains = <&pd IMX_SC_R_GPIO_4>;
78	};
79
80	lsio_gpio5: gpio@5d0d0000 {
81		reg = <0x5d0d0000 0x10000>;
82		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
83		gpio-controller;
84		#gpio-cells = <2>;
85		interrupt-controller;
86		#interrupt-cells = <2>;
87		power-domains = <&pd IMX_SC_R_GPIO_5>;
88	};
89
90	lsio_gpio6: gpio@5d0e0000 {
91		reg = <0x5d0e0000 0x10000>;
92		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
93		gpio-controller;
94		#gpio-cells = <2>;
95		interrupt-controller;
96		#interrupt-cells = <2>;
97		power-domains = <&pd IMX_SC_R_GPIO_6>;
98	};
99
100	lsio_gpio7: gpio@5d0f0000 {
101		reg = <0x5d0f0000 0x10000>;
102		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
103		gpio-controller;
104		#gpio-cells = <2>;
105		interrupt-controller;
106		#interrupt-cells = <2>;
107		power-domains = <&pd IMX_SC_R_GPIO_7>;
108	};
109
110	lsio_mu0: mailbox@5d1b0000 {
111		reg = <0x5d1b0000 0x10000>;
112		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
113		#mbox-cells = <2>;
114		status = "disabled";
115	};
116
117	lsio_mu1: mailbox@5d1c0000 {
118		reg = <0x5d1c0000 0x10000>;
119		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
120		#mbox-cells = <2>;
121	};
122
123	lsio_mu2: mailbox@5d1d0000 {
124		reg = <0x5d1d0000 0x10000>;
125		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
126		#mbox-cells = <2>;
127		status = "disabled";
128	};
129
130	lsio_mu3: mailbox@5d1e0000 {
131		reg = <0x5d1e0000 0x10000>;
132		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
133		#mbox-cells = <2>;
134		status = "disabled";
135	};
136
137	lsio_mu4: mailbox@5d1f0000 {
138		reg = <0x5d1f0000 0x10000>;
139		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
140		#mbox-cells = <2>;
141		status = "disabled";
142	};
143
144	lsio_mu5: mailbox@5d200000 {
145		reg = <0x5d200000 0x10000>;
146		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
147		#mbox-cells = <2>;
148		power-domains = <&pd IMX_SC_R_MU_5A>;
149		status = "disabled";
150	};
151
152	lsio_mu6: mailbox@5d210000 {
153		reg = <0x5d210000 0x10000>;
154		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
155		#mbox-cells = <2>;
156		power-domains = <&pd IMX_SC_R_MU_6A>;
157		status = "disabled";
158	};
159
160	lsio_mu13: mailbox@5d280000 {
161		reg = <0x5d280000 0x10000>;
162		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
163		#mbox-cells = <2>;
164		power-domains = <&pd IMX_SC_R_MU_13A>;
165	};
166
167	/* LPCG clocks */
168	pwm0_lpcg: clock-controller@5d400000 {
169		compatible = "fsl,imx8qxp-lpcg";
170		reg = <0x5d400000 0x10000>;
171		#clock-cells = <1>;
172		clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
173			 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
174			 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
175			 <&lsio_bus_clk>,
176			 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
177		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
178				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
179				<IMX_LPCG_CLK_6>;
180		clock-output-names = "pwm0_lpcg_ipg_clk",
181				     "pwm0_lpcg_ipg_hf_clk",
182				     "pwm0_lpcg_ipg_s_clk",
183				     "pwm0_lpcg_ipg_slv_clk",
184				     "pwm0_lpcg_ipg_mstr_clk";
185		power-domains = <&pd IMX_SC_R_PWM_0>;
186	};
187
188	pwm1_lpcg: clock-controller@5d410000 {
189		compatible = "fsl,imx8qxp-lpcg";
190		reg = <0x5d410000 0x10000>;
191		#clock-cells = <1>;
192		clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
193			 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
194			 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
195			 <&lsio_bus_clk>,
196			 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
197		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
198				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
199				<IMX_LPCG_CLK_6>;
200		clock-output-names = "pwm1_lpcg_ipg_clk",
201				     "pwm1_lpcg_ipg_hf_clk",
202				     "pwm1_lpcg_ipg_s_clk",
203				     "pwm1_lpcg_ipg_slv_clk",
204				     "pwm1_lpcg_ipg_mstr_clk";
205		power-domains = <&pd IMX_SC_R_PWM_1>;
206	};
207
208	pwm2_lpcg: clock-controller@5d420000 {
209		compatible = "fsl,imx8qxp-lpcg";
210		reg = <0x5d420000 0x10000>;
211		#clock-cells = <1>;
212		clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
213			 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
214			 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
215			 <&lsio_bus_clk>,
216			 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
217		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
218				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
219				<IMX_LPCG_CLK_6>;
220		clock-output-names = "pwm2_lpcg_ipg_clk",
221				     "pwm2_lpcg_ipg_hf_clk",
222				     "pwm2_lpcg_ipg_s_clk",
223				     "pwm2_lpcg_ipg_slv_clk",
224				     "pwm2_lpcg_ipg_mstr_clk";
225		power-domains = <&pd IMX_SC_R_PWM_2>;
226	};
227
228	pwm3_lpcg: clock-controller@5d430000 {
229		compatible = "fsl,imx8qxp-lpcg";
230		reg = <0x5d430000 0x10000>;
231		#clock-cells = <1>;
232		clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
233			 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
234			 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
235			 <&lsio_bus_clk>,
236			 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
237		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
238				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
239				<IMX_LPCG_CLK_6>;
240		clock-output-names = "pwm3_lpcg_ipg_clk",
241				     "pwm3_lpcg_ipg_hf_clk",
242				     "pwm3_lpcg_ipg_s_clk",
243				     "pwm3_lpcg_ipg_slv_clk",
244				     "pwm3_lpcg_ipg_mstr_clk";
245		power-domains = <&pd IMX_SC_R_PWM_3>;
246	};
247
248	pwm4_lpcg: clock-controller@5d440000 {
249		compatible = "fsl,imx8qxp-lpcg";
250		reg = <0x5d440000 0x10000>;
251		#clock-cells = <1>;
252		clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
253			 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
254			 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
255			 <&lsio_bus_clk>,
256			 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
257		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
258				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
259				<IMX_LPCG_CLK_6>;
260		clock-output-names = "pwm4_lpcg_ipg_clk",
261				     "pwm4_lpcg_ipg_hf_clk",
262				     "pwm4_lpcg_ipg_s_clk",
263				     "pwm4_lpcg_ipg_slv_clk",
264				     "pwm4_lpcg_ipg_mstr_clk";
265		power-domains = <&pd IMX_SC_R_PWM_4>;
266	};
267
268	pwm5_lpcg: clock-controller@5d450000 {
269		compatible = "fsl,imx8qxp-lpcg";
270		reg = <0x5d450000 0x10000>;
271		#clock-cells = <1>;
272		clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
273			 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
274			 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
275			 <&lsio_bus_clk>,
276			 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
277		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
278				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
279				<IMX_LPCG_CLK_6>;
280		clock-output-names = "pwm5_lpcg_ipg_clk",
281				     "pwm5_lpcg_ipg_hf_clk",
282				     "pwm5_lpcg_ipg_s_clk",
283				     "pwm5_lpcg_ipg_slv_clk",
284				     "pwm5_lpcg_ipg_mstr_clk";
285		power-domains = <&pd IMX_SC_R_PWM_5>;
286	};
287
288	pwm6_lpcg: clock-controller@5d460000 {
289		compatible = "fsl,imx8qxp-lpcg";
290		reg = <0x5d460000 0x10000>;
291		#clock-cells = <1>;
292		clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
293			 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
294			 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
295			 <&lsio_bus_clk>,
296			 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
297		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
298				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
299				<IMX_LPCG_CLK_6>;
300		clock-output-names = "pwm6_lpcg_ipg_clk",
301				     "pwm6_lpcg_ipg_hf_clk",
302				     "pwm6_lpcg_ipg_s_clk",
303				     "pwm6_lpcg_ipg_slv_clk",
304				     "pwm6_lpcg_ipg_mstr_clk";
305		power-domains = <&pd IMX_SC_R_PWM_6>;
306	};
307
308	pwm7_lpcg: clock-controller@5d470000 {
309		compatible = "fsl,imx8qxp-lpcg";
310		reg = <0x5d470000 0x10000>;
311		#clock-cells = <1>;
312		clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
313			 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
314			 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
315			 <&lsio_bus_clk>,
316			 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
317		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
318				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
319				<IMX_LPCG_CLK_6>;
320		clock-output-names = "pwm7_lpcg_ipg_clk",
321				     "pwm7_lpcg_ipg_hf_clk",
322				     "pwm7_lpcg_ipg_s_clk",
323				     "pwm7_lpcg_ipg_slv_clk",
324				     "pwm7_lpcg_ipg_mstr_clk";
325		power-domains = <&pd IMX_SC_R_PWM_7>;
326	};
327};
328