1*5bb27917SMirela Rabulea// SPDX-License-Identifier: GPL-2.0+ 2*5bb27917SMirela Rabulea/* 3*5bb27917SMirela Rabulea * Copyright 2019-2021 NXP 4*5bb27917SMirela Rabulea * Zhou Guoniu <guoniu.zhou@nxp.com> 5*5bb27917SMirela Rabulea */ 6*5bb27917SMirela Rabuleaimg_subsys: bus@58000000 { 7*5bb27917SMirela Rabulea compatible = "simple-bus"; 8*5bb27917SMirela Rabulea #address-cells = <1>; 9*5bb27917SMirela Rabulea #size-cells = <1>; 10*5bb27917SMirela Rabulea ranges = <0x58000000 0x0 0x58000000 0x1000000>; 11*5bb27917SMirela Rabulea 12*5bb27917SMirela Rabulea img_ipg_clk: clock-img-ipg { 13*5bb27917SMirela Rabulea compatible = "fixed-clock"; 14*5bb27917SMirela Rabulea #clock-cells = <0>; 15*5bb27917SMirela Rabulea clock-frequency = <200000000>; 16*5bb27917SMirela Rabulea clock-output-names = "img_ipg_clk"; 17*5bb27917SMirela Rabulea }; 18*5bb27917SMirela Rabulea 19*5bb27917SMirela Rabulea jpegdec: jpegdec@58400000 { 20*5bb27917SMirela Rabulea reg = <0x58400000 0x00050000>; 21*5bb27917SMirela Rabulea interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 22*5bb27917SMirela Rabulea <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 23*5bb27917SMirela Rabulea <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 24*5bb27917SMirela Rabulea <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 25*5bb27917SMirela Rabulea clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, 26*5bb27917SMirela Rabulea <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; 27*5bb27917SMirela Rabulea clock-names = "per", "ipg"; 28*5bb27917SMirela Rabulea assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, 29*5bb27917SMirela Rabulea <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; 30*5bb27917SMirela Rabulea assigned-clock-rates = <200000000>, <200000000>; 31*5bb27917SMirela Rabulea power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, 32*5bb27917SMirela Rabulea <&pd IMX_SC_R_MJPEG_DEC_S0>, 33*5bb27917SMirela Rabulea <&pd IMX_SC_R_MJPEG_DEC_S1>, 34*5bb27917SMirela Rabulea <&pd IMX_SC_R_MJPEG_DEC_S2>, 35*5bb27917SMirela Rabulea <&pd IMX_SC_R_MJPEG_DEC_S3>; 36*5bb27917SMirela Rabulea }; 37*5bb27917SMirela Rabulea 38*5bb27917SMirela Rabulea jpegenc: jpegenc@58450000 { 39*5bb27917SMirela Rabulea reg = <0x58450000 0x00050000>; 40*5bb27917SMirela Rabulea interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 41*5bb27917SMirela Rabulea <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 42*5bb27917SMirela Rabulea <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 43*5bb27917SMirela Rabulea <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 44*5bb27917SMirela Rabulea clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, 45*5bb27917SMirela Rabulea <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; 46*5bb27917SMirela Rabulea clock-names = "per", "ipg"; 47*5bb27917SMirela Rabulea assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, 48*5bb27917SMirela Rabulea <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; 49*5bb27917SMirela Rabulea assigned-clock-rates = <200000000>, <200000000>; 50*5bb27917SMirela Rabulea power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, 51*5bb27917SMirela Rabulea <&pd IMX_SC_R_MJPEG_ENC_S0>, 52*5bb27917SMirela Rabulea <&pd IMX_SC_R_MJPEG_ENC_S1>, 53*5bb27917SMirela Rabulea <&pd IMX_SC_R_MJPEG_ENC_S2>, 54*5bb27917SMirela Rabulea <&pd IMX_SC_R_MJPEG_ENC_S3>; 55*5bb27917SMirela Rabulea }; 56*5bb27917SMirela Rabulea 57*5bb27917SMirela Rabulea img_jpeg_dec_lpcg: clock-controller@585d0000 { 58*5bb27917SMirela Rabulea compatible = "fsl,imx8qxp-lpcg"; 59*5bb27917SMirela Rabulea reg = <0x585d0000 0x10000>; 60*5bb27917SMirela Rabulea #clock-cells = <1>; 61*5bb27917SMirela Rabulea clocks = <&img_ipg_clk>, <&img_ipg_clk>; 62*5bb27917SMirela Rabulea clock-indices = <IMX_LPCG_CLK_0>, 63*5bb27917SMirela Rabulea <IMX_LPCG_CLK_4>; 64*5bb27917SMirela Rabulea clock-output-names = "img_jpeg_dec_lpcg_clk", 65*5bb27917SMirela Rabulea "img_jpeg_dec_lpcg_ipg_clk"; 66*5bb27917SMirela Rabulea power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; 67*5bb27917SMirela Rabulea }; 68*5bb27917SMirela Rabulea 69*5bb27917SMirela Rabulea img_jpeg_enc_lpcg: clock-controller@585f0000 { 70*5bb27917SMirela Rabulea compatible = "fsl,imx8qxp-lpcg"; 71*5bb27917SMirela Rabulea reg = <0x585f0000 0x10000>; 72*5bb27917SMirela Rabulea #clock-cells = <1>; 73*5bb27917SMirela Rabulea clocks = <&img_ipg_clk>, <&img_ipg_clk>; 74*5bb27917SMirela Rabulea clock-indices = <IMX_LPCG_CLK_0>, 75*5bb27917SMirela Rabulea <IMX_LPCG_CLK_4>; 76*5bb27917SMirela Rabulea clock-output-names = "img_jpeg_enc_lpcg_clk", 77*5bb27917SMirela Rabulea "img_jpeg_enc_lpcg_ipg_clk"; 78*5bb27917SMirela Rabulea power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; 79*5bb27917SMirela Rabulea }; 80*5bb27917SMirela Rabulea}; 81