1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10dma_subsys: bus@5a000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; 15 16 dma_ipg_clk: clock-dma-ipg { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <120000000>; 20 clock-output-names = "dma_ipg_clk"; 21 }; 22 23 lpuart0: serial@5a060000 { 24 reg = <0x5a060000 0x1000>; 25 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 26 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, 27 <&uart0_lpcg IMX_LPCG_CLK_0>; 28 clock-names = "ipg", "baud"; 29 power-domains = <&pd IMX_SC_R_UART_0>; 30 status = "disabled"; 31 }; 32 33 lpuart1: serial@5a070000 { 34 reg = <0x5a070000 0x1000>; 35 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 36 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, 37 <&uart1_lpcg IMX_LPCG_CLK_0>; 38 clock-names = "ipg", "baud"; 39 power-domains = <&pd IMX_SC_R_UART_1>; 40 status = "disabled"; 41 }; 42 43 lpuart2: serial@5a080000 { 44 reg = <0x5a080000 0x1000>; 45 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, 47 <&uart2_lpcg IMX_LPCG_CLK_0>; 48 clock-names = "ipg", "baud"; 49 power-domains = <&pd IMX_SC_R_UART_2>; 50 status = "disabled"; 51 }; 52 53 lpuart3: serial@5a090000 { 54 reg = <0x5a090000 0x1000>; 55 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 56 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, 57 <&uart3_lpcg IMX_LPCG_CLK_0>; 58 clock-names = "ipg", "baud"; 59 power-domains = <&pd IMX_SC_R_UART_3>; 60 status = "disabled"; 61 }; 62 63 uart0_lpcg: clock-controller@5a460000 { 64 compatible = "fsl,imx8qxp-lpcg"; 65 reg = <0x5a460000 0x10000>; 66 #clock-cells = <1>; 67 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, 68 <&dma_ipg_clk>; 69 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 70 clock-output-names = "uart0_lpcg_baud_clk", 71 "uart0_lpcg_ipg_clk"; 72 power-domains = <&pd IMX_SC_R_UART_0>; 73 }; 74 75 uart1_lpcg: clock-controller@5a470000 { 76 compatible = "fsl,imx8qxp-lpcg"; 77 reg = <0x5a470000 0x10000>; 78 #clock-cells = <1>; 79 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, 80 <&dma_ipg_clk>; 81 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 82 clock-output-names = "uart1_lpcg_baud_clk", 83 "uart1_lpcg_ipg_clk"; 84 power-domains = <&pd IMX_SC_R_UART_1>; 85 }; 86 87 uart2_lpcg: clock-controller@5a480000 { 88 compatible = "fsl,imx8qxp-lpcg"; 89 reg = <0x5a480000 0x10000>; 90 #clock-cells = <1>; 91 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, 92 <&dma_ipg_clk>; 93 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 94 clock-output-names = "uart2_lpcg_baud_clk", 95 "uart2_lpcg_ipg_clk"; 96 power-domains = <&pd IMX_SC_R_UART_2>; 97 }; 98 99 uart3_lpcg: clock-controller@5a490000 { 100 compatible = "fsl,imx8qxp-lpcg"; 101 reg = <0x5a490000 0x10000>; 102 #clock-cells = <1>; 103 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, 104 <&dma_ipg_clk>; 105 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 106 clock-output-names = "uart3_lpcg_baud_clk", 107 "uart3_lpcg_ipg_clk"; 108 power-domains = <&pd IMX_SC_R_UART_3>; 109 }; 110 111 i2c0: i2c@5a800000 { 112 reg = <0x5a800000 0x4000>; 113 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>, 115 <&i2c0_lpcg IMX_LPCG_CLK_4>; 116 clock-names = "per", "ipg"; 117 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; 118 assigned-clock-rates = <24000000>; 119 power-domains = <&pd IMX_SC_R_I2C_0>; 120 status = "disabled"; 121 }; 122 123 i2c1: i2c@5a810000 { 124 reg = <0x5a810000 0x4000>; 125 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>, 127 <&i2c1_lpcg IMX_LPCG_CLK_4>; 128 clock-names = "per", "ipg"; 129 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; 130 assigned-clock-rates = <24000000>; 131 power-domains = <&pd IMX_SC_R_I2C_1>; 132 status = "disabled"; 133 }; 134 135 i2c2: i2c@5a820000 { 136 reg = <0x5a820000 0x4000>; 137 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>, 139 <&i2c2_lpcg IMX_LPCG_CLK_4>; 140 clock-names = "per", "ipg"; 141 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; 142 assigned-clock-rates = <24000000>; 143 power-domains = <&pd IMX_SC_R_I2C_2>; 144 status = "disabled"; 145 }; 146 147 i2c3: i2c@5a830000 { 148 reg = <0x5a830000 0x4000>; 149 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>, 151 <&i2c3_lpcg IMX_LPCG_CLK_4>; 152 clock-names = "per", "ipg"; 153 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; 154 assigned-clock-rates = <24000000>; 155 power-domains = <&pd IMX_SC_R_I2C_3>; 156 status = "disabled"; 157 }; 158 159 i2c0_lpcg: clock-controller@5ac00000 { 160 compatible = "fsl,imx8qxp-lpcg"; 161 reg = <0x5ac00000 0x10000>; 162 #clock-cells = <1>; 163 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, 164 <&dma_ipg_clk>; 165 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 166 clock-output-names = "i2c0_lpcg_clk", 167 "i2c0_lpcg_ipg_clk"; 168 power-domains = <&pd IMX_SC_R_I2C_0>; 169 }; 170 171 i2c1_lpcg: clock-controller@5ac10000 { 172 compatible = "fsl,imx8qxp-lpcg"; 173 reg = <0x5ac10000 0x10000>; 174 #clock-cells = <1>; 175 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, 176 <&dma_ipg_clk>; 177 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 178 clock-output-names = "i2c1_lpcg_clk", 179 "i2c1_lpcg_ipg_clk"; 180 power-domains = <&pd IMX_SC_R_I2C_1>; 181 }; 182 183 i2c2_lpcg: clock-controller@5ac20000 { 184 compatible = "fsl,imx8qxp-lpcg"; 185 reg = <0x5ac20000 0x10000>; 186 #clock-cells = <1>; 187 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, 188 <&dma_ipg_clk>; 189 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 190 clock-output-names = "i2c2_lpcg_clk", 191 "i2c2_lpcg_ipg_clk"; 192 power-domains = <&pd IMX_SC_R_I2C_2>; 193 }; 194 195 i2c3_lpcg: clock-controller@5ac30000 { 196 compatible = "fsl,imx8qxp-lpcg"; 197 reg = <0x5ac30000 0x10000>; 198 #clock-cells = <1>; 199 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, 200 <&dma_ipg_clk>; 201 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 202 clock-output-names = "i2c3_lpcg_clk", 203 "i2c3_lpcg_ipg_clk"; 204 power-domains = <&pd IMX_SC_R_I2C_3>; 205 }; 206}; 207