1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10dma_subsys: bus@5a000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; 15 16 dma_ipg_clk: clock-dma-ipg { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <120000000>; 20 clock-output-names = "dma_ipg_clk"; 21 }; 22 23 lpspi0: spi@5a000000 { 24 compatible = "fsl,imx7ulp-spi"; 25 reg = <0x5a000000 0x10000>; 26 #address-cells = <1>; 27 #size-cells = <0>; 28 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-parent = <&gic>; 30 clocks = <&spi0_lpcg 0>, 31 <&spi0_lpcg 1>; 32 clock-names = "per", "ipg"; 33 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; 34 assigned-clock-rates = <20000000>; 35 power-domains = <&pd IMX_SC_R_SPI_0>; 36 status = "disabled"; 37 }; 38 39 lpspi1: spi@5a010000 { 40 compatible = "fsl,imx7ulp-spi"; 41 reg = <0x5a010000 0x10000>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 45 interrupt-parent = <&gic>; 46 clocks = <&spi1_lpcg 0>, 47 <&spi1_lpcg 1>; 48 clock-names = "per", "ipg"; 49 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; 50 assigned-clock-rates = <60000000>; 51 power-domains = <&pd IMX_SC_R_SPI_1>; 52 status = "disabled"; 53 }; 54 55 lpspi2: spi@5a020000 { 56 compatible = "fsl,imx7ulp-spi"; 57 reg = <0x5a020000 0x10000>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 61 interrupt-parent = <&gic>; 62 clocks = <&spi2_lpcg 0>, 63 <&spi2_lpcg 1>; 64 clock-names = "per", "ipg"; 65 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; 66 assigned-clock-rates = <60000000>; 67 power-domains = <&pd IMX_SC_R_SPI_2>; 68 status = "disabled"; 69 }; 70 71 lpspi3: spi@5a030000 { 72 compatible = "fsl,imx7ulp-spi"; 73 reg = <0x5a030000 0x10000>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-parent = <&gic>; 78 clocks = <&spi3_lpcg 0>, 79 <&spi3_lpcg 1>; 80 clock-names = "per", "ipg"; 81 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; 82 assigned-clock-rates = <60000000>; 83 power-domains = <&pd IMX_SC_R_SPI_3>; 84 status = "disabled"; 85 }; 86 87 lpuart0: serial@5a060000 { 88 reg = <0x5a060000 0x1000>; 89 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, 91 <&uart0_lpcg IMX_LPCG_CLK_0>; 92 clock-names = "ipg", "baud"; 93 power-domains = <&pd IMX_SC_R_UART_0>; 94 status = "disabled"; 95 }; 96 97 lpuart1: serial@5a070000 { 98 reg = <0x5a070000 0x1000>; 99 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, 101 <&uart1_lpcg IMX_LPCG_CLK_0>; 102 clock-names = "ipg", "baud"; 103 power-domains = <&pd IMX_SC_R_UART_1>; 104 status = "disabled"; 105 }; 106 107 lpuart2: serial@5a080000 { 108 reg = <0x5a080000 0x1000>; 109 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, 111 <&uart2_lpcg IMX_LPCG_CLK_0>; 112 clock-names = "ipg", "baud"; 113 power-domains = <&pd IMX_SC_R_UART_2>; 114 status = "disabled"; 115 }; 116 117 lpuart3: serial@5a090000 { 118 reg = <0x5a090000 0x1000>; 119 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, 121 <&uart3_lpcg IMX_LPCG_CLK_0>; 122 clock-names = "ipg", "baud"; 123 power-domains = <&pd IMX_SC_R_UART_3>; 124 status = "disabled"; 125 }; 126 127 spi0_lpcg: clock-controller@5a400000 { 128 compatible = "fsl,imx8qxp-lpcg"; 129 reg = <0x5a400000 0x10000>; 130 #clock-cells = <1>; 131 clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, 132 <&dma_ipg_clk>; 133 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 134 clock-output-names = "spi0_lpcg_clk", 135 "spi0_lpcg_ipg_clk"; 136 power-domains = <&pd IMX_SC_R_SPI_0>; 137 }; 138 139 spi1_lpcg: clock-controller@5a410000 { 140 compatible = "fsl,imx8qxp-lpcg"; 141 reg = <0x5a410000 0x10000>; 142 #clock-cells = <1>; 143 clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, 144 <&dma_ipg_clk>; 145 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 146 clock-output-names = "spi1_lpcg_clk", 147 "spi1_lpcg_ipg_clk"; 148 power-domains = <&pd IMX_SC_R_SPI_1>; 149 }; 150 151 spi2_lpcg: clock-controller@5a420000 { 152 compatible = "fsl,imx8qxp-lpcg"; 153 reg = <0x5a420000 0x10000>; 154 #clock-cells = <1>; 155 clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, 156 <&dma_ipg_clk>; 157 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 158 clock-output-names = "spi2_lpcg_clk", 159 "spi2_lpcg_ipg_clk"; 160 power-domains = <&pd IMX_SC_R_SPI_2>; 161 }; 162 163 spi3_lpcg: clock-controller@5a430000 { 164 compatible = "fsl,imx8qxp-lpcg"; 165 reg = <0x5a430000 0x10000>; 166 #clock-cells = <1>; 167 clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, 168 <&dma_ipg_clk>; 169 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 170 clock-output-names = "spi3_lpcg_clk", 171 "spi3_lpcg_ipg_clk"; 172 power-domains = <&pd IMX_SC_R_SPI_3>; 173 }; 174 175 uart0_lpcg: clock-controller@5a460000 { 176 compatible = "fsl,imx8qxp-lpcg"; 177 reg = <0x5a460000 0x10000>; 178 #clock-cells = <1>; 179 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, 180 <&dma_ipg_clk>; 181 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 182 clock-output-names = "uart0_lpcg_baud_clk", 183 "uart0_lpcg_ipg_clk"; 184 power-domains = <&pd IMX_SC_R_UART_0>; 185 }; 186 187 uart1_lpcg: clock-controller@5a470000 { 188 compatible = "fsl,imx8qxp-lpcg"; 189 reg = <0x5a470000 0x10000>; 190 #clock-cells = <1>; 191 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, 192 <&dma_ipg_clk>; 193 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 194 clock-output-names = "uart1_lpcg_baud_clk", 195 "uart1_lpcg_ipg_clk"; 196 power-domains = <&pd IMX_SC_R_UART_1>; 197 }; 198 199 uart2_lpcg: clock-controller@5a480000 { 200 compatible = "fsl,imx8qxp-lpcg"; 201 reg = <0x5a480000 0x10000>; 202 #clock-cells = <1>; 203 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, 204 <&dma_ipg_clk>; 205 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 206 clock-output-names = "uart2_lpcg_baud_clk", 207 "uart2_lpcg_ipg_clk"; 208 power-domains = <&pd IMX_SC_R_UART_2>; 209 }; 210 211 uart3_lpcg: clock-controller@5a490000 { 212 compatible = "fsl,imx8qxp-lpcg"; 213 reg = <0x5a490000 0x10000>; 214 #clock-cells = <1>; 215 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, 216 <&dma_ipg_clk>; 217 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 218 clock-output-names = "uart3_lpcg_baud_clk", 219 "uart3_lpcg_ipg_clk"; 220 power-domains = <&pd IMX_SC_R_UART_3>; 221 }; 222 223 i2c0: i2c@5a800000 { 224 reg = <0x5a800000 0x4000>; 225 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>, 227 <&i2c0_lpcg IMX_LPCG_CLK_4>; 228 clock-names = "per", "ipg"; 229 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; 230 assigned-clock-rates = <24000000>; 231 power-domains = <&pd IMX_SC_R_I2C_0>; 232 status = "disabled"; 233 }; 234 235 i2c1: i2c@5a810000 { 236 reg = <0x5a810000 0x4000>; 237 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>, 239 <&i2c1_lpcg IMX_LPCG_CLK_4>; 240 clock-names = "per", "ipg"; 241 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; 242 assigned-clock-rates = <24000000>; 243 power-domains = <&pd IMX_SC_R_I2C_1>; 244 status = "disabled"; 245 }; 246 247 i2c2: i2c@5a820000 { 248 reg = <0x5a820000 0x4000>; 249 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>, 251 <&i2c2_lpcg IMX_LPCG_CLK_4>; 252 clock-names = "per", "ipg"; 253 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; 254 assigned-clock-rates = <24000000>; 255 power-domains = <&pd IMX_SC_R_I2C_2>; 256 status = "disabled"; 257 }; 258 259 i2c3: i2c@5a830000 { 260 reg = <0x5a830000 0x4000>; 261 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>, 263 <&i2c3_lpcg IMX_LPCG_CLK_4>; 264 clock-names = "per", "ipg"; 265 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; 266 assigned-clock-rates = <24000000>; 267 power-domains = <&pd IMX_SC_R_I2C_3>; 268 status = "disabled"; 269 }; 270 271 adc0: adc@5a880000 { 272 compatible = "nxp,imx8qxp-adc"; 273 reg = <0x5a880000 0x10000>; 274 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-parent = <&gic>; 276 clocks = <&adc0_lpcg 0>, 277 <&adc0_lpcg 1>; 278 clock-names = "per", "ipg"; 279 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; 280 assigned-clock-rates = <24000000>; 281 power-domains = <&pd IMX_SC_R_ADC_0>; 282 status = "disabled"; 283 }; 284 285 adc1: adc@5a890000 { 286 compatible = "nxp,imx8qxp-adc"; 287 reg = <0x5a890000 0x10000>; 288 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-parent = <&gic>; 290 clocks = <&adc1_lpcg 0>, 291 <&adc1_lpcg 1>; 292 clock-names = "per", "ipg"; 293 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; 294 assigned-clock-rates = <24000000>; 295 power-domains = <&pd IMX_SC_R_ADC_1>; 296 status = "disabled"; 297 }; 298 299 i2c0_lpcg: clock-controller@5ac00000 { 300 compatible = "fsl,imx8qxp-lpcg"; 301 reg = <0x5ac00000 0x10000>; 302 #clock-cells = <1>; 303 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, 304 <&dma_ipg_clk>; 305 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 306 clock-output-names = "i2c0_lpcg_clk", 307 "i2c0_lpcg_ipg_clk"; 308 power-domains = <&pd IMX_SC_R_I2C_0>; 309 }; 310 311 i2c1_lpcg: clock-controller@5ac10000 { 312 compatible = "fsl,imx8qxp-lpcg"; 313 reg = <0x5ac10000 0x10000>; 314 #clock-cells = <1>; 315 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, 316 <&dma_ipg_clk>; 317 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 318 clock-output-names = "i2c1_lpcg_clk", 319 "i2c1_lpcg_ipg_clk"; 320 power-domains = <&pd IMX_SC_R_I2C_1>; 321 }; 322 323 i2c2_lpcg: clock-controller@5ac20000 { 324 compatible = "fsl,imx8qxp-lpcg"; 325 reg = <0x5ac20000 0x10000>; 326 #clock-cells = <1>; 327 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, 328 <&dma_ipg_clk>; 329 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 330 clock-output-names = "i2c2_lpcg_clk", 331 "i2c2_lpcg_ipg_clk"; 332 power-domains = <&pd IMX_SC_R_I2C_2>; 333 }; 334 335 i2c3_lpcg: clock-controller@5ac30000 { 336 compatible = "fsl,imx8qxp-lpcg"; 337 reg = <0x5ac30000 0x10000>; 338 #clock-cells = <1>; 339 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, 340 <&dma_ipg_clk>; 341 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 342 clock-output-names = "i2c3_lpcg_clk", 343 "i2c3_lpcg_ipg_clk"; 344 power-domains = <&pd IMX_SC_R_I2C_3>; 345 }; 346 347 adc0_lpcg: clock-controller@5ac80000 { 348 compatible = "fsl,imx8qxp-lpcg"; 349 reg = <0x5ac80000 0x10000>; 350 #clock-cells = <1>; 351 clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, 352 <&dma_ipg_clk>; 353 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 354 clock-output-names = "adc0_lpcg_clk", 355 "adc0_lpcg_ipg_clk"; 356 power-domains = <&pd IMX_SC_R_ADC_0>; 357 }; 358 359 adc1_lpcg: clock-controller@5ac90000 { 360 compatible = "fsl,imx8qxp-lpcg"; 361 reg = <0x5ac90000 0x10000>; 362 #clock-cells = <1>; 363 clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, 364 <&dma_ipg_clk>; 365 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 366 clock-output-names = "adc1_lpcg_clk", 367 "adc1_lpcg_ipg_clk"; 368 power-domains = <&pd IMX_SC_R_ADC_1>; 369 }; 370}; 371