1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include <dt-bindings/pwm/pwm.h>
7
8/ {
9	chosen {
10		stdout-path = &lpuart1;
11	};
12
13	/* Apalis BKL1 */
14	backlight: backlight {
15		compatible = "pwm-backlight";
16		pinctrl-names = "default";
17		pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18		brightness-levels = <0 45 63 88 119 158 203 255>;
19		default-brightness-level = <4>;
20		enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
21		/* TODO: hook-up to Apalis BKL1_PWM */
22		status = "disabled";
23	};
24
25	gpio_fan: gpio-fan {
26		compatible = "gpio-fan";
27		pinctrl-names = "default";
28		pinctrl-0 = <&pinctrl_gpio8>;
29		gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>;
30		gpio-fan,speed-map = <	 0 0
31				      3000 1>;
32	};
33
34	/* TODO: LVDS Panel */
35
36	/* TODO: Shared PCIe/SATA Reference Clock */
37
38	/* TODO: PCIe Wi-Fi Reference Clock */
39
40	/*
41	 * Power management bus used to control LDO1OUT of the
42	 * second PMIC PF8100. This is used for controlling voltage levels of
43	 * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
44	 *
45	 * IMX_SC_R_BOARD_R1 for 3.3V
46	 * IMX_SC_R_BOARD_R2 for 1.8V
47	 * IMX_SC_R_BOARD_R3 for 2.5V
48	 * Note that for 2.5V operation the pad muxing needs to be changed,
49	 * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
50	 *
51	 * those power domains are mutually exclusive.
52	 */
53	reg_ext_rgmii: regulator-ext-rgmii {
54		compatible = "regulator-fixed";
55		power-domains = <&pd IMX_SC_R_BOARD_R1>;
56		regulator-max-microvolt = <3300000>;
57		regulator-min-microvolt = <3300000>;
58		regulator-name = "VDD_EXT_RGMII (LDO1)";
59
60		regulator-state-mem {
61			regulator-off-in-suspend;
62		};
63	};
64
65	reg_module_3v3: regulator-module-3v3 {
66		compatible = "regulator-fixed";
67		regulator-max-microvolt = <3300000>;
68		regulator-min-microvolt = <3300000>;
69		regulator-name = "+V3.3";
70	};
71
72	reg_module_3v3_avdd: regulator-module-3v3-avdd {
73		compatible = "regulator-fixed";
74		regulator-max-microvolt = <3300000>;
75		regulator-min-microvolt = <3300000>;
76		regulator-name = "+V3.3_AUDIO";
77	};
78
79	reg_module_wifi: regulator-module-wifi {
80		compatible = "regulator-fixed";
81		pinctrl-names = "default";
82		pinctrl-0 = <&pinctrl_wifi_pdn>;
83		gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
84		enable-active-high;
85		regulator-always-on;
86		regulator-name = "wifi_pwrdn_fake_regulator";
87		regulator-settling-time-us = <100>;
88	};
89
90	reg_pcie_switch: regulator-pcie-switch {
91		compatible = "regulator-fixed";
92		pinctrl-names = "default";
93		pinctrl-0 = <&pinctrl_gpio7>;
94		gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>;
95		enable-active-high;
96		regulator-max-microvolt = <1800000>;
97		regulator-min-microvolt = <1800000>;
98		regulator-name = "pcie_switch";
99		startup-delay-us = <100000>;
100	};
101
102	reg_usb_host_vbus: regulator-usb-host-vbus {
103		compatible = "regulator-fixed";
104		pinctrl-names = "default";
105		pinctrl-0 = <&pinctrl_usbh_en>;
106		/* Apalis USBH_EN */
107		gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>;
108		enable-active-high;
109		regulator-always-on;
110		regulator-max-microvolt = <5000000>;
111		regulator-min-microvolt = <5000000>;
112		regulator-name = "usb-host-vbus";
113	};
114
115	reg_usb_hsic: regulator-usb-hsic {
116		compatible = "regulator-fixed";
117		regulator-max-microvolt = <3000000>;
118		regulator-min-microvolt = <3000000>;
119		regulator-name = "usb-hsic-dummy";
120	};
121
122	reg_usb_phy: regulator-usb-hsic1 {
123		compatible = "regulator-fixed";
124		regulator-max-microvolt = <3000000>;
125		regulator-min-microvolt = <3000000>;
126		regulator-name = "usb-phy-dummy";
127	};
128
129	reserved-memory {
130		#address-cells = <2>;
131		#size-cells = <2>;
132		ranges;
133
134		decoder_boot: decoder-boot@84000000 {
135			reg = <0 0x84000000 0 0x2000000>;
136			no-map;
137		};
138
139		encoder1_boot: encoder1-boot@86000000 {
140			reg = <0 0x86000000 0 0x200000>;
141			no-map;
142		};
143
144		encoder2_boot: encoder2-boot@86200000 {
145			reg = <0 0x86200000 0 0x200000>;
146			no-map;
147		};
148
149		/*
150		 * reserved-memory layout
151		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
152		 * Shouldn't be used at A core and Linux side.
153		 *
154		 */
155		m4_reserved: m4@88000000 {
156			reg = <0 0x88000000 0 0x8000000>;
157			no-map;
158		};
159
160		rpmsg_reserved: rpmsg@90200000 {
161			reg = <0 0x90200000 0 0x200000>;
162			no-map;
163		};
164
165		vdevbuffer: vdevbuffer@90400000 {
166			compatible = "shared-dma-pool";
167			reg = <0 0x90400000 0 0x100000>;
168			no-map;
169		};
170
171		decoder_rpc: decoder-rpc@92000000 {
172			reg = <0 0x92000000 0 0x200000>;
173			no-map;
174		};
175
176		dsp_reserved: dsp@92400000 {
177			reg = <0 0x92400000 0 0x2000000>;
178			no-map;
179		};
180
181		encoder1_rpc: encoder1-rpc@94400000 {
182			reg = <0 0x94400000 0 0x700000>;
183			no-map;
184		};
185
186		encoder2_rpc: encoder2-rpc@94b00000 {
187			reg = <0 0x94b00000 0 0x700000>;
188			no-map;
189		};
190
191		/* global autoconfigured region for contiguous allocations */
192		linux,cma {
193			compatible = "shared-dma-pool";
194			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
195			linux,cma-default;
196			reusable;
197			size = <0 0x3c000000>;
198		};
199	};
200
201	/* TODO: Apalis Analogue Audio */
202
203	/* TODO: HDMI Audio */
204
205	/* TODO: Apalis SPDIF1 */
206
207	touchscreen: touchscreen {
208		compatible = "toradex,vf50-touchscreen";
209		interrupt-parent = <&lsio_gpio3>;
210		interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
211		pinctrl-names = "idle", "default";
212		pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>;
213		pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>;
214		io-channels = <&adc1 2>, <&adc1 1>,
215			      <&adc1 0>, <&adc1 3>;
216		vf50-ts-min-pressure = <200>;
217		xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>;
218		xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>;
219		yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>;
220		ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>;
221		/*
222		 * NOTE: you must remove the pinctrl-adc1 from the adc1
223		 * node below to use the touchscreen
224		 */
225		status = "disabled";
226	};
227
228};
229
230&adc0 {
231	pinctrl-names = "default";
232	pinctrl-0 = <&pinctrl_adc0>;
233};
234
235&adc1 {
236	pinctrl-names = "default";
237	pinctrl-0 = <&pinctrl_adc1>;
238};
239
240/* TODO: Asynchronous Sample Rate Converter (ASRC) */
241
242/* Apalis ETH1 */
243&fec1 {
244	pinctrl-names = "default", "sleep";
245	pinctrl-0 = <&pinctrl_fec1>;
246	pinctrl-1 = <&pinctrl_fec1_sleep>;
247	fsl,magic-packet;
248	phy-handle = <&ethphy0>;
249	phy-mode = "rgmii-id";
250
251	mdio {
252		#address-cells = <1>;
253		#size-cells = <0>;
254
255		ethphy0: ethernet-phy@7 {
256			compatible = "ethernet-phy-ieee802.3-c22";
257			reg = <7>;
258			interrupt-parent = <&lsio_gpio1>;
259			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
260			micrel,led-mode = <0>;
261			reset-assert-us = <2>;
262			reset-deassert-us = <2>;
263			reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
264			reset-names = "phy-reset";
265		};
266	};
267};
268
269/* Apalis CAN1 */
270&flexcan1 {
271	pinctrl-names = "default";
272	pinctrl-0 = <&pinctrl_flexcan1>;
273};
274
275/* Apalis CAN2 */
276&flexcan2 {
277	pinctrl-names = "default";
278	pinctrl-0 = <&pinctrl_flexcan2>;
279};
280
281/* Apalis CAN3 (optional) */
282&flexcan3 {
283	pinctrl-names = "default";
284	pinctrl-0 = <&pinctrl_flexcan3>;
285};
286
287/* TODO: Apalis HDMI1 */
288
289/* On-module I2C */
290&i2c1 {
291	pinctrl-names = "default";
292	pinctrl-0 = <&pinctrl_lpi2c1>;
293	#address-cells = <1>;
294	#size-cells = <0>;
295	clock-frequency = <100000>;
296	status = "okay";
297
298	/* TODO: Audio Codec */
299
300	/* USB3503A */
301	usb-hub@8 {
302		compatible = "smsc,usb3503a";
303		reg = <0x08>;
304		pinctrl-names = "default";
305		pinctrl-0 = <&pinctrl_usb3503a>;
306		connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>;
307		initial-mode = <1>;
308		intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;
309		refclk-frequency = <25000000>;
310		reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>;
311	};
312};
313
314/* Apalis I2C1 */
315&i2c2 {
316	pinctrl-names = "default";
317	pinctrl-0 = <&pinctrl_lpi2c2>;
318	#address-cells = <1>;
319	#size-cells = <0>;
320	clock-frequency = <100000>;
321
322	atmel_mxt_ts: touch@4a {
323		compatible = "atmel,maxtouch";
324		reg = <0x4a>;
325		interrupt-parent = <&lsio_gpio4>;
326		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;		/* Apalis GPIO5 */
327		pinctrl-names = "default";
328		pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>;
329		reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>;	/* Apalis GPIO6 */
330		status = "disabled";
331	};
332
333	/* M41T0M6 real time clock on carrier board */
334	rtc_i2c: rtc@68 {
335		compatible = "st,m41t0";
336		reg = <0x68>;
337		status = "disabled";
338	};
339};
340
341/* Apalis I2C3 (CAM) */
342&i2c3 {
343	pinctrl-names = "default";
344	pinctrl-0 = <&pinctrl_lpi2c3>;
345	#address-cells = <1>;
346	#size-cells = <0>;
347	clock-frequency = <100000>;
348};
349
350&jpegdec {
351	status = "okay";
352};
353
354&jpegenc {
355	status = "okay";
356};
357
358/* TODO: Apalis LVDS1 */
359
360/* Apalis SPI1 */
361&lpspi0 {
362	pinctrl-names = "default";
363	pinctrl-0 = <&pinctrl_lpspi0>;
364	#address-cells = <1>;
365	#size-cells = <0>;
366	cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>;
367};
368
369/* Apalis SPI2 */
370&lpspi2 {
371	pinctrl-names = "default";
372	pinctrl-0 = <&pinctrl_lpspi2>;
373	#address-cells = <1>;
374	#size-cells = <0>;
375	cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
376};
377
378/* Apalis UART3 */
379&lpuart0 {
380	pinctrl-names = "default";
381	pinctrl-0 = <&pinctrl_lpuart0>;
382};
383
384/* Apalis UART1 */
385&lpuart1 {
386	pinctrl-names = "default";
387	pinctrl-0 = <&pinctrl_lpuart1>;
388};
389
390/* Apalis UART4 */
391&lpuart2 {
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_lpuart2>;
394};
395
396/* Apalis UART2 */
397&lpuart3 {
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_lpuart3>;
400};
401
402&lsio_gpio0 {
403	gpio-line-names = "MXM3_279",
404			  "MXM3_277",
405			  "MXM3_135",
406			  "MXM3_203",
407			  "MXM3_201",
408			  "MXM3_275",
409			  "MXM3_110",
410			  "MXM3_120",
411			  "MXM3_1/GPIO1",
412			  "MXM3_3/GPIO2",
413			  "MXM3_124",
414			  "MXM3_122",
415			  "MXM3_5/GPIO3",
416			  "MXM3_7/GPIO4",
417			  "",
418			  "",
419			  "MXM3_4",
420			  "MXM3_211",
421			  "MXM3_209",
422			  "MXM3_2",
423			  "MXM3_136",
424			  "MXM3_134",
425			  "MXM3_6",
426			  "MXM3_8",
427			  "MXM3_112",
428			  "MXM3_118",
429			  "MXM3_114",
430			  "MXM3_116";
431};
432
433&lsio_gpio1 {
434	gpio-line-names = "",
435			  "",
436			  "",
437			  "",
438			  "MXM3_286",
439			  "",
440			  "MXM3_87",
441			  "MXM3_99",
442			  "MXM3_138",
443			  "MXM3_140",
444			  "MXM3_239",
445			  "",
446			  "MXM3_281",
447			  "MXM3_283",
448			  "MXM3_126",
449			  "MXM3_132",
450			  "",
451			  "",
452			  "",
453			  "",
454			  "MXM3_173",
455			  "MXM3_175",
456			  "MXM3_123";
457
458	hdmi-ctrl-hog {
459		pinctrl-names = "default";
460		pinctrl-0 = <&pinctrl_hdmi_ctrl>;
461		gpio-hog;
462		gpios = <30 GPIO_ACTIVE_HIGH>;
463		line-name = "CONNECTOR_IS_HDMI";
464		/* Set signals depending on HDP device type, 0 DP, 1 HDMI */
465		output-high;
466	};
467};
468
469&lsio_gpio2 {
470	gpio-line-names = "",
471			  "",
472			  "",
473			  "",
474			  "",
475			  "",
476			  "",
477			  "MXM3_198",
478			  "MXM3_35",
479			  "MXM3_164",
480			  "",
481			  "",
482			  "",
483			  "",
484			  "MXM3_217",
485			  "MXM3_215",
486			  "",
487			  "",
488			  "MXM3_193",
489			  "MXM3_194",
490			  "MXM3_37",
491			  "",
492			  "MXM3_271",
493			  "MXM3_273",
494			  "MXM3_195",
495			  "MXM3_197",
496			  "MXM3_177",
497			  "MXM3_179",
498			  "MXM3_181",
499			  "MXM3_183",
500			  "MXM3_185",
501			  "MXM3_187";
502
503	/*
504	 * Add GPIO2_20 as a wakeup source:
505	 * Pin:  101	SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO)
506	 * Type: 5	SC_PAD_WAKEUP_FALL_EDGE
507	 * Line: 20
508	 */
509	pad-wakeup = <IMX8QM_SPI3_CS0 5 20>;
510	pad-wakeup-num = <1>;
511
512	pcie-wifi-hog {
513		pinctrl-names = "default";
514		pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
515		gpio-hog;
516		gpios = <11 GPIO_ACTIVE_HIGH>;
517		line-name = "PCIE_WIFI_CLK";
518		output-high;
519	};
520};
521
522&lsio_gpio3 {
523	gpio-line-names = "MXM3_191",
524			  "",
525			  "MXM3_221",
526			  "MXM3_225",
527			  "MXM3_223",
528			  "MXM3_227",
529			  "MXM3_200",
530			  "MXM3_235",
531			  "MXM3_231",
532			  "MXM3_229",
533			  "MXM3_233",
534			  "MXM3_204",
535			  "MXM3_196",
536			  "",
537			  "MXM3_202",
538			  "",
539			  "",
540			  "",
541			  "MXM3_305",
542			  "MXM3_307",
543			  "MXM3_309",
544			  "MXM3_311",
545			  "MXM3_315",
546			  "MXM3_317",
547			  "MXM3_319",
548			  "MXM3_321",
549			  "MXM3_15/GPIO7",
550			  "MXM3_63",
551			  "MXM3_17/GPIO8",
552			  "MXM3_12",
553			  "MXM3_14",
554			  "MXM3_16";
555};
556
557&lsio_gpio4 {
558	gpio-line-names = "MXM3_18",
559			  "MXM3_11/GPIO5",
560			  "MXM3_13/GPIO6",
561			  "MXM3_274",
562			  "MXM3_84",
563			  "MXM3_262",
564			  "MXM3_96",
565			  "",
566			  "",
567			  "",
568			  "",
569			  "",
570			  "MXM3_190",
571			  "",
572			  "",
573			  "",
574			  "MXM3_269",
575			  "MXM3_251",
576			  "MXM3_253",
577			  "MXM3_295",
578			  "MXM3_299",
579			  "MXM3_301",
580			  "MXM3_297",
581			  "MXM3_293",
582			  "MXM3_291",
583			  "MXM3_289",
584			  "MXM3_287";
585
586	/* Enable pcie root / sata ref clock unconditionally */
587	pcie-sata-hog {
588		pinctrl-names = "default";
589		pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
590		gpio-hog;
591		gpios = <11 GPIO_ACTIVE_HIGH>;
592		line-name = "PCIE_SATA_CLK";
593		output-high;
594	};
595};
596
597&lsio_gpio5 {
598	gpio-line-names = "",
599			  "",
600			  "",
601			  "",
602			  "",
603			  "",
604			  "",
605			  "",
606			  "",
607			  "",
608			  "",
609			  "",
610			  "",
611			  "",
612			  "MXM3_150",
613			  "MXM3_160",
614			  "MXM3_162",
615			  "MXM3_144",
616			  "MXM3_146",
617			  "MXM3_148",
618			  "MXM3_152",
619			  "MXM3_156",
620			  "MXM3_158",
621			  "MXM3_159",
622			  "MXM3_184",
623			  "MXM3_180",
624			  "MXM3_186",
625			  "MXM3_188",
626			  "MXM3_176",
627			  "MXM3_178";
628};
629
630&lsio_gpio6 {
631	gpio-line-names = "",
632			  "",
633			  "",
634			  "",
635			  "",
636			  "",
637			  "",
638			  "",
639			  "",
640			  "",
641			  "MXM3_261",
642			  "MXM3_263",
643			  "MXM3_259",
644			  "MXM3_257",
645			  "MXM3_255",
646			  "MXM3_128",
647			  "MXM3_130",
648			  "MXM3_265",
649			  "MXM3_249",
650			  "MXM3_247",
651			  "MXM3_245",
652			  "MXM3_243";
653};
654
655/* Apalis PWM3, MXM3 pin 6 */
656&lsio_pwm0 {
657	pinctrl-names = "default";
658	pinctrl-0 = <&pinctrl_pwm0>;
659	#pwm-cells = <3>;
660};
661
662/* Apalis PWM4, MXM3 pin 8 */
663&lsio_pwm1 {
664	pinctrl-names = "default";
665	pinctrl-0 = <&pinctrl_pwm1>;
666	#pwm-cells = <3>;
667};
668
669/* Apalis PWM1, MXM3 pin 2 */
670&lsio_pwm2 {
671	pinctrl-names = "default";
672	pinctrl-0 = <&pinctrl_pwm2>;
673	#pwm-cells = <3>;
674};
675
676/* Apalis PWM2, MXM3 pin 4 */
677&lsio_pwm3 {
678	pinctrl-names = "default";
679	pinctrl-0 = <&pinctrl_pwm3>;
680	#pwm-cells = <3>;
681};
682
683/* Messaging Units */
684&mu_m0 {
685	status = "okay";
686};
687
688&mu1_m0 {
689	status = "okay";
690};
691
692&mu2_m0 {
693	status = "okay";
694};
695
696/* TODO: Apalis PCIE1 */
697
698/* TODO: On-module Wi-Fi */
699
700/* TODO: Apalis BKL1_PWM */
701
702/* TODO: Apalis DAP1 */
703
704/* TODO: Analogue Audio */
705
706/* TODO: Apalis SATA1 */
707
708/* TODO: Apalis SPDIF1 */
709
710/* TODO: Thermal Zones */
711
712/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
713
714/* TODO: Apalis USBH4 */
715
716/* Apalis USBO1 */
717&usbphy1 {
718	phy-3p0-supply = <&reg_usb_phy>;
719	status = "okay";
720};
721
722&usbotg1 {
723	pinctrl-names = "default";
724	pinctrl-0 = <&pinctrl_usbotg1>;
725	adp-disable;
726	hnp-disable;
727	over-current-active-low;
728	power-active-high;
729	srp-disable;
730};
731
732/* On-module eMMC */
733&usdhc1 {
734	pinctrl-names = "default", "state_100mhz", "state_200mhz";
735	pinctrl-0 = <&pinctrl_usdhc1>;
736	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
737	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
738	bus-width = <8>;
739	non-removable;
740	status = "okay";
741};
742
743/* Apalis MMC1 */
744&usdhc2 {
745	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
746	pinctrl-0 = <&pinctrl_usdhc2_4bit>,
747		    <&pinctrl_usdhc2_8bit>,
748		    <&pinctrl_mmc1_cd>;
749	pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>,
750		    <&pinctrl_usdhc2_8bit_100mhz>,
751		    <&pinctrl_mmc1_cd>;
752	pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>,
753		    <&pinctrl_usdhc2_8bit_200mhz>,
754		    <&pinctrl_mmc1_cd>;
755	pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>,
756		    <&pinctrl_usdhc2_8bit_sleep>,
757		    <&pinctrl_mmc1_cd_sleep>;
758	bus-width = <8>;
759	cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
760	no-1-8-v;
761};
762
763/* Apalis SD1 */
764&usdhc3 {
765	pinctrl-names = "default", "state_100mhz", "state_200mhz";
766	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
767	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>;
768	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>;
769	bus-width = <4>;
770	cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
771	no-1-8-v;
772};
773
774/* Video Processing Unit */
775&vpu {
776	compatible = "nxp,imx8qm-vpu";
777	status = "okay";
778};
779
780&vpu_core0 {
781	reg = <0x2d080000 0x10000>;
782	memory-region = <&decoder_boot>, <&decoder_rpc>;
783	status = "okay";
784};
785
786&vpu_core1 {
787	reg = <0x2d090000 0x10000>;
788	memory-region = <&encoder1_boot>, <&encoder1_rpc>;
789	status = "okay";
790};
791
792&vpu_core2 {
793	reg = <0x2d0a0000 0x10000>;
794	memory-region = <&encoder2_boot>, <&encoder2_rpc>;
795	status = "okay";
796};
797
798&iomuxc {
799	pinctrl-names = "default";
800	pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
801		    <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
802		    <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>,
803		    <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>,
804		    <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>,
805		    <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>,
806		    <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>,
807		    <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>,
808		    <&pinctrl_usdhc1_gpios>;
809
810	/* Apalis AN1_ADC */
811	pinctrl_adc0: adc0grp {
812		fsl,pins = /* Apalis AN1_ADC0 */
813			   <IMX8QM_ADC_IN0_DMA_ADC0_IN0				0xc0000060>,
814			   /* Apalis AN1_ADC1 */
815			   <IMX8QM_ADC_IN1_DMA_ADC0_IN1				0xc0000060>,
816			   /* Apalis AN1_ADC2 */
817			   <IMX8QM_ADC_IN2_DMA_ADC0_IN2				0xc0000060>,
818			   /* Apalis AN1_TSWIP_ADC3 */
819			   <IMX8QM_ADC_IN3_DMA_ADC0_IN3				0xc0000060>;
820	};
821
822	/* Apalis AN1_TS */
823	pinctrl_adc1: adc1grp {
824		fsl,pins = /* Apalis AN1_TSPX */
825			   <IMX8QM_ADC_IN4_DMA_ADC1_IN0				0xc0000060>,
826			   /* Apalis AN1_TSMX */
827			   <IMX8QM_ADC_IN5_DMA_ADC1_IN1				0xc0000060>,
828			   /* Apalis AN1_TSPY */
829			   <IMX8QM_ADC_IN6_DMA_ADC1_IN2				0xc0000060>,
830			   /* Apalis AN1_TSMY */
831			   <IMX8QM_ADC_IN7_DMA_ADC1_IN3				0xc0000060>;
832	};
833
834	/* Apalis CAM1 */
835	pinctrl_cam1_gpios: cam1gpiosgrp {
836		fsl,pins = /* Apalis CAM1_D7 */
837			   <IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20		0x00000021>,
838			   /* Apalis CAM1_D6 */
839			   <IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21		0x00000021>,
840			   /* Apalis CAM1_D5 */
841			   <IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26			0x00000021>,
842			   /* Apalis CAM1_D4 */
843			   <IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27			0x00000021>,
844			   /* Apalis CAM1_D3 */
845			   <IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28		0x00000021>,
846			   /* Apalis CAM1_D2 */
847			   <IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29		0x00000021>,
848			   /* Apalis CAM1_D1 */
849			   <IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30		0x00000021>,
850			   /* Apalis CAM1_D0 */
851			   <IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31		0x00000021>,
852			   /* Apalis CAM1_PCLK */
853			   <IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00			0x00000021>,
854			   /* Apalis CAM1_MCLK */
855			   <IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18			0x00000021>,
856			   /* Apalis CAM1_VSYNC */
857			   <IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24			0x00000021>,
858			   /* Apalis CAM1_HSYNC */
859			   <IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25			0x00000021>;
860	};
861
862	/* Apalis DAP1 */
863	pinctrl_dap1_gpios: dap1gpiosgrp {
864		fsl,pins = /* Apalis DAP1_MCLK */
865			   <IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19			0x00000021>,
866			   /* Apalis DAP1_D_OUT */
867			   <IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12			0x00000021>,
868			   /* Apalis DAP1_RESET */
869			   <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07			0x00000021>,
870			   /* Apalis DAP1_BIT_CLK */
871			   <IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06			0x00000021>,
872			   /* Apalis DAP1_D_IN */
873			   <IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14			0x00000021>,
874			   /* Apalis DAP1_SYNC */
875			   <IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11			0x00000021>,
876			   /* On-module Wi-Fi_I2S_EN# */
877			   <IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13		0x00000021>;
878	};
879
880	/* Apalis LCD1_G1+2 */
881	pinctrl_esai0_gpios: esai0gpiosgrp {
882		fsl,pins = /* Apalis LCD1_G1 */
883			   <IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22			0x00000021>,
884			   /* Apalis LCD1_G2 */
885			   <IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23			0x00000021>;
886	};
887
888	/* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */
889	pinctrl_fec1: fec1grp {
890		fsl,pins = /* Use pads in 3.3V mode */
891			   <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD			0x000014a0>,
892			   <IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020>,
893			   <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO				0x06000020>,
894			   <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL		0x06000020>,
895			   <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC			0x06000020>,
896			   <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020>,
897			   <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020>,
898			   <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020>,
899			   <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020>,
900			   <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC			0x06000020>,
901			   <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL		0x06000020>,
902			   <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020>,
903			   <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020>,
904			   <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020>,
905			   <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020>,
906			   <IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M	0x06000020>,
907			   /* On-module ETH_RESET# */
908			   <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11				0x06000020>,
909			   /* On-module ETH_INT# */
910			   <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29			0x04000060>;
911	};
912
913	pinctrl_fec1_sleep: fec1-sleepgrp {
914		fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD		0x000014a0>,
915			   <IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14			0x04000040>,
916			   <IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13			0x04000040>,
917			   <IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31		0x04000040>,
918			   <IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30		0x04000040>,
919			   <IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00		0x04000040>,
920			   <IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01		0x04000040>,
921			   <IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02		0x04000040>,
922			   <IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03		0x04000040>,
923			   <IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04		0x04000040>,
924			   <IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05		0x04000040>,
925			   <IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06		0x04000040>,
926			   <IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07		0x04000040>,
927			   <IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08		0x04000040>,
928			   <IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09		0x04000040>,
929			   <IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15	0x04000040>,
930			   <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11			0x06000020>,
931			   <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29		0x04000040>;
932	};
933
934	/* Apalis LCD1_ */
935	pinctrl_fec2_gpios: fec2gpiosgrp {
936		fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0>,
937			   /* Apalis LCD1_R1 */
938			   <IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18			0x00000021>,
939			   /* Apalis LCD1_R0 */
940			   <IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17			0x00000021>,
941			   /* Apalis LCD1_G0 */
942			   <IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16	0x00000021>,
943			   /* Apalis LCD1_R7 */
944			   <IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17		0x00000021>,
945			   /* Apalis LCD1_DE */
946			   <IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18		0x00000021>,
947			   /* Apalis LCD1_HSYNC */
948			   <IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19		0x00000021>,
949			   /* Apalis LCD1_VSYNC */
950			   <IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20		0x00000021>,
951			   /* Apalis LCD1_PCLK */
952			   <IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21		0x00000021>,
953			   /* Apalis LCD1_R6 */
954			   <IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11		0x00000021>,
955			   /* Apalis LCD1_R5 */
956			   <IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10		0x00000021>,
957			   /* Apalis LCD1_R4 */
958			   <IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12		0x00000021>,
959			   /* Apalis LCD1_R3 */
960			   <IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13		0x00000021>,
961			   /* Apalis LCD1_R2 */
962			   <IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14		0x00000021>;
963	};
964
965	/* Apalis CAN1 */
966	pinctrl_flexcan1: flexcan0grp {
967		fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX			0x00000021>,
968			   <IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX			0x00000021>;
969	};
970
971	/* Apalis CAN2 */
972	pinctrl_flexcan2: flexcan1grp {
973		fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX			0x00000021>,
974			   <IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX			0x00000021>;
975	};
976
977	/* Apalis CAN3 (optional) */
978	pinctrl_flexcan3: flexcan2grp {
979		fsl,pins = <IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX			0x00000021>,
980			   <IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX			0x00000021>;
981	};
982
983	/* Apalis GPIO1 */
984	pinctrl_gpio1: gpio1grp {
985		fsl,pins = <IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08			0x06000021>;
986	};
987
988	/* Apalis GPIO2 */
989	pinctrl_gpio2: gpio2grp {
990		fsl,pins = <IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09			0x06000021>;
991	};
992
993	/* Apalis GPIO3 */
994	pinctrl_gpio3: gpio3grp {
995		fsl,pins = <IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12			0x06000021>;
996	};
997
998	/* Apalis GPIO4 */
999	pinctrl_gpio4: gpio4grp {
1000		fsl,pins = <IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13			0x06000021>;
1001	};
1002
1003	/* Apalis GPIO5 */
1004	pinctrl_gpio5: gpio5grp {
1005		fsl,pins = <IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01			0x06000021>;
1006	};
1007
1008	/* Apalis GPIO6 */
1009	pinctrl_gpio6: gpio6grp {
1010		fsl,pins = <IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02			0x00000021>;
1011	};
1012
1013	/* Apalis GPIO7 */
1014	pinctrl_gpio7: gpio7grp {
1015		fsl,pins = <IMX8QM_MLB_SIG_LSIO_GPIO3_IO26			0x00000021>;
1016	};
1017
1018	/* Apalis GPIO8 */
1019	pinctrl_gpio8: gpio8grp {
1020		fsl,pins = <IMX8QM_MLB_DATA_LSIO_GPIO3_IO28			0x00000021>;
1021	};
1022
1023	/* Apalis BKL1_ON */
1024	pinctrl_gpio_bkl_on: gpiobklongrp {
1025		fsl,pins = <IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04			0x00000021>;
1026	};
1027
1028	/* Apalis WAKE1_MICO */
1029	pinctrl_gpio_keys: gpiokeysgrp {
1030		fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20			0x06700021>;
1031	};
1032
1033	/* Apalis USBH_OC# */
1034	pinctrl_gpio_usbh_oc_n: gpiousbhocngrp {
1035		fsl,pins = <IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06			0x04000021>;
1036	};
1037
1038	/* On-module HDMI_CTRL */
1039	pinctrl_hdmi_ctrl: hdmictrlgrp {
1040		fsl,pins = <IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0x00000061>;
1041	};
1042
1043	/* On-module I2C */
1044	pinctrl_lpi2c1: lpi2c1grp {
1045		fsl,pins = <IMX8QM_GPT0_CLK_DMA_I2C1_SCL			0x04000020>,
1046			   <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA			0x04000020>;
1047	};
1048
1049	/* Apalis I2C1 */
1050	pinctrl_lpi2c2: lpi2c2grp {
1051		fsl,pins = <IMX8QM_GPT1_CLK_DMA_I2C2_SCL			0x04000020>,
1052			   <IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA			0x04000020>;
1053	};
1054
1055	/* Apalis I2C3 (CAM) */
1056	pinctrl_lpi2c3: lpi2c3grp {
1057		fsl,pins = <IMX8QM_SIM0_PD_DMA_I2C3_SCL				0x04000020>,
1058			   <IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA			0x04000020>;
1059	};
1060
1061	/* Apalis SPI1 */
1062	pinctrl_lpspi0: lpspi0grp {
1063		fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK			0x0600004c>,
1064			   <IMX8QM_SPI0_SDO_DMA_SPI0_SDO			0x0600004c>,
1065			   <IMX8QM_SPI0_SDI_DMA_SPI0_SDI			0x0600004c>,
1066			   <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05			0x0600004c>;
1067	};
1068
1069	/* Apalis SPI2 */
1070	pinctrl_lpspi2: lpspi2grp {
1071		fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK			0x0600004c>,
1072			   <IMX8QM_SPI2_SDO_DMA_SPI2_SDO			0x0600004c>,
1073			   <IMX8QM_SPI2_SDI_DMA_SPI2_SDI			0x0600004c>,
1074			   <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10			0x0600004c>;
1075	};
1076
1077	/* Apalis UART3 */
1078	pinctrl_lpuart0: lpuart0grp {
1079		fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX			0x06000020>,
1080			   <IMX8QM_UART0_TX_DMA_UART0_TX			0x06000020>;
1081	};
1082
1083	/* Apalis UART1 */
1084	pinctrl_lpuart1: lpuart1grp {
1085		fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX			0x06000020>,
1086			   <IMX8QM_UART1_TX_DMA_UART1_TX			0x06000020>,
1087			   <IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B			0x06000020>,
1088			   <IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B			0x06000020>;
1089	};
1090
1091	/* Apalis UART1 */
1092	pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
1093		fsl,pins = /* Apalis UART1_DTR */
1094			   <IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06			0x00000021>,
1095			   /* Apalis UART1_DSR */
1096			   <IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07			0x00000021>,
1097			   /* Apalis UART1_DCD */
1098			   <IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10			0x00000021>,
1099			   /* Apalis UART1_RI */
1100			   <IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11			0x00000021>;
1101	};
1102
1103	/* Apalis UART4 */
1104	pinctrl_lpuart2: lpuart2grp {
1105		fsl,pins = <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX			0x06000020>,
1106			   <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX			0x06000020>;
1107	};
1108
1109	/* Apalis UART2 */
1110	pinctrl_lpuart3: lpuart3grp {
1111		fsl,pins = <IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX			0x06000020>,
1112			   <IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX			0x06000020>,
1113			   <IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B		0x06000020>,
1114			   <IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B		0x06000020>;
1115	};
1116
1117	/* Apalis TS_2 */
1118	pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp {
1119		fsl,pins = <IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06		0x00000021>;
1120	};
1121
1122	/* Apalis LCD1_G6+7 */
1123	pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
1124		fsl,pins = /* Apalis LCD1_G6 */
1125			   <IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12		0x00000021>,
1126			   /* Apalis LCD1_G7 */
1127			   <IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x00000021>;
1128	};
1129
1130	/* Apalis TS_3 */
1131	pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp {
1132		fsl,pins = <IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07		0x00000021>;
1133	};
1134
1135	/* Apalis TS_4 */
1136	pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
1137		fsl,pins = <IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22		0x00000021>;
1138	};
1139
1140	/* Apalis TS_1 */
1141	pinctrl_mlb_gpios: mlbgpiosgrp {
1142		fsl,pins = <IMX8QM_MLB_CLK_LSIO_GPIO3_IO27			0x00000021>;
1143	};
1144
1145	/* Apalis MMC1_CD# */
1146	pinctrl_mmc1_cd: mmc1cdgrp {
1147		fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09			0x00000021>;
1148	};
1149
1150	pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp {
1151		fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09			0x04000021>;
1152	};
1153
1154	/* On-module PCIe_Wi-Fi */
1155	pinctrl_pcieb: pciebgrp {
1156		fsl,pins = <IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30		0x00000021>,
1157			   <IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31		0x00000021>,
1158			   <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00		0x00000021>;
1159	};
1160
1161	/* On-module PCIe_CLK_EN1 */
1162	pinctrl_pcie_sata_refclk: pciesatarefclkgrp {
1163		fsl,pins = <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11			0x00000021>;
1164	};
1165
1166	/* On-module PCIe_CLK_EN2 */
1167	pinctrl_pcie_wifi_refclk: pciewifirefclkgrp {
1168		fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11		0x00000021>;
1169	};
1170
1171	/* Apalis PWM3 */
1172	pinctrl_pwm0: pwm0grp {
1173		fsl,pins = <IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT			0x00000020>;
1174	};
1175
1176	/* Apalis PWM4 */
1177	pinctrl_pwm1: pwm1grp {
1178		fsl,pins = <IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT			0x00000020>;
1179	};
1180
1181	/* Apalis PWM1 */
1182	pinctrl_pwm2: pwm2grp {
1183		fsl,pins = <IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT			0x00000020>;
1184	};
1185
1186	/* Apalis PWM2 */
1187	pinctrl_pwm3: pwm3grp {
1188		fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT			0x00000020>;
1189	};
1190
1191	/* Apalis BKL1_PWM */
1192	pinctrl_pwm_bkl: pwmbklgrp {
1193		fsl,pins = <IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT			0x00000020>;
1194	};
1195
1196	/* Apalis LCD1_ */
1197	pinctrl_qspi1a_gpios: qspi1agpiosgrp {
1198		fsl,pins = /* Apalis LCD1_B0 */
1199			   <IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26			0x00000021>,
1200			   /* Apalis LCD1_B1 */
1201			   <IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25			0x00000021>,
1202			   /* Apalis LCD1_B2 */
1203			   <IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24			0x00000021>,
1204			   /* Apalis LCD1_B3 */
1205			   <IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23			0x00000021>,
1206			   /* Apalis LCD1_B5 */
1207			   <IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22			0x00000021>,
1208			   /* Apalis LCD1_B7 */
1209			   <IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21			0x00000021>,
1210			   /* Apalis LCD1_B4 */
1211			   <IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19			0x00000021>,
1212			   /* Apalis LCD1_B6 */
1213			   <IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20			0x00000021>;
1214	};
1215
1216	/* On-module RESET_MOCI#_DRV */
1217	pinctrl_reset_moci: resetmocigrp {
1218		fsl,pins = <IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30			0x00000021>;
1219	};
1220
1221	/* On-module I2S SGTL5000 for Apalis Analogue Audio */
1222	pinctrl_sai1: sai1grp {
1223		fsl,pins = <IMX8QM_SAI1_TXD_AUD_SAI1_TXD			0xc600006c>,
1224			   <IMX8QM_SAI1_RXD_AUD_SAI1_RXD			0xc600004c>,
1225			   <IMX8QM_SAI1_TXC_AUD_SAI1_TXC			0xc600004c>,
1226			   <IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS			0xc600004c>;
1227	};
1228
1229	/* Apalis SATA1_ACT# */
1230	pinctrl_sata1_act: sata1actgrp {
1231		fsl,pins = <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08			0x00000021>;
1232	};
1233
1234	/* Apalis SD1_CD# */
1235	pinctrl_sd1_cd: sd1cdgrp {
1236		fsl,pins = <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12			0x00000021>;
1237	};
1238
1239	/* On-module I2S SGTL5000 SYS_MCLK */
1240	pinctrl_sgtl5000: sgtl5000grp {
1241		fsl,pins = <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0			0xc600004c>;
1242	};
1243
1244	/* Apalis LCD1_ */
1245	pinctrl_sim0_gpios: sim0gpiosgrp {
1246		fsl,pins = /* Apalis LCD1_G5 */
1247			   <IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00			0x00000021>,
1248			   /* Apalis LCD1_G3 */
1249			   <IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05		0x00000021>,
1250			   /* Apalis TS_5 */
1251			   <IMX8QM_SIM0_IO_LSIO_GPIO0_IO02			0x00000021>,
1252			   /* Apalis LCD1_G4 */
1253			   <IMX8QM_SIM0_RST_LSIO_GPIO0_IO01			0x00000021>;
1254	};
1255
1256	/* Apalis SPDIF */
1257	pinctrl_spdif0: spdif0grp {
1258		fsl,pins = <IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX			0xc6000040>,
1259			   <IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX			0xc6000040>;
1260	};
1261
1262	pinctrl_touchctrl_gpios: touchctrlgpiosgrp {
1263		fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04			0x00000021>,
1264			   <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05			0x00000041>,
1265			   <IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17			0x00000021>,
1266			   <IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21			0x00000041>;
1267	};
1268
1269	pinctrl_touchctrl_idle: touchctrlidlegrp {
1270		fsl,pins = <IMX8QM_ADC_IN4_LSIO_GPIO3_IO22			0x00000021>,
1271			   <IMX8QM_ADC_IN5_LSIO_GPIO3_IO23			0x00000021>,
1272			   <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24			0x00000021>,
1273			   <IMX8QM_ADC_IN7_LSIO_GPIO3_IO25			0x00000021>;
1274	};
1275
1276	/* On-module USB HSIC HUB (active) */
1277	pinctrl_usb_hsic_active: usbh1activegrp {
1278		fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA		0x000000cf>,
1279			   <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0x000000ff>;
1280	};
1281
1282	/* On-module USB HSIC HUB (idle) */
1283	pinctrl_usb_hsic_idle: usbh1idlegrp {
1284		fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA		0x000000cf>,
1285			   <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0x000000cf>;
1286	};
1287
1288	/* On-module USB HSIC HUB */
1289	pinctrl_usb3503a: usb3503agrp {
1290		fsl,pins = /* On-module HSIC_HUB_CONNECT */
1291			   <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31			0x00000041>,
1292			   /* On-module HSIC_INT_N */
1293			   <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01			0x00000021>,
1294			   /* On-module HSIC_RESET_N */
1295			   <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02			0x00000041>;
1296	};
1297
1298	/* Apalis USBH_EN */
1299	pinctrl_usbh_en: usbhengrp {
1300		fsl,pins = <IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04			0x00000021>;
1301	};
1302
1303	/* Apalis USBO1 */
1304	pinctrl_usbotg1: usbotg1grp {
1305		fsl,pins = /* Apalis USBO1_EN */
1306			   <IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021>,
1307			   /* Apalis USBO1_OC# */
1308			   <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC			0x04000021>;
1309	};
1310
1311	/* On-module eMMC */
1312	pinctrl_usdhc1: usdhc1grp {
1313		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041>,
1314			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021>,
1315			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021>,
1316			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021>,
1317			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021>,
1318			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021>,
1319			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021>,
1320			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021>,
1321			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021>,
1322			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021>,
1323			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000041>,
1324			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000021>;
1325	};
1326
1327	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1328		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000040>,
1329			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000020>,
1330			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000020>,
1331			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000020>,
1332			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000020>,
1333			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000020>,
1334			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000020>,
1335			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000020>,
1336			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000020>,
1337			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000020>,
1338			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000040>,
1339			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000020>;
1340	};
1341
1342	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1343		fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK			0x06000040>,
1344			   <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD			0x00000020>,
1345			   <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000020>,
1346			   <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000020>,
1347			   <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000020>,
1348			   <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000020>,
1349			   <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000020>,
1350			   <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000020>,
1351			   <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000020>,
1352			   <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000020>,
1353			   <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE		0x06000040>,
1354			   <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x00000020>;
1355	};
1356
1357	/* Apalis TS_6 */
1358	pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
1359		fsl,pins = <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23		0x00000021>;
1360	};
1361
1362	/* Apalis MMC1 */
1363	pinctrl_usdhc2_4bit: usdhc2grp4bitgrp {
1364		fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041>,
1365			   <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021>,
1366			   <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000021>,
1367			   <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000021>,
1368			   <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000021>,
1369			   <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000021>,
1370			   /* On-module PMIC use */
1371			   <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021>;
1372	};
1373
1374	pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp {
1375		fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000040>,
1376			   <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000020>,
1377			   <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000020>,
1378			   <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000020>,
1379			   <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000020>,
1380			   <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000020>,
1381			   /* On-module PMIC use */
1382			   <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021>;
1383	};
1384
1385	pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp {
1386		fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000040>,
1387			   <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000020>,
1388			   <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x00000020>,
1389			   <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x00000020>,
1390			   <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x00000020>,
1391			   <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x00000020>,
1392			   /* On-module PMIC use */
1393			   <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021>;
1394	};
1395
1396	pinctrl_usdhc2_8bit: usdhc2grp8bitgrp {
1397		fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000021>,
1398			   <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000021>,
1399			   <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000021>,
1400			   <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000021>;
1401	};
1402
1403	pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp {
1404		fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000020>,
1405			   <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000020>,
1406			   <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000020>,
1407			   <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000020>;
1408	};
1409
1410	pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp {
1411		fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x00000020>,
1412			   <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x00000020>,
1413			   <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x00000020>,
1414			   <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x00000020>;
1415	};
1416
1417	pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp {
1418		fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x04000061>,
1419			   <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x04000061>,
1420			   <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0		0x04000061>,
1421			   <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1		0x04000061>,
1422			   <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2		0x04000061>,
1423			   <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3		0x04000061>,
1424			   /* On-module PMIC use */
1425			   <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021>;
1426	};
1427
1428	pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp {
1429		fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4		0x04000061>,
1430			   <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5		0x04000061>,
1431			   <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6		0x04000061>,
1432			   <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7		0x04000061>;
1433	};
1434
1435	/* Apalis SD1 */
1436	pinctrl_usdhc3: usdhc3grp {
1437		fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041>,
1438			   <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021>,
1439			   <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021>,
1440			   <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021>,
1441			   <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021>,
1442			   <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021>,
1443			   /* On-module PMIC use */
1444			   <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021>;
1445	};
1446
1447	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1448		fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041>,
1449			   <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021>,
1450			   <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021>,
1451			   <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021>,
1452			   <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021>,
1453			   <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021>,
1454			   /* On-module PMIC use */
1455			   <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021>;
1456	};
1457
1458	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1459		fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK			0x06000041>,
1460			   <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD			0x00000021>,
1461			   <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0		0x00000021>,
1462			   <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1		0x00000021>,
1463			   <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2		0x00000021>,
1464			   <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3		0x00000021>,
1465			   /* On-module PMIC use */
1466			   <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT		0x00000021>;
1467	};
1468
1469	/* On-module Wi-Fi */
1470	pinctrl_wifi: wifigrp {
1471		fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */
1472			   <IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x06000021>,
1473			   /* On-module Wi-Fi_PCIE_W_DISABLE */
1474			   <IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24		0x06000021>;
1475	};
1476
1477	pinctrl_wifi_pdn: wifipdngrp {
1478		fsl,pins = /* On-module Wi-Fi_POWER_DOWN */
1479			   <IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0x06000021>;
1480	};
1481};
1482