1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018 NXP 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/memreserve/ 0x80000000 0x00010000; 11 12/ { 13 compatible = "fsl,lx2160a"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 // 8 clusters having 2 Cortex-A72 cores each 23 cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a72"; 26 enable-method = "psci"; 27 reg = <0x0>; 28 clocks = <&clockgen 1 0>; 29 d-cache-size = <0x8000>; 30 d-cache-line-size = <64>; 31 d-cache-sets = <128>; 32 i-cache-size = <0xC000>; 33 i-cache-line-size = <64>; 34 i-cache-sets = <192>; 35 next-level-cache = <&cluster0_l2>; 36 }; 37 38 cpu@1 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a72"; 41 enable-method = "psci"; 42 reg = <0x1>; 43 clocks = <&clockgen 1 0>; 44 d-cache-size = <0x8000>; 45 d-cache-line-size = <64>; 46 d-cache-sets = <128>; 47 i-cache-size = <0xC000>; 48 i-cache-line-size = <64>; 49 i-cache-sets = <192>; 50 next-level-cache = <&cluster0_l2>; 51 }; 52 53 cpu@100 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a72"; 56 enable-method = "psci"; 57 reg = <0x100>; 58 clocks = <&clockgen 1 1>; 59 d-cache-size = <0x8000>; 60 d-cache-line-size = <64>; 61 d-cache-sets = <128>; 62 i-cache-size = <0xC000>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <192>; 65 next-level-cache = <&cluster1_l2>; 66 }; 67 68 cpu@101 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a72"; 71 enable-method = "psci"; 72 reg = <0x101>; 73 clocks = <&clockgen 1 1>; 74 d-cache-size = <0x8000>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 i-cache-size = <0xC000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <192>; 80 next-level-cache = <&cluster1_l2>; 81 }; 82 83 cpu@200 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a72"; 86 enable-method = "psci"; 87 reg = <0x200>; 88 clocks = <&clockgen 1 2>; 89 d-cache-size = <0x8000>; 90 d-cache-line-size = <64>; 91 d-cache-sets = <128>; 92 i-cache-size = <0xC000>; 93 i-cache-line-size = <64>; 94 i-cache-sets = <192>; 95 next-level-cache = <&cluster2_l2>; 96 }; 97 98 cpu@201 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a72"; 101 enable-method = "psci"; 102 reg = <0x201>; 103 clocks = <&clockgen 1 2>; 104 d-cache-size = <0x8000>; 105 d-cache-line-size = <64>; 106 d-cache-sets = <128>; 107 i-cache-size = <0xC000>; 108 i-cache-line-size = <64>; 109 i-cache-sets = <192>; 110 next-level-cache = <&cluster2_l2>; 111 }; 112 113 cpu@300 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a72"; 116 enable-method = "psci"; 117 reg = <0x300>; 118 clocks = <&clockgen 1 3>; 119 d-cache-size = <0x8000>; 120 d-cache-line-size = <64>; 121 d-cache-sets = <128>; 122 i-cache-size = <0xC000>; 123 i-cache-line-size = <64>; 124 i-cache-sets = <192>; 125 next-level-cache = <&cluster3_l2>; 126 }; 127 128 cpu@301 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a72"; 131 enable-method = "psci"; 132 reg = <0x301>; 133 clocks = <&clockgen 1 3>; 134 d-cache-size = <0x8000>; 135 d-cache-line-size = <64>; 136 d-cache-sets = <128>; 137 i-cache-size = <0xC000>; 138 i-cache-line-size = <64>; 139 i-cache-sets = <192>; 140 next-level-cache = <&cluster3_l2>; 141 }; 142 143 cpu@400 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a72"; 146 enable-method = "psci"; 147 reg = <0x400>; 148 clocks = <&clockgen 1 4>; 149 d-cache-size = <0x8000>; 150 d-cache-line-size = <64>; 151 d-cache-sets = <128>; 152 i-cache-size = <0xC000>; 153 i-cache-line-size = <64>; 154 i-cache-sets = <192>; 155 next-level-cache = <&cluster4_l2>; 156 }; 157 158 cpu@401 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a72"; 161 enable-method = "psci"; 162 reg = <0x401>; 163 clocks = <&clockgen 1 4>; 164 d-cache-size = <0x8000>; 165 d-cache-line-size = <64>; 166 d-cache-sets = <128>; 167 i-cache-size = <0xC000>; 168 i-cache-line-size = <64>; 169 i-cache-sets = <192>; 170 next-level-cache = <&cluster4_l2>; 171 }; 172 173 cpu@500 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a72"; 176 enable-method = "psci"; 177 reg = <0x500>; 178 clocks = <&clockgen 1 5>; 179 d-cache-size = <0x8000>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <128>; 182 i-cache-size = <0xC000>; 183 i-cache-line-size = <64>; 184 i-cache-sets = <192>; 185 next-level-cache = <&cluster5_l2>; 186 }; 187 188 cpu@501 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a72"; 191 enable-method = "psci"; 192 reg = <0x501>; 193 clocks = <&clockgen 1 5>; 194 d-cache-size = <0x8000>; 195 d-cache-line-size = <64>; 196 d-cache-sets = <128>; 197 i-cache-size = <0xC000>; 198 i-cache-line-size = <64>; 199 i-cache-sets = <192>; 200 next-level-cache = <&cluster5_l2>; 201 }; 202 203 cpu@600 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a72"; 206 enable-method = "psci"; 207 reg = <0x600>; 208 clocks = <&clockgen 1 6>; 209 d-cache-size = <0x8000>; 210 d-cache-line-size = <64>; 211 d-cache-sets = <128>; 212 i-cache-size = <0xC000>; 213 i-cache-line-size = <64>; 214 i-cache-sets = <192>; 215 next-level-cache = <&cluster6_l2>; 216 }; 217 218 cpu@601 { 219 device_type = "cpu"; 220 compatible = "arm,cortex-a72"; 221 enable-method = "psci"; 222 reg = <0x601>; 223 clocks = <&clockgen 1 6>; 224 d-cache-size = <0x8000>; 225 d-cache-line-size = <64>; 226 d-cache-sets = <128>; 227 i-cache-size = <0xC000>; 228 i-cache-line-size = <64>; 229 i-cache-sets = <192>; 230 next-level-cache = <&cluster6_l2>; 231 }; 232 233 cpu@700 { 234 device_type = "cpu"; 235 compatible = "arm,cortex-a72"; 236 enable-method = "psci"; 237 reg = <0x700>; 238 clocks = <&clockgen 1 7>; 239 d-cache-size = <0x8000>; 240 d-cache-line-size = <64>; 241 d-cache-sets = <128>; 242 i-cache-size = <0xC000>; 243 i-cache-line-size = <64>; 244 i-cache-sets = <192>; 245 next-level-cache = <&cluster7_l2>; 246 }; 247 248 cpu@701 { 249 device_type = "cpu"; 250 compatible = "arm,cortex-a72"; 251 enable-method = "psci"; 252 reg = <0x701>; 253 clocks = <&clockgen 1 7>; 254 d-cache-size = <0x8000>; 255 d-cache-line-size = <64>; 256 d-cache-sets = <128>; 257 i-cache-size = <0xC000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <192>; 260 next-level-cache = <&cluster7_l2>; 261 }; 262 263 cluster0_l2: l2-cache0 { 264 compatible = "cache"; 265 cache-size = <0x100000>; 266 cache-line-size = <64>; 267 cache-sets = <1024>; 268 cache-level = <2>; 269 }; 270 271 cluster1_l2: l2-cache1 { 272 compatible = "cache"; 273 cache-size = <0x100000>; 274 cache-line-size = <64>; 275 cache-sets = <1024>; 276 cache-level = <2>; 277 }; 278 279 cluster2_l2: l2-cache2 { 280 compatible = "cache"; 281 cache-size = <0x100000>; 282 cache-line-size = <64>; 283 cache-sets = <1024>; 284 cache-level = <2>; 285 }; 286 287 cluster3_l2: l2-cache3 { 288 compatible = "cache"; 289 cache-size = <0x100000>; 290 cache-line-size = <64>; 291 cache-sets = <1024>; 292 cache-level = <2>; 293 }; 294 295 cluster4_l2: l2-cache4 { 296 compatible = "cache"; 297 cache-size = <0x100000>; 298 cache-line-size = <64>; 299 cache-sets = <1024>; 300 cache-level = <2>; 301 }; 302 303 cluster5_l2: l2-cache5 { 304 compatible = "cache"; 305 cache-size = <0x100000>; 306 cache-line-size = <64>; 307 cache-sets = <1024>; 308 cache-level = <2>; 309 }; 310 311 cluster6_l2: l2-cache6 { 312 compatible = "cache"; 313 cache-size = <0x100000>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 }; 318 319 cluster7_l2: l2-cache7 { 320 compatible = "cache"; 321 cache-size = <0x100000>; 322 cache-line-size = <64>; 323 cache-sets = <1024>; 324 cache-level = <2>; 325 }; 326 }; 327 328 gic: interrupt-controller@6000000 { 329 compatible = "arm,gic-v3"; 330 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 331 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 332 // SGI_base) 333 <0x0 0x0c0c0000 0 0x2000>, // GICC 334 <0x0 0x0c0d0000 0 0x1000>, // GICH 335 <0x0 0x0c0e0000 0 0x20000>; // GICV 336 #interrupt-cells = <3>; 337 #address-cells = <2>; 338 #size-cells = <2>; 339 ranges; 340 interrupt-controller; 341 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 342 343 its: gic-its@6020000 { 344 compatible = "arm,gic-v3-its"; 345 msi-controller; 346 reg = <0x0 0x6020000 0 0x20000>; 347 }; 348 }; 349 350 timer { 351 compatible = "arm,armv8-timer"; 352 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 356 }; 357 358 pmu { 359 compatible = "arm,cortex-a72-pmu"; 360 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 361 }; 362 363 psci { 364 compatible = "arm,psci-0.2"; 365 method = "smc"; 366 }; 367 368 memory@80000000 { 369 // DRAM space - 1, size : 2 GB DRAM 370 device_type = "memory"; 371 reg = <0x00000000 0x80000000 0 0x80000000>; 372 }; 373 374 ddr1: memory-controller@1080000 { 375 compatible = "fsl,qoriq-memory-controller"; 376 reg = <0x0 0x1080000 0x0 0x1000>; 377 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 378 little-endian; 379 }; 380 381 ddr2: memory-controller@1090000 { 382 compatible = "fsl,qoriq-memory-controller"; 383 reg = <0x0 0x1090000 0x0 0x1000>; 384 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 385 little-endian; 386 }; 387 388 // One clock unit-sysclk node which bootloader require during DT fix-up 389 sysclk: sysclk { 390 compatible = "fixed-clock"; 391 #clock-cells = <0>; 392 clock-frequency = <100000000>; // fixed up by bootloader 393 clock-output-names = "sysclk"; 394 }; 395 396 soc { 397 compatible = "simple-bus"; 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 402 403 crypto: crypto@8000000 { 404 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 405 fsl,sec-era = <10>; 406 #address-cells = <1>; 407 #size-cells = <1>; 408 ranges = <0x0 0x00 0x8000000 0x100000>; 409 reg = <0x00 0x8000000 0x0 0x100000>; 410 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 411 dma-coherent; 412 status = "disabled"; 413 414 sec_jr0: jr@10000 { 415 compatible = "fsl,sec-v5.0-job-ring", 416 "fsl,sec-v4.0-job-ring"; 417 reg = <0x10000 0x10000>; 418 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 419 }; 420 421 sec_jr1: jr@20000 { 422 compatible = "fsl,sec-v5.0-job-ring", 423 "fsl,sec-v4.0-job-ring"; 424 reg = <0x20000 0x10000>; 425 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 426 }; 427 428 sec_jr2: jr@30000 { 429 compatible = "fsl,sec-v5.0-job-ring", 430 "fsl,sec-v4.0-job-ring"; 431 reg = <0x30000 0x10000>; 432 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 433 }; 434 435 sec_jr3: jr@40000 { 436 compatible = "fsl,sec-v5.0-job-ring", 437 "fsl,sec-v4.0-job-ring"; 438 reg = <0x40000 0x10000>; 439 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 440 }; 441 }; 442 443 clockgen: clock-controller@1300000 { 444 compatible = "fsl,lx2160a-clockgen"; 445 reg = <0 0x1300000 0 0xa0000>; 446 #clock-cells = <2>; 447 clocks = <&sysclk>; 448 }; 449 450 dcfg: syscon@1e00000 { 451 compatible = "fsl,lx2160a-dcfg", "syscon"; 452 reg = <0x0 0x1e00000 0x0 0x10000>; 453 little-endian; 454 }; 455 456 i2c0: i2c@2000000 { 457 compatible = "fsl,vf610-i2c"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 reg = <0x0 0x2000000 0x0 0x10000>; 461 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 462 clock-names = "i2c"; 463 clocks = <&clockgen 4 7>; 464 scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; 465 status = "disabled"; 466 }; 467 468 i2c1: i2c@2010000 { 469 compatible = "fsl,vf610-i2c"; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 reg = <0x0 0x2010000 0x0 0x10000>; 473 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 474 clock-names = "i2c"; 475 clocks = <&clockgen 4 7>; 476 status = "disabled"; 477 }; 478 479 i2c2: i2c@2020000 { 480 compatible = "fsl,vf610-i2c"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 reg = <0x0 0x2020000 0x0 0x10000>; 484 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 485 clock-names = "i2c"; 486 clocks = <&clockgen 4 7>; 487 status = "disabled"; 488 }; 489 490 i2c3: i2c@2030000 { 491 compatible = "fsl,vf610-i2c"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 reg = <0x0 0x2030000 0x0 0x10000>; 495 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 496 clock-names = "i2c"; 497 clocks = <&clockgen 4 7>; 498 status = "disabled"; 499 }; 500 501 i2c4: i2c@2040000 { 502 compatible = "fsl,vf610-i2c"; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 reg = <0x0 0x2040000 0x0 0x10000>; 506 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 507 clock-names = "i2c"; 508 clocks = <&clockgen 4 7>; 509 scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; 510 status = "disabled"; 511 }; 512 513 i2c5: i2c@2050000 { 514 compatible = "fsl,vf610-i2c"; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <0x0 0x2050000 0x0 0x10000>; 518 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 519 clock-names = "i2c"; 520 clocks = <&clockgen 4 7>; 521 status = "disabled"; 522 }; 523 524 i2c6: i2c@2060000 { 525 compatible = "fsl,vf610-i2c"; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 reg = <0x0 0x2060000 0x0 0x10000>; 529 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 530 clock-names = "i2c"; 531 clocks = <&clockgen 4 7>; 532 status = "disabled"; 533 }; 534 535 i2c7: i2c@2070000 { 536 compatible = "fsl,vf610-i2c"; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 reg = <0x0 0x2070000 0x0 0x10000>; 540 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 541 clock-names = "i2c"; 542 clocks = <&clockgen 4 7>; 543 status = "disabled"; 544 }; 545 546 fspi: spi@20c0000 { 547 compatible = "nxp,lx2160a-fspi"; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 reg = <0x0 0x20c0000 0x0 0x10000>, 551 <0x0 0x20000000 0x0 0x10000000>; 552 reg-names = "fspi_base", "fspi_mmap"; 553 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 555 clock-names = "fspi_en", "fspi"; 556 status = "disabled"; 557 }; 558 559 esdhc0: esdhc@2140000 { 560 compatible = "fsl,esdhc"; 561 reg = <0x0 0x2140000 0x0 0x10000>; 562 interrupts = <0 28 0x4>; /* Level high type */ 563 clocks = <&clockgen 4 1>; 564 voltage-ranges = <1800 1800 3300 3300>; 565 sdhci,auto-cmd12; 566 little-endian; 567 bus-width = <4>; 568 status = "disabled"; 569 }; 570 571 esdhc1: esdhc@2150000 { 572 compatible = "fsl,esdhc"; 573 reg = <0x0 0x2150000 0x0 0x10000>; 574 interrupts = <0 63 0x4>; /* Level high type */ 575 clocks = <&clockgen 4 1>; 576 voltage-ranges = <1800 1800 3300 3300>; 577 sdhci,auto-cmd12; 578 broken-cd; 579 little-endian; 580 bus-width = <4>; 581 status = "disabled"; 582 }; 583 584 uart0: serial@21c0000 { 585 compatible = "arm,sbsa-uart","arm,pl011"; 586 reg = <0x0 0x21c0000 0x0 0x1000>; 587 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 588 current-speed = <115200>; 589 status = "disabled"; 590 }; 591 592 uart1: serial@21d0000 { 593 compatible = "arm,sbsa-uart","arm,pl011"; 594 reg = <0x0 0x21d0000 0x0 0x1000>; 595 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 596 current-speed = <115200>; 597 status = "disabled"; 598 }; 599 600 uart2: serial@21e0000 { 601 compatible = "arm,sbsa-uart","arm,pl011"; 602 reg = <0x0 0x21e0000 0x0 0x1000>; 603 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 604 current-speed = <115200>; 605 status = "disabled"; 606 }; 607 608 uart3: serial@21f0000 { 609 compatible = "arm,sbsa-uart","arm,pl011"; 610 reg = <0x0 0x21f0000 0x0 0x1000>; 611 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 612 current-speed = <115200>; 613 status = "disabled"; 614 }; 615 616 gpio0: gpio@2300000 { 617 compatible = "fsl,qoriq-gpio"; 618 reg = <0x0 0x2300000 0x0 0x10000>; 619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 620 gpio-controller; 621 little-endian; 622 #gpio-cells = <2>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 }; 626 627 gpio1: gpio@2310000 { 628 compatible = "fsl,qoriq-gpio"; 629 reg = <0x0 0x2310000 0x0 0x10000>; 630 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 631 gpio-controller; 632 little-endian; 633 #gpio-cells = <2>; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 }; 637 638 gpio2: gpio@2320000 { 639 compatible = "fsl,qoriq-gpio"; 640 reg = <0x0 0x2320000 0x0 0x10000>; 641 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 642 gpio-controller; 643 little-endian; 644 #gpio-cells = <2>; 645 interrupt-controller; 646 #interrupt-cells = <2>; 647 }; 648 649 gpio3: gpio@2330000 { 650 compatible = "fsl,qoriq-gpio"; 651 reg = <0x0 0x2330000 0x0 0x10000>; 652 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 653 gpio-controller; 654 little-endian; 655 #gpio-cells = <2>; 656 interrupt-controller; 657 #interrupt-cells = <2>; 658 }; 659 660 watchdog@23a0000 { 661 compatible = "arm,sbsa-gwdt"; 662 reg = <0x0 0x23a0000 0 0x1000>, 663 <0x0 0x2390000 0 0x1000>; 664 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 665 timeout-sec = <30>; 666 }; 667 668 usb0: usb@3100000 { 669 compatible = "snps,dwc3"; 670 reg = <0x0 0x3100000 0x0 0x10000>; 671 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 672 dr_mode = "host"; 673 snps,quirk-frame-length-adjustment = <0x20>; 674 snps,dis_rxdet_inp3_quirk; 675 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 676 status = "disabled"; 677 }; 678 679 usb1: usb@3110000 { 680 compatible = "snps,dwc3"; 681 reg = <0x0 0x3110000 0x0 0x10000>; 682 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 683 dr_mode = "host"; 684 snps,quirk-frame-length-adjustment = <0x20>; 685 snps,dis_rxdet_inp3_quirk; 686 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 687 status = "disabled"; 688 }; 689 690 smmu: iommu@5000000 { 691 compatible = "arm,mmu-500"; 692 reg = <0 0x5000000 0 0x800000>; 693 #iommu-cells = <1>; 694 #global-interrupts = <14>; 695 // global secure fault 696 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 697 // combined secure 698 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 699 // global non-secure fault 700 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 701 // combined non-secure 702 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 703 // performance counter interrupts 0-9 704 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 714 // per context interrupt, 64 interrupts 715 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 779 dma-coherent; 780 }; 781 782 fsl_mc: fsl-mc@80c000000 { 783 compatible = "fsl,qoriq-mc"; 784 reg = <0x00000008 0x0c000000 0 0x40>, 785 <0x00000000 0x08340000 0 0x40000>; 786 msi-parent = <&its>; 787 /* iommu-map property is fixed up by u-boot */ 788 iommu-map = <0 &smmu 0 0>; 789 dma-coherent; 790 #address-cells = <3>; 791 #size-cells = <1>; 792 793 /* 794 * Region type 0x0 - MC portals 795 * Region type 0x1 - QBMAN portals 796 */ 797 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 798 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 799 800 /* 801 * Define the maximum number of MACs present on the SoC. 802 */ 803 dpmacs { 804 #address-cells = <1>; 805 #size-cells = <0>; 806 807 dpmac1: dpmac@1 { 808 compatible = "fsl,qoriq-mc-dpmac"; 809 reg = <0x1>; 810 }; 811 812 dpmac2: dpmac@2 { 813 compatible = "fsl,qoriq-mc-dpmac"; 814 reg = <0x2>; 815 }; 816 817 dpmac3: dpmac@3 { 818 compatible = "fsl,qoriq-mc-dpmac"; 819 reg = <0x3>; 820 }; 821 822 dpmac4: dpmac@4 { 823 compatible = "fsl,qoriq-mc-dpmac"; 824 reg = <0x4>; 825 }; 826 827 dpmac5: dpmac@5 { 828 compatible = "fsl,qoriq-mc-dpmac"; 829 reg = <0x5>; 830 }; 831 832 dpmac6: dpmac@6 { 833 compatible = "fsl,qoriq-mc-dpmac"; 834 reg = <0x6>; 835 }; 836 837 dpmac7: dpmac@7 { 838 compatible = "fsl,qoriq-mc-dpmac"; 839 reg = <0x7>; 840 }; 841 842 dpmac8: dpmac@8 { 843 compatible = "fsl,qoriq-mc-dpmac"; 844 reg = <0x8>; 845 }; 846 847 dpmac9: dpmac@9 { 848 compatible = "fsl,qoriq-mc-dpmac"; 849 reg = <0x9>; 850 }; 851 852 dpmac10: dpmac@a { 853 compatible = "fsl,qoriq-mc-dpmac"; 854 reg = <0xa>; 855 }; 856 857 dpmac11: dpmac@b { 858 compatible = "fsl,qoriq-mc-dpmac"; 859 reg = <0xb>; 860 }; 861 862 dpmac12: dpmac@c { 863 compatible = "fsl,qoriq-mc-dpmac"; 864 reg = <0xc>; 865 }; 866 867 dpmac13: dpmac@d { 868 compatible = "fsl,qoriq-mc-dpmac"; 869 reg = <0xd>; 870 }; 871 872 dpmac14: dpmac@e { 873 compatible = "fsl,qoriq-mc-dpmac"; 874 reg = <0xe>; 875 }; 876 877 dpmac15: dpmac@f { 878 compatible = "fsl,qoriq-mc-dpmac"; 879 reg = <0xf>; 880 }; 881 882 dpmac16: dpmac@10 { 883 compatible = "fsl,qoriq-mc-dpmac"; 884 reg = <0x10>; 885 }; 886 887 dpmac17: dpmac@11 { 888 compatible = "fsl,qoriq-mc-dpmac"; 889 reg = <0x11>; 890 }; 891 892 dpmac18: dpmac@12 { 893 compatible = "fsl,qoriq-mc-dpmac"; 894 reg = <0x12>; 895 }; 896 }; 897 }; 898 }; 899}; 900