1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Device Tree Include file for Layerscape-LX2160A family SoC.
4//
5// Copyright 2018 NXP
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/memreserve/ 0x80000000 0x00010000;
11
12/ {
13	compatible = "fsl,lx2160a";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		// 8 clusters having 2 Cortex-A72 cores each
23		cpu@0 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a72";
26			enable-method = "psci";
27			reg = <0x0>;
28			clocks = <&clockgen 1 0>;
29			d-cache-size = <0x8000>;
30			d-cache-line-size = <64>;
31			d-cache-sets = <128>;
32			i-cache-size = <0xC000>;
33			i-cache-line-size = <64>;
34			i-cache-sets = <192>;
35			next-level-cache = <&cluster0_l2>;
36			cpu-idle-states = <&cpu_pw20>;
37		};
38
39		cpu@1 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a72";
42			enable-method = "psci";
43			reg = <0x1>;
44			clocks = <&clockgen 1 0>;
45			d-cache-size = <0x8000>;
46			d-cache-line-size = <64>;
47			d-cache-sets = <128>;
48			i-cache-size = <0xC000>;
49			i-cache-line-size = <64>;
50			i-cache-sets = <192>;
51			next-level-cache = <&cluster0_l2>;
52			cpu-idle-states = <&cpu_pw20>;
53		};
54
55		cpu@100 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a72";
58			enable-method = "psci";
59			reg = <0x100>;
60			clocks = <&clockgen 1 1>;
61			d-cache-size = <0x8000>;
62			d-cache-line-size = <64>;
63			d-cache-sets = <128>;
64			i-cache-size = <0xC000>;
65			i-cache-line-size = <64>;
66			i-cache-sets = <192>;
67			next-level-cache = <&cluster1_l2>;
68			cpu-idle-states = <&cpu_pw20>;
69		};
70
71		cpu@101 {
72			device_type = "cpu";
73			compatible = "arm,cortex-a72";
74			enable-method = "psci";
75			reg = <0x101>;
76			clocks = <&clockgen 1 1>;
77			d-cache-size = <0x8000>;
78			d-cache-line-size = <64>;
79			d-cache-sets = <128>;
80			i-cache-size = <0xC000>;
81			i-cache-line-size = <64>;
82			i-cache-sets = <192>;
83			next-level-cache = <&cluster1_l2>;
84			cpu-idle-states = <&cpu_pw20>;
85		};
86
87		cpu@200 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a72";
90			enable-method = "psci";
91			reg = <0x200>;
92			clocks = <&clockgen 1 2>;
93			d-cache-size = <0x8000>;
94			d-cache-line-size = <64>;
95			d-cache-sets = <128>;
96			i-cache-size = <0xC000>;
97			i-cache-line-size = <64>;
98			i-cache-sets = <192>;
99			next-level-cache = <&cluster2_l2>;
100			cpu-idle-states = <&cpu_pw20>;
101		};
102
103		cpu@201 {
104			device_type = "cpu";
105			compatible = "arm,cortex-a72";
106			enable-method = "psci";
107			reg = <0x201>;
108			clocks = <&clockgen 1 2>;
109			d-cache-size = <0x8000>;
110			d-cache-line-size = <64>;
111			d-cache-sets = <128>;
112			i-cache-size = <0xC000>;
113			i-cache-line-size = <64>;
114			i-cache-sets = <192>;
115			next-level-cache = <&cluster2_l2>;
116			cpu-idle-states = <&cpu_pw20>;
117		};
118
119		cpu@300 {
120			device_type = "cpu";
121			compatible = "arm,cortex-a72";
122			enable-method = "psci";
123			reg = <0x300>;
124			clocks = <&clockgen 1 3>;
125			d-cache-size = <0x8000>;
126			d-cache-line-size = <64>;
127			d-cache-sets = <128>;
128			i-cache-size = <0xC000>;
129			i-cache-line-size = <64>;
130			i-cache-sets = <192>;
131			next-level-cache = <&cluster3_l2>;
132			cpu-idle-states = <&cpu_pw20>;
133		};
134
135		cpu@301 {
136			device_type = "cpu";
137			compatible = "arm,cortex-a72";
138			enable-method = "psci";
139			reg = <0x301>;
140			clocks = <&clockgen 1 3>;
141			d-cache-size = <0x8000>;
142			d-cache-line-size = <64>;
143			d-cache-sets = <128>;
144			i-cache-size = <0xC000>;
145			i-cache-line-size = <64>;
146			i-cache-sets = <192>;
147			next-level-cache = <&cluster3_l2>;
148			cpu-idle-states = <&cpu_pw20>;
149		};
150
151		cpu@400 {
152			device_type = "cpu";
153			compatible = "arm,cortex-a72";
154			enable-method = "psci";
155			reg = <0x400>;
156			clocks = <&clockgen 1 4>;
157			d-cache-size = <0x8000>;
158			d-cache-line-size = <64>;
159			d-cache-sets = <128>;
160			i-cache-size = <0xC000>;
161			i-cache-line-size = <64>;
162			i-cache-sets = <192>;
163			next-level-cache = <&cluster4_l2>;
164			cpu-idle-states = <&cpu_pw20>;
165		};
166
167		cpu@401 {
168			device_type = "cpu";
169			compatible = "arm,cortex-a72";
170			enable-method = "psci";
171			reg = <0x401>;
172			clocks = <&clockgen 1 4>;
173			d-cache-size = <0x8000>;
174			d-cache-line-size = <64>;
175			d-cache-sets = <128>;
176			i-cache-size = <0xC000>;
177			i-cache-line-size = <64>;
178			i-cache-sets = <192>;
179			next-level-cache = <&cluster4_l2>;
180			cpu-idle-states = <&cpu_pw20>;
181		};
182
183		cpu@500 {
184			device_type = "cpu";
185			compatible = "arm,cortex-a72";
186			enable-method = "psci";
187			reg = <0x500>;
188			clocks = <&clockgen 1 5>;
189			d-cache-size = <0x8000>;
190			d-cache-line-size = <64>;
191			d-cache-sets = <128>;
192			i-cache-size = <0xC000>;
193			i-cache-line-size = <64>;
194			i-cache-sets = <192>;
195			next-level-cache = <&cluster5_l2>;
196			cpu-idle-states = <&cpu_pw20>;
197		};
198
199		cpu@501 {
200			device_type = "cpu";
201			compatible = "arm,cortex-a72";
202			enable-method = "psci";
203			reg = <0x501>;
204			clocks = <&clockgen 1 5>;
205			d-cache-size = <0x8000>;
206			d-cache-line-size = <64>;
207			d-cache-sets = <128>;
208			i-cache-size = <0xC000>;
209			i-cache-line-size = <64>;
210			i-cache-sets = <192>;
211			next-level-cache = <&cluster5_l2>;
212			cpu-idle-states = <&cpu_pw20>;
213		};
214
215		cpu@600 {
216			device_type = "cpu";
217			compatible = "arm,cortex-a72";
218			enable-method = "psci";
219			reg = <0x600>;
220			clocks = <&clockgen 1 6>;
221			d-cache-size = <0x8000>;
222			d-cache-line-size = <64>;
223			d-cache-sets = <128>;
224			i-cache-size = <0xC000>;
225			i-cache-line-size = <64>;
226			i-cache-sets = <192>;
227			next-level-cache = <&cluster6_l2>;
228			cpu-idle-states = <&cpu_pw20>;
229		};
230
231		cpu@601 {
232			device_type = "cpu";
233			compatible = "arm,cortex-a72";
234			enable-method = "psci";
235			reg = <0x601>;
236			clocks = <&clockgen 1 6>;
237			d-cache-size = <0x8000>;
238			d-cache-line-size = <64>;
239			d-cache-sets = <128>;
240			i-cache-size = <0xC000>;
241			i-cache-line-size = <64>;
242			i-cache-sets = <192>;
243			next-level-cache = <&cluster6_l2>;
244			cpu-idle-states = <&cpu_pw20>;
245		};
246
247		cpu@700 {
248			device_type = "cpu";
249			compatible = "arm,cortex-a72";
250			enable-method = "psci";
251			reg = <0x700>;
252			clocks = <&clockgen 1 7>;
253			d-cache-size = <0x8000>;
254			d-cache-line-size = <64>;
255			d-cache-sets = <128>;
256			i-cache-size = <0xC000>;
257			i-cache-line-size = <64>;
258			i-cache-sets = <192>;
259			next-level-cache = <&cluster7_l2>;
260			cpu-idle-states = <&cpu_pw20>;
261		};
262
263		cpu@701 {
264			device_type = "cpu";
265			compatible = "arm,cortex-a72";
266			enable-method = "psci";
267			reg = <0x701>;
268			clocks = <&clockgen 1 7>;
269			d-cache-size = <0x8000>;
270			d-cache-line-size = <64>;
271			d-cache-sets = <128>;
272			i-cache-size = <0xC000>;
273			i-cache-line-size = <64>;
274			i-cache-sets = <192>;
275			next-level-cache = <&cluster7_l2>;
276			cpu-idle-states = <&cpu_pw20>;
277		};
278
279		cluster0_l2: l2-cache0 {
280			compatible = "cache";
281			cache-size = <0x100000>;
282			cache-line-size = <64>;
283			cache-sets = <1024>;
284			cache-level = <2>;
285		};
286
287		cluster1_l2: l2-cache1 {
288			compatible = "cache";
289			cache-size = <0x100000>;
290			cache-line-size = <64>;
291			cache-sets = <1024>;
292			cache-level = <2>;
293		};
294
295		cluster2_l2: l2-cache2 {
296			compatible = "cache";
297			cache-size = <0x100000>;
298			cache-line-size = <64>;
299			cache-sets = <1024>;
300			cache-level = <2>;
301		};
302
303		cluster3_l2: l2-cache3 {
304			compatible = "cache";
305			cache-size = <0x100000>;
306			cache-line-size = <64>;
307			cache-sets = <1024>;
308			cache-level = <2>;
309		};
310
311		cluster4_l2: l2-cache4 {
312			compatible = "cache";
313			cache-size = <0x100000>;
314			cache-line-size = <64>;
315			cache-sets = <1024>;
316			cache-level = <2>;
317		};
318
319		cluster5_l2: l2-cache5 {
320			compatible = "cache";
321			cache-size = <0x100000>;
322			cache-line-size = <64>;
323			cache-sets = <1024>;
324			cache-level = <2>;
325		};
326
327		cluster6_l2: l2-cache6 {
328			compatible = "cache";
329			cache-size = <0x100000>;
330			cache-line-size = <64>;
331			cache-sets = <1024>;
332			cache-level = <2>;
333		};
334
335		cluster7_l2: l2-cache7 {
336			compatible = "cache";
337			cache-size = <0x100000>;
338			cache-line-size = <64>;
339			cache-sets = <1024>;
340			cache-level = <2>;
341		};
342
343		cpu_pw20: cpu-pw20 {
344			compatible = "arm,idle-state";
345			idle-state-name = "PW20";
346			arm,psci-suspend-param = <0x0>;
347			entry-latency-us = <2000>;
348			exit-latency-us = <2000>;
349			min-residency-us = <6000>;
350		  };
351	};
352
353	gic: interrupt-controller@6000000 {
354		compatible = "arm,gic-v3";
355		reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
356			<0x0 0x06200000 0 0x200000>, // GICR (RD_base +
357						     // SGI_base)
358			<0x0 0x0c0c0000 0 0x2000>, // GICC
359			<0x0 0x0c0d0000 0 0x1000>, // GICH
360			<0x0 0x0c0e0000 0 0x20000>; // GICV
361		#interrupt-cells = <3>;
362		#address-cells = <2>;
363		#size-cells = <2>;
364		ranges;
365		interrupt-controller;
366		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
367
368		its: gic-its@6020000 {
369			compatible = "arm,gic-v3-its";
370			msi-controller;
371			reg = <0x0 0x6020000 0 0x20000>;
372		};
373	};
374
375	timer {
376		compatible = "arm,armv8-timer";
377		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
378			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
379			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
380			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
381	};
382
383	pmu {
384		compatible = "arm,cortex-a72-pmu";
385		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
386	};
387
388	psci {
389		compatible = "arm,psci-0.2";
390		method = "smc";
391	};
392
393	memory@80000000 {
394		// DRAM space - 1, size : 2 GB DRAM
395		device_type = "memory";
396		reg = <0x00000000 0x80000000 0 0x80000000>;
397	};
398
399	ddr1: memory-controller@1080000 {
400		compatible = "fsl,qoriq-memory-controller";
401		reg = <0x0 0x1080000 0x0 0x1000>;
402		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
403		little-endian;
404	};
405
406	ddr2: memory-controller@1090000 {
407		compatible = "fsl,qoriq-memory-controller";
408		reg = <0x0 0x1090000 0x0 0x1000>;
409		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
410		little-endian;
411	};
412
413	// One clock unit-sysclk node which bootloader require during DT fix-up
414	sysclk: sysclk {
415		compatible = "fixed-clock";
416		#clock-cells = <0>;
417		clock-frequency = <100000000>; // fixed up by bootloader
418		clock-output-names = "sysclk";
419	};
420
421	soc {
422		compatible = "simple-bus";
423		#address-cells = <2>;
424		#size-cells = <2>;
425		ranges;
426		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
427
428		crypto: crypto@8000000 {
429			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
430			fsl,sec-era = <10>;
431			#address-cells = <1>;
432			#size-cells = <1>;
433			ranges = <0x0 0x00 0x8000000 0x100000>;
434			reg = <0x00 0x8000000 0x0 0x100000>;
435			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
436			dma-coherent;
437			status = "disabled";
438
439			sec_jr0: jr@10000 {
440				compatible = "fsl,sec-v5.0-job-ring",
441					     "fsl,sec-v4.0-job-ring";
442				reg        = <0x10000 0x10000>;
443				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
444			};
445
446			sec_jr1: jr@20000 {
447				compatible = "fsl,sec-v5.0-job-ring",
448					     "fsl,sec-v4.0-job-ring";
449				reg        = <0x20000 0x10000>;
450				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
451			};
452
453			sec_jr2: jr@30000 {
454				compatible = "fsl,sec-v5.0-job-ring",
455					     "fsl,sec-v4.0-job-ring";
456				reg        = <0x30000 0x10000>;
457				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
458			};
459
460			sec_jr3: jr@40000 {
461				compatible = "fsl,sec-v5.0-job-ring",
462					     "fsl,sec-v4.0-job-ring";
463				reg        = <0x40000 0x10000>;
464				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
465			};
466		};
467
468		clockgen: clock-controller@1300000 {
469			compatible = "fsl,lx2160a-clockgen";
470			reg = <0 0x1300000 0 0xa0000>;
471			#clock-cells = <2>;
472			clocks = <&sysclk>;
473		};
474
475		dcfg: syscon@1e00000 {
476			compatible = "fsl,lx2160a-dcfg", "syscon";
477			reg = <0x0 0x1e00000 0x0 0x10000>;
478			little-endian;
479		};
480
481		i2c0: i2c@2000000 {
482			compatible = "fsl,vf610-i2c";
483			#address-cells = <1>;
484			#size-cells = <0>;
485			reg = <0x0 0x2000000 0x0 0x10000>;
486			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
487			clock-names = "i2c";
488			clocks = <&clockgen 4 7>;
489			scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
490			status = "disabled";
491		};
492
493		i2c1: i2c@2010000 {
494			compatible = "fsl,vf610-i2c";
495			#address-cells = <1>;
496			#size-cells = <0>;
497			reg = <0x0 0x2010000 0x0 0x10000>;
498			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
499			clock-names = "i2c";
500			clocks = <&clockgen 4 7>;
501			status = "disabled";
502		};
503
504		i2c2: i2c@2020000 {
505			compatible = "fsl,vf610-i2c";
506			#address-cells = <1>;
507			#size-cells = <0>;
508			reg = <0x0 0x2020000 0x0 0x10000>;
509			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
510			clock-names = "i2c";
511			clocks = <&clockgen 4 7>;
512			status = "disabled";
513		};
514
515		i2c3: i2c@2030000 {
516			compatible = "fsl,vf610-i2c";
517			#address-cells = <1>;
518			#size-cells = <0>;
519			reg = <0x0 0x2030000 0x0 0x10000>;
520			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
521			clock-names = "i2c";
522			clocks = <&clockgen 4 7>;
523			status = "disabled";
524		};
525
526		i2c4: i2c@2040000 {
527			compatible = "fsl,vf610-i2c";
528			#address-cells = <1>;
529			#size-cells = <0>;
530			reg = <0x0 0x2040000 0x0 0x10000>;
531			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
532			clock-names = "i2c";
533			clocks = <&clockgen 4 7>;
534			scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
535			status = "disabled";
536		};
537
538		i2c5: i2c@2050000 {
539			compatible = "fsl,vf610-i2c";
540			#address-cells = <1>;
541			#size-cells = <0>;
542			reg = <0x0 0x2050000 0x0 0x10000>;
543			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
544			clock-names = "i2c";
545			clocks = <&clockgen 4 7>;
546			status = "disabled";
547		};
548
549		i2c6: i2c@2060000 {
550			compatible = "fsl,vf610-i2c";
551			#address-cells = <1>;
552			#size-cells = <0>;
553			reg = <0x0 0x2060000 0x0 0x10000>;
554			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
555			clock-names = "i2c";
556			clocks = <&clockgen 4 7>;
557			status = "disabled";
558		};
559
560		i2c7: i2c@2070000 {
561			compatible = "fsl,vf610-i2c";
562			#address-cells = <1>;
563			#size-cells = <0>;
564			reg = <0x0 0x2070000 0x0 0x10000>;
565			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
566			clock-names = "i2c";
567			clocks = <&clockgen 4 7>;
568			status = "disabled";
569		};
570
571		fspi: spi@20c0000 {
572			compatible = "nxp,lx2160a-fspi";
573			#address-cells = <1>;
574			#size-cells = <0>;
575			reg = <0x0 0x20c0000 0x0 0x10000>,
576			      <0x0 0x20000000 0x0 0x10000000>;
577			reg-names = "fspi_base", "fspi_mmap";
578			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
579			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
580			clock-names = "fspi_en", "fspi";
581			status = "disabled";
582		};
583
584		esdhc0: esdhc@2140000 {
585			compatible = "fsl,esdhc";
586			reg = <0x0 0x2140000 0x0 0x10000>;
587			interrupts = <0 28 0x4>; /* Level high type */
588			clocks = <&clockgen 4 1>;
589			voltage-ranges = <1800 1800 3300 3300>;
590			sdhci,auto-cmd12;
591			little-endian;
592			bus-width = <4>;
593			status = "disabled";
594		};
595
596		esdhc1: esdhc@2150000 {
597			compatible = "fsl,esdhc";
598			reg = <0x0 0x2150000 0x0 0x10000>;
599			interrupts = <0 63 0x4>; /* Level high type */
600			clocks = <&clockgen 4 1>;
601			voltage-ranges = <1800 1800 3300 3300>;
602			sdhci,auto-cmd12;
603			broken-cd;
604			little-endian;
605			bus-width = <4>;
606			status = "disabled";
607		};
608
609		uart0: serial@21c0000 {
610			compatible = "arm,sbsa-uart","arm,pl011";
611			reg = <0x0 0x21c0000 0x0 0x1000>;
612			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
613			current-speed = <115200>;
614			status = "disabled";
615		};
616
617		uart1: serial@21d0000 {
618			compatible = "arm,sbsa-uart","arm,pl011";
619			reg = <0x0 0x21d0000 0x0 0x1000>;
620			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
621			current-speed = <115200>;
622			status = "disabled";
623		};
624
625		uart2: serial@21e0000 {
626			compatible = "arm,sbsa-uart","arm,pl011";
627			reg = <0x0 0x21e0000 0x0 0x1000>;
628			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
629			current-speed = <115200>;
630			status = "disabled";
631		};
632
633		uart3: serial@21f0000 {
634			compatible = "arm,sbsa-uart","arm,pl011";
635			reg = <0x0 0x21f0000 0x0 0x1000>;
636			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
637			current-speed = <115200>;
638			status = "disabled";
639		};
640
641		gpio0: gpio@2300000 {
642			compatible = "fsl,qoriq-gpio";
643			reg = <0x0 0x2300000 0x0 0x10000>;
644			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
645			gpio-controller;
646			little-endian;
647			#gpio-cells = <2>;
648			interrupt-controller;
649			#interrupt-cells = <2>;
650		};
651
652		gpio1: gpio@2310000 {
653			compatible = "fsl,qoriq-gpio";
654			reg = <0x0 0x2310000 0x0 0x10000>;
655			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
656			gpio-controller;
657			little-endian;
658			#gpio-cells = <2>;
659			interrupt-controller;
660			#interrupt-cells = <2>;
661		};
662
663		gpio2: gpio@2320000 {
664			compatible = "fsl,qoriq-gpio";
665			reg = <0x0 0x2320000 0x0 0x10000>;
666			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
667			gpio-controller;
668			little-endian;
669			#gpio-cells = <2>;
670			interrupt-controller;
671			#interrupt-cells = <2>;
672		};
673
674		gpio3: gpio@2330000 {
675			compatible = "fsl,qoriq-gpio";
676			reg = <0x0 0x2330000 0x0 0x10000>;
677			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
678			gpio-controller;
679			little-endian;
680			#gpio-cells = <2>;
681			interrupt-controller;
682			#interrupt-cells = <2>;
683		};
684
685		watchdog@23a0000 {
686			compatible = "arm,sbsa-gwdt";
687			reg = <0x0 0x23a0000 0 0x1000>,
688			      <0x0 0x2390000 0 0x1000>;
689			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
690			timeout-sec = <30>;
691		};
692
693		usb0: usb@3100000 {
694			compatible = "snps,dwc3";
695			reg = <0x0 0x3100000 0x0 0x10000>;
696			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
697			dr_mode = "host";
698			snps,quirk-frame-length-adjustment = <0x20>;
699			snps,dis_rxdet_inp3_quirk;
700			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
701			status = "disabled";
702		};
703
704		usb1: usb@3110000 {
705			compatible = "snps,dwc3";
706			reg = <0x0 0x3110000 0x0 0x10000>;
707			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
708			dr_mode = "host";
709			snps,quirk-frame-length-adjustment = <0x20>;
710			snps,dis_rxdet_inp3_quirk;
711			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
712			status = "disabled";
713		};
714
715		sata0: sata@3200000 {
716			compatible = "fsl,lx2160a-ahci";
717			reg = <0x0 0x3200000 0x0 0x10000>,
718			      <0x7 0x100520 0x0 0x4>;
719			reg-names = "ahci", "sata-ecc";
720			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
721			clocks = <&clockgen 4 3>;
722			dma-coherent;
723			status = "disabled";
724		};
725
726		sata1: sata@3210000 {
727			compatible = "fsl,lx2160a-ahci";
728			reg = <0x0 0x3210000 0x0 0x10000>,
729			      <0x7 0x100520 0x0 0x4>;
730			reg-names = "ahci", "sata-ecc";
731			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
732			clocks = <&clockgen 4 3>;
733			dma-coherent;
734			status = "disabled";
735		};
736
737		sata2: sata@3220000 {
738			compatible = "fsl,lx2160a-ahci";
739			reg = <0x0 0x3220000 0x0 0x10000>,
740			      <0x7 0x100520 0x0 0x4>;
741			reg-names = "ahci", "sata-ecc";
742			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
743			clocks = <&clockgen 4 3>;
744			dma-coherent;
745			status = "disabled";
746		};
747
748		sata3: sata@3230000 {
749			compatible = "fsl,lx2160a-ahci";
750			reg = <0x0 0x3230000 0x0 0x10000>,
751			      <0x7 0x100520 0x0 0x4>;
752			reg-names = "ahci", "sata-ecc";
753			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
754			clocks = <&clockgen 4 3>;
755			dma-coherent;
756			status = "disabled";
757		};
758
759		smmu: iommu@5000000 {
760			compatible = "arm,mmu-500";
761			reg = <0 0x5000000 0 0x800000>;
762			#iommu-cells = <1>;
763			#global-interrupts = <14>;
764				     // global secure fault
765			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
766				     // combined secure
767				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
768				     // global non-secure fault
769				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
770				     // combined non-secure
771				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
772				     // performance counter interrupts 0-9
773				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
774				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
775				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
776				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
777				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
778				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
779				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
780				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
781				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
782				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
783				     // per context interrupt, 64 interrupts
784				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
785				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
786				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
787				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
788				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
789				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
790				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
791				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
792				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
793				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
794				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
795				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
796				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
797				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
798				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
799				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
800				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
801				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
802				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
803				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
804				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
805				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
806				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
807				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
808				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
809				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
810				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
811				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
812				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
813				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
814				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
815				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
816				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
817				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
818				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
819				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
820				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
821				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
822				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
823				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
824				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
825				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
826				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
827				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
828				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
829				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
830				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
831				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
832				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
833				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
834				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
835				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
836				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
837				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
838				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
839				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
840				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
841				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
842				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
843				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
844				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
845				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
846				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
847				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
848			dma-coherent;
849		};
850
851		ptp-timer@8b95000 {
852			compatible = "fsl,dpaa2-ptp";
853			reg = <0x0 0x8b95000 0x0 0x100>;
854			clocks = <&clockgen 4 1>;
855			little-endian;
856			fsl,extts-fifo;
857		};
858
859		fsl_mc: fsl-mc@80c000000 {
860			compatible = "fsl,qoriq-mc";
861			reg = <0x00000008 0x0c000000 0 0x40>,
862			      <0x00000000 0x08340000 0 0x40000>;
863			msi-parent = <&its>;
864			/* iommu-map property is fixed up by u-boot */
865			iommu-map = <0 &smmu 0 0>;
866			dma-coherent;
867			#address-cells = <3>;
868			#size-cells = <1>;
869
870			/*
871			 * Region type 0x0 - MC portals
872			 * Region type 0x1 - QBMAN portals
873			 */
874			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
875				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
876
877			/*
878			 * Define the maximum number of MACs present on the SoC.
879			 */
880			dpmacs {
881				#address-cells = <1>;
882				#size-cells = <0>;
883
884				dpmac1: dpmac@1 {
885					compatible = "fsl,qoriq-mc-dpmac";
886					reg = <0x1>;
887				};
888
889				dpmac2: dpmac@2 {
890					compatible = "fsl,qoriq-mc-dpmac";
891					reg = <0x2>;
892				};
893
894				dpmac3: dpmac@3 {
895					compatible = "fsl,qoriq-mc-dpmac";
896					reg = <0x3>;
897				};
898
899				dpmac4: dpmac@4 {
900					compatible = "fsl,qoriq-mc-dpmac";
901					reg = <0x4>;
902				};
903
904				dpmac5: dpmac@5 {
905					compatible = "fsl,qoriq-mc-dpmac";
906					reg = <0x5>;
907				};
908
909				dpmac6: dpmac@6 {
910					compatible = "fsl,qoriq-mc-dpmac";
911					reg = <0x6>;
912				};
913
914				dpmac7: dpmac@7 {
915					compatible = "fsl,qoriq-mc-dpmac";
916					reg = <0x7>;
917				};
918
919				dpmac8: dpmac@8 {
920					compatible = "fsl,qoriq-mc-dpmac";
921					reg = <0x8>;
922				};
923
924				dpmac9: dpmac@9 {
925					compatible = "fsl,qoriq-mc-dpmac";
926					reg = <0x9>;
927				};
928
929				dpmac10: dpmac@a {
930					compatible = "fsl,qoriq-mc-dpmac";
931					reg = <0xa>;
932				};
933
934				dpmac11: dpmac@b {
935					compatible = "fsl,qoriq-mc-dpmac";
936					reg = <0xb>;
937				};
938
939				dpmac12: dpmac@c {
940					compatible = "fsl,qoriq-mc-dpmac";
941					reg = <0xc>;
942				};
943
944				dpmac13: dpmac@d {
945					compatible = "fsl,qoriq-mc-dpmac";
946					reg = <0xd>;
947				};
948
949				dpmac14: dpmac@e {
950					compatible = "fsl,qoriq-mc-dpmac";
951					reg = <0xe>;
952				};
953
954				dpmac15: dpmac@f {
955					compatible = "fsl,qoriq-mc-dpmac";
956					reg = <0xf>;
957				};
958
959				dpmac16: dpmac@10 {
960					compatible = "fsl,qoriq-mc-dpmac";
961					reg = <0x10>;
962				};
963
964				dpmac17: dpmac@11 {
965					compatible = "fsl,qoriq-mc-dpmac";
966					reg = <0x11>;
967				};
968
969				dpmac18: dpmac@12 {
970					compatible = "fsl,qoriq-mc-dpmac";
971					reg = <0x12>;
972				};
973			};
974		};
975	};
976};
977