1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Device Tree Include file for Layerscape-LX2160A family SoC.
4//
5// Copyright 2018-2020 NXP
6
7#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/thermal/thermal.h>
11
12/memreserve/ 0x80000000 0x00010000;
13
14/ {
15	compatible = "fsl,lx2160a";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		rtc1 = &ftm_alarm0;
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		// 8 clusters having 2 Cortex-A72 cores each
29		cpu0: cpu@0 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a72";
32			enable-method = "psci";
33			reg = <0x0>;
34			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35			d-cache-size = <0x8000>;
36			d-cache-line-size = <64>;
37			d-cache-sets = <128>;
38			i-cache-size = <0xC000>;
39			i-cache-line-size = <64>;
40			i-cache-sets = <192>;
41			next-level-cache = <&cluster0_l2>;
42			cpu-idle-states = <&cpu_pw15>;
43			#cooling-cells = <2>;
44		};
45
46		cpu1: cpu@1 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a72";
49			enable-method = "psci";
50			reg = <0x1>;
51			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52			d-cache-size = <0x8000>;
53			d-cache-line-size = <64>;
54			d-cache-sets = <128>;
55			i-cache-size = <0xC000>;
56			i-cache-line-size = <64>;
57			i-cache-sets = <192>;
58			next-level-cache = <&cluster0_l2>;
59			cpu-idle-states = <&cpu_pw15>;
60			#cooling-cells = <2>;
61		};
62
63		cpu100: cpu@100 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a72";
66			enable-method = "psci";
67			reg = <0x100>;
68			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
69			d-cache-size = <0x8000>;
70			d-cache-line-size = <64>;
71			d-cache-sets = <128>;
72			i-cache-size = <0xC000>;
73			i-cache-line-size = <64>;
74			i-cache-sets = <192>;
75			next-level-cache = <&cluster1_l2>;
76			cpu-idle-states = <&cpu_pw15>;
77			#cooling-cells = <2>;
78		};
79
80		cpu101: cpu@101 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a72";
83			enable-method = "psci";
84			reg = <0x101>;
85			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
86			d-cache-size = <0x8000>;
87			d-cache-line-size = <64>;
88			d-cache-sets = <128>;
89			i-cache-size = <0xC000>;
90			i-cache-line-size = <64>;
91			i-cache-sets = <192>;
92			next-level-cache = <&cluster1_l2>;
93			cpu-idle-states = <&cpu_pw15>;
94			#cooling-cells = <2>;
95		};
96
97		cpu200: cpu@200 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a72";
100			enable-method = "psci";
101			reg = <0x200>;
102			clocks = <&clockgen QORIQ_CLK_CMUX 2>;
103			d-cache-size = <0x8000>;
104			d-cache-line-size = <64>;
105			d-cache-sets = <128>;
106			i-cache-size = <0xC000>;
107			i-cache-line-size = <64>;
108			i-cache-sets = <192>;
109			next-level-cache = <&cluster2_l2>;
110			cpu-idle-states = <&cpu_pw15>;
111			#cooling-cells = <2>;
112		};
113
114		cpu201: cpu@201 {
115			device_type = "cpu";
116			compatible = "arm,cortex-a72";
117			enable-method = "psci";
118			reg = <0x201>;
119			clocks = <&clockgen QORIQ_CLK_CMUX 2>;
120			d-cache-size = <0x8000>;
121			d-cache-line-size = <64>;
122			d-cache-sets = <128>;
123			i-cache-size = <0xC000>;
124			i-cache-line-size = <64>;
125			i-cache-sets = <192>;
126			next-level-cache = <&cluster2_l2>;
127			cpu-idle-states = <&cpu_pw15>;
128			#cooling-cells = <2>;
129		};
130
131		cpu300: cpu@300 {
132			device_type = "cpu";
133			compatible = "arm,cortex-a72";
134			enable-method = "psci";
135			reg = <0x300>;
136			clocks = <&clockgen QORIQ_CLK_CMUX 3>;
137			d-cache-size = <0x8000>;
138			d-cache-line-size = <64>;
139			d-cache-sets = <128>;
140			i-cache-size = <0xC000>;
141			i-cache-line-size = <64>;
142			i-cache-sets = <192>;
143			next-level-cache = <&cluster3_l2>;
144			cpu-idle-states = <&cpu_pw15>;
145			#cooling-cells = <2>;
146		};
147
148		cpu301: cpu@301 {
149			device_type = "cpu";
150			compatible = "arm,cortex-a72";
151			enable-method = "psci";
152			reg = <0x301>;
153			clocks = <&clockgen QORIQ_CLK_CMUX 3>;
154			d-cache-size = <0x8000>;
155			d-cache-line-size = <64>;
156			d-cache-sets = <128>;
157			i-cache-size = <0xC000>;
158			i-cache-line-size = <64>;
159			i-cache-sets = <192>;
160			next-level-cache = <&cluster3_l2>;
161			cpu-idle-states = <&cpu_pw15>;
162			#cooling-cells = <2>;
163		};
164
165		cpu400: cpu@400 {
166			device_type = "cpu";
167			compatible = "arm,cortex-a72";
168			enable-method = "psci";
169			reg = <0x400>;
170			clocks = <&clockgen QORIQ_CLK_CMUX 4>;
171			d-cache-size = <0x8000>;
172			d-cache-line-size = <64>;
173			d-cache-sets = <128>;
174			i-cache-size = <0xC000>;
175			i-cache-line-size = <64>;
176			i-cache-sets = <192>;
177			next-level-cache = <&cluster4_l2>;
178			cpu-idle-states = <&cpu_pw15>;
179			#cooling-cells = <2>;
180		};
181
182		cpu401: cpu@401 {
183			device_type = "cpu";
184			compatible = "arm,cortex-a72";
185			enable-method = "psci";
186			reg = <0x401>;
187			clocks = <&clockgen QORIQ_CLK_CMUX 4>;
188			d-cache-size = <0x8000>;
189			d-cache-line-size = <64>;
190			d-cache-sets = <128>;
191			i-cache-size = <0xC000>;
192			i-cache-line-size = <64>;
193			i-cache-sets = <192>;
194			next-level-cache = <&cluster4_l2>;
195			cpu-idle-states = <&cpu_pw15>;
196			#cooling-cells = <2>;
197		};
198
199		cpu500: cpu@500 {
200			device_type = "cpu";
201			compatible = "arm,cortex-a72";
202			enable-method = "psci";
203			reg = <0x500>;
204			clocks = <&clockgen QORIQ_CLK_CMUX 5>;
205			d-cache-size = <0x8000>;
206			d-cache-line-size = <64>;
207			d-cache-sets = <128>;
208			i-cache-size = <0xC000>;
209			i-cache-line-size = <64>;
210			i-cache-sets = <192>;
211			next-level-cache = <&cluster5_l2>;
212			cpu-idle-states = <&cpu_pw15>;
213			#cooling-cells = <2>;
214		};
215
216		cpu501: cpu@501 {
217			device_type = "cpu";
218			compatible = "arm,cortex-a72";
219			enable-method = "psci";
220			reg = <0x501>;
221			clocks = <&clockgen QORIQ_CLK_CMUX 5>;
222			d-cache-size = <0x8000>;
223			d-cache-line-size = <64>;
224			d-cache-sets = <128>;
225			i-cache-size = <0xC000>;
226			i-cache-line-size = <64>;
227			i-cache-sets = <192>;
228			next-level-cache = <&cluster5_l2>;
229			cpu-idle-states = <&cpu_pw15>;
230			#cooling-cells = <2>;
231		};
232
233		cpu600: cpu@600 {
234			device_type = "cpu";
235			compatible = "arm,cortex-a72";
236			enable-method = "psci";
237			reg = <0x600>;
238			clocks = <&clockgen QORIQ_CLK_CMUX 6>;
239			d-cache-size = <0x8000>;
240			d-cache-line-size = <64>;
241			d-cache-sets = <128>;
242			i-cache-size = <0xC000>;
243			i-cache-line-size = <64>;
244			i-cache-sets = <192>;
245			next-level-cache = <&cluster6_l2>;
246			cpu-idle-states = <&cpu_pw15>;
247			#cooling-cells = <2>;
248		};
249
250		cpu601: cpu@601 {
251			device_type = "cpu";
252			compatible = "arm,cortex-a72";
253			enable-method = "psci";
254			reg = <0x601>;
255			clocks = <&clockgen QORIQ_CLK_CMUX 6>;
256			d-cache-size = <0x8000>;
257			d-cache-line-size = <64>;
258			d-cache-sets = <128>;
259			i-cache-size = <0xC000>;
260			i-cache-line-size = <64>;
261			i-cache-sets = <192>;
262			next-level-cache = <&cluster6_l2>;
263			cpu-idle-states = <&cpu_pw15>;
264			#cooling-cells = <2>;
265		};
266
267		cpu700: cpu@700 {
268			device_type = "cpu";
269			compatible = "arm,cortex-a72";
270			enable-method = "psci";
271			reg = <0x700>;
272			clocks = <&clockgen QORIQ_CLK_CMUX 7>;
273			d-cache-size = <0x8000>;
274			d-cache-line-size = <64>;
275			d-cache-sets = <128>;
276			i-cache-size = <0xC000>;
277			i-cache-line-size = <64>;
278			i-cache-sets = <192>;
279			next-level-cache = <&cluster7_l2>;
280			cpu-idle-states = <&cpu_pw15>;
281			#cooling-cells = <2>;
282		};
283
284		cpu701: cpu@701 {
285			device_type = "cpu";
286			compatible = "arm,cortex-a72";
287			enable-method = "psci";
288			reg = <0x701>;
289			clocks = <&clockgen QORIQ_CLK_CMUX 7>;
290			d-cache-size = <0x8000>;
291			d-cache-line-size = <64>;
292			d-cache-sets = <128>;
293			i-cache-size = <0xC000>;
294			i-cache-line-size = <64>;
295			i-cache-sets = <192>;
296			next-level-cache = <&cluster7_l2>;
297			cpu-idle-states = <&cpu_pw15>;
298			#cooling-cells = <2>;
299		};
300
301		cluster0_l2: l2-cache0 {
302			compatible = "cache";
303			cache-size = <0x100000>;
304			cache-line-size = <64>;
305			cache-sets = <1024>;
306			cache-level = <2>;
307		};
308
309		cluster1_l2: l2-cache1 {
310			compatible = "cache";
311			cache-size = <0x100000>;
312			cache-line-size = <64>;
313			cache-sets = <1024>;
314			cache-level = <2>;
315		};
316
317		cluster2_l2: l2-cache2 {
318			compatible = "cache";
319			cache-size = <0x100000>;
320			cache-line-size = <64>;
321			cache-sets = <1024>;
322			cache-level = <2>;
323		};
324
325		cluster3_l2: l2-cache3 {
326			compatible = "cache";
327			cache-size = <0x100000>;
328			cache-line-size = <64>;
329			cache-sets = <1024>;
330			cache-level = <2>;
331		};
332
333		cluster4_l2: l2-cache4 {
334			compatible = "cache";
335			cache-size = <0x100000>;
336			cache-line-size = <64>;
337			cache-sets = <1024>;
338			cache-level = <2>;
339		};
340
341		cluster5_l2: l2-cache5 {
342			compatible = "cache";
343			cache-size = <0x100000>;
344			cache-line-size = <64>;
345			cache-sets = <1024>;
346			cache-level = <2>;
347		};
348
349		cluster6_l2: l2-cache6 {
350			compatible = "cache";
351			cache-size = <0x100000>;
352			cache-line-size = <64>;
353			cache-sets = <1024>;
354			cache-level = <2>;
355		};
356
357		cluster7_l2: l2-cache7 {
358			compatible = "cache";
359			cache-size = <0x100000>;
360			cache-line-size = <64>;
361			cache-sets = <1024>;
362			cache-level = <2>;
363		};
364
365		cpu_pw15: cpu-pw15 {
366			compatible = "arm,idle-state";
367			idle-state-name = "PW15";
368			arm,psci-suspend-param = <0x0>;
369			entry-latency-us = <2000>;
370			exit-latency-us = <2000>;
371			min-residency-us = <6000>;
372		  };
373	};
374
375	gic: interrupt-controller@6000000 {
376		compatible = "arm,gic-v3";
377		reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
378			<0x0 0x06200000 0 0x200000>, // GICR (RD_base +
379						     // SGI_base)
380			<0x0 0x0c0c0000 0 0x2000>, // GICC
381			<0x0 0x0c0d0000 0 0x1000>, // GICH
382			<0x0 0x0c0e0000 0 0x20000>; // GICV
383		#interrupt-cells = <3>;
384		#address-cells = <2>;
385		#size-cells = <2>;
386		ranges;
387		interrupt-controller;
388		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
389
390		its: gic-its@6020000 {
391			compatible = "arm,gic-v3-its";
392			msi-controller;
393			reg = <0x0 0x6020000 0 0x20000>;
394		};
395	};
396
397	timer {
398		compatible = "arm,armv8-timer";
399		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
400			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
401			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
402			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
403	};
404
405	pmu {
406		compatible = "arm,cortex-a72-pmu";
407		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
408	};
409
410	psci {
411		compatible = "arm,psci-0.2";
412		method = "smc";
413	};
414
415	memory@80000000 {
416		// DRAM space - 1, size : 2 GB DRAM
417		device_type = "memory";
418		reg = <0x00000000 0x80000000 0 0x80000000>;
419	};
420
421	ddr1: memory-controller@1080000 {
422		compatible = "fsl,qoriq-memory-controller";
423		reg = <0x0 0x1080000 0x0 0x1000>;
424		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
425		little-endian;
426	};
427
428	ddr2: memory-controller@1090000 {
429		compatible = "fsl,qoriq-memory-controller";
430		reg = <0x0 0x1090000 0x0 0x1000>;
431		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
432		little-endian;
433	};
434
435	// One clock unit-sysclk node which bootloader require during DT fix-up
436	sysclk: sysclk {
437		compatible = "fixed-clock";
438		#clock-cells = <0>;
439		clock-frequency = <100000000>; // fixed up by bootloader
440		clock-output-names = "sysclk";
441	};
442
443	thermal-zones {
444		cluster6-7 {
445			polling-delay-passive = <1000>;
446			polling-delay = <5000>;
447			thermal-sensors = <&tmu 0>;
448
449			trips {
450				cluster6_7_alert: cluster6-7-alert {
451					temperature = <85000>;
452					hysteresis = <2000>;
453					type = "passive";
454				};
455
456				cluster6_7_crit: cluster6-7-crit {
457					temperature = <95000>;
458					hysteresis = <2000>;
459					type = "critical";
460				};
461			};
462
463			cooling-maps {
464				map0 {
465					trip = <&cluster6_7_alert>;
466					cooling-device =
467						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
468						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
469						<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
470						<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
471						<&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
472						<&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
473						<&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
474						<&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
475						<&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
476						<&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
477						<&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
478						<&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
479						<&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
480						<&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
481						<&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
482						<&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
483				};
484			};
485		};
486
487		ddr-cluster5 {
488			polling-delay-passive = <1000>;
489			polling-delay = <5000>;
490			thermal-sensors = <&tmu 1>;
491
492			trips {
493				ddr-cluster5-alert {
494					temperature = <85000>;
495					hysteresis = <2000>;
496					type = "passive";
497				};
498
499				ddr-cluster5-crit {
500					temperature = <95000>;
501					hysteresis = <2000>;
502					type = "critical";
503				};
504			};
505		};
506
507		wriop {
508			polling-delay-passive = <1000>;
509			polling-delay = <5000>;
510			thermal-sensors = <&tmu 2>;
511
512			trips {
513				wriop-alert {
514					temperature = <85000>;
515					hysteresis = <2000>;
516					type = "passive";
517				};
518
519				wriop-crit {
520					temperature = <95000>;
521					hysteresis = <2000>;
522					type = "critical";
523				};
524			};
525		};
526
527		dce-qbman-hsio2 {
528			polling-delay-passive = <1000>;
529			polling-delay = <5000>;
530			thermal-sensors = <&tmu 3>;
531
532			trips {
533				dce-qbman-alert {
534					temperature = <85000>;
535					hysteresis = <2000>;
536					type = "passive";
537				};
538
539				dce-qbman-crit {
540					temperature = <95000>;
541					hysteresis = <2000>;
542					type = "critical";
543				};
544			};
545		};
546
547		ccn-dpaa-tbu {
548			polling-delay-passive = <1000>;
549			polling-delay = <5000>;
550			thermal-sensors = <&tmu 4>;
551
552			trips {
553				ccn-dpaa-alert {
554					temperature = <85000>;
555					hysteresis = <2000>;
556					type = "passive";
557				};
558
559				ccn-dpaa-crit {
560					temperature = <95000>;
561					hysteresis = <2000>;
562					type = "critical";
563				};
564			};
565		};
566
567		cluster4-hsio3 {
568			polling-delay-passive = <1000>;
569			polling-delay = <5000>;
570			thermal-sensors = <&tmu 5>;
571
572			trips {
573				clust4-hsio3-alert {
574					temperature = <85000>;
575					hysteresis = <2000>;
576					type = "passive";
577				};
578
579				clust4-hsio3-crit {
580					temperature = <95000>;
581					hysteresis = <2000>;
582					type = "critical";
583				};
584			};
585		};
586
587		cluster2-3 {
588			polling-delay-passive = <1000>;
589			polling-delay = <5000>;
590			thermal-sensors = <&tmu 6>;
591
592			trips {
593				cluster2-3-alert {
594					temperature = <85000>;
595					hysteresis = <2000>;
596					type = "passive";
597				};
598
599				cluster2-3-crit {
600					temperature = <95000>;
601					hysteresis = <2000>;
602					type = "critical";
603				};
604			};
605		};
606	};
607
608	soc {
609		compatible = "simple-bus";
610		#address-cells = <2>;
611		#size-cells = <2>;
612		ranges;
613		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
614
615		serdes_1: phy@1ea0000 {
616			compatible = "fsl,lynx-28g";
617			reg = <0x0 0x1ea0000 0x0 0x1e30>;
618			#phy-cells = <1>;
619		};
620
621		crypto: crypto@8000000 {
622			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
623			fsl,sec-era = <10>;
624			#address-cells = <1>;
625			#size-cells = <1>;
626			ranges = <0x0 0x00 0x8000000 0x100000>;
627			reg = <0x00 0x8000000 0x0 0x100000>;
628			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
629			dma-coherent;
630			status = "disabled";
631
632			sec_jr0: jr@10000 {
633				compatible = "fsl,sec-v5.0-job-ring",
634					     "fsl,sec-v4.0-job-ring";
635				reg = <0x10000 0x10000>;
636				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
637			};
638
639			sec_jr1: jr@20000 {
640				compatible = "fsl,sec-v5.0-job-ring",
641					     "fsl,sec-v4.0-job-ring";
642				reg = <0x20000 0x10000>;
643				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
644			};
645
646			sec_jr2: jr@30000 {
647				compatible = "fsl,sec-v5.0-job-ring",
648					     "fsl,sec-v4.0-job-ring";
649				reg = <0x30000 0x10000>;
650				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
651			};
652
653			sec_jr3: jr@40000 {
654				compatible = "fsl,sec-v5.0-job-ring",
655					     "fsl,sec-v4.0-job-ring";
656				reg = <0x40000 0x10000>;
657				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
658			};
659		};
660
661		clockgen: clock-controller@1300000 {
662			compatible = "fsl,lx2160a-clockgen";
663			reg = <0 0x1300000 0 0xa0000>;
664			#clock-cells = <2>;
665			clocks = <&sysclk>;
666		};
667
668		dcfg: syscon@1e00000 {
669			compatible = "fsl,lx2160a-dcfg", "syscon";
670			reg = <0x0 0x1e00000 0x0 0x10000>;
671			little-endian;
672		};
673
674		sfp: efuse@1e80000 {
675			compatible = "fsl,ls1028a-sfp";
676			reg = <0x0 0x1e80000 0x0 0x10000>;
677			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
678					    QORIQ_CLK_PLL_DIV(4)>;
679			clock-names = "sfp";
680		};
681
682		isc: syscon@1f70000 {
683			compatible = "fsl,lx2160a-isc", "syscon";
684			reg = <0x0 0x1f70000 0x0 0x10000>;
685			little-endian;
686			#address-cells = <1>;
687			#size-cells = <1>;
688			ranges = <0x0 0x0 0x1f70000 0x10000>;
689
690			extirq: interrupt-controller@14 {
691				compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
692				#interrupt-cells = <2>;
693				#address-cells = <0>;
694				interrupt-controller;
695				reg = <0x14 4>;
696				interrupt-map =
697					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
698					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
699					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
700					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
701					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
702					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
703					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
704					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
705					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
706					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
707					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
708					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
709				interrupt-map-mask = <0xf 0x0>;
710			};
711		};
712
713		tmu: tmu@1f80000 {
714			compatible = "fsl,qoriq-tmu";
715			reg = <0x0 0x1f80000 0x0 0x10000>;
716			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
717			fsl,tmu-range = <0x800000e6 0x8001017d>;
718			fsl,tmu-calibration =
719				/* Calibration data group 1 */
720				<0x00000000 0x00000035
721				/* Calibration data group 2 */
722				0x00000001 0x00000154>;
723			little-endian;
724			#thermal-sensor-cells = <1>;
725		};
726
727		i2c0: i2c@2000000 {
728			compatible = "fsl,vf610-i2c";
729			#address-cells = <1>;
730			#size-cells = <0>;
731			reg = <0x0 0x2000000 0x0 0x10000>;
732			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
733			clock-names = "i2c";
734			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
735					    QORIQ_CLK_PLL_DIV(16)>;
736			scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
737			status = "disabled";
738		};
739
740		i2c1: i2c@2010000 {
741			compatible = "fsl,vf610-i2c";
742			#address-cells = <1>;
743			#size-cells = <0>;
744			reg = <0x0 0x2010000 0x0 0x10000>;
745			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
746			clock-names = "i2c";
747			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
748					    QORIQ_CLK_PLL_DIV(16)>;
749			status = "disabled";
750		};
751
752		i2c2: i2c@2020000 {
753			compatible = "fsl,vf610-i2c";
754			#address-cells = <1>;
755			#size-cells = <0>;
756			reg = <0x0 0x2020000 0x0 0x10000>;
757			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
758			clock-names = "i2c";
759			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
760					    QORIQ_CLK_PLL_DIV(16)>;
761			status = "disabled";
762		};
763
764		i2c3: i2c@2030000 {
765			compatible = "fsl,vf610-i2c";
766			#address-cells = <1>;
767			#size-cells = <0>;
768			reg = <0x0 0x2030000 0x0 0x10000>;
769			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
770			clock-names = "i2c";
771			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
772					    QORIQ_CLK_PLL_DIV(16)>;
773			status = "disabled";
774		};
775
776		i2c4: i2c@2040000 {
777			compatible = "fsl,vf610-i2c";
778			#address-cells = <1>;
779			#size-cells = <0>;
780			reg = <0x0 0x2040000 0x0 0x10000>;
781			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
782			clock-names = "i2c";
783			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
784					    QORIQ_CLK_PLL_DIV(16)>;
785			scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
786			status = "disabled";
787		};
788
789		i2c5: i2c@2050000 {
790			compatible = "fsl,vf610-i2c";
791			#address-cells = <1>;
792			#size-cells = <0>;
793			reg = <0x0 0x2050000 0x0 0x10000>;
794			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
795			clock-names = "i2c";
796			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
797					    QORIQ_CLK_PLL_DIV(16)>;
798			status = "disabled";
799		};
800
801		i2c6: i2c@2060000 {
802			compatible = "fsl,vf610-i2c";
803			#address-cells = <1>;
804			#size-cells = <0>;
805			reg = <0x0 0x2060000 0x0 0x10000>;
806			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
807			clock-names = "i2c";
808			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
809					    QORIQ_CLK_PLL_DIV(16)>;
810			status = "disabled";
811		};
812
813		i2c7: i2c@2070000 {
814			compatible = "fsl,vf610-i2c";
815			#address-cells = <1>;
816			#size-cells = <0>;
817			reg = <0x0 0x2070000 0x0 0x10000>;
818			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
819			clock-names = "i2c";
820			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
821					    QORIQ_CLK_PLL_DIV(16)>;
822			status = "disabled";
823		};
824
825		fspi: spi@20c0000 {
826			compatible = "nxp,lx2160a-fspi";
827			#address-cells = <1>;
828			#size-cells = <0>;
829			reg = <0x0 0x20c0000 0x0 0x10000>,
830			      <0x0 0x20000000 0x0 0x10000000>;
831			reg-names = "fspi_base", "fspi_mmap";
832			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
833			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
834					    QORIQ_CLK_PLL_DIV(4)>,
835				 <&clockgen QORIQ_CLK_PLATFORM_PLL
836					    QORIQ_CLK_PLL_DIV(4)>;
837			clock-names = "fspi_en", "fspi";
838			status = "disabled";
839		};
840
841		dspi0: spi@2100000 {
842			compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
843			#address-cells = <1>;
844			#size-cells = <0>;
845			reg = <0x0 0x2100000 0x0 0x10000>;
846			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
847			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
848					    QORIQ_CLK_PLL_DIV(8)>;
849			clock-names = "dspi";
850			spi-num-chipselects = <5>;
851			bus-num = <0>;
852			status = "disabled";
853		};
854
855		dspi1: spi@2110000 {
856			compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
857			#address-cells = <1>;
858			#size-cells = <0>;
859			reg = <0x0 0x2110000 0x0 0x10000>;
860			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
861			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
862					    QORIQ_CLK_PLL_DIV(8)>;
863			clock-names = "dspi";
864			spi-num-chipselects = <5>;
865			bus-num = <1>;
866			status = "disabled";
867		};
868
869		dspi2: spi@2120000 {
870			compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
871			#address-cells = <1>;
872			#size-cells = <0>;
873			reg = <0x0 0x2120000 0x0 0x10000>;
874			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
875			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
876					    QORIQ_CLK_PLL_DIV(8)>;
877			clock-names = "dspi";
878			spi-num-chipselects = <5>;
879			bus-num = <2>;
880			status = "disabled";
881		};
882
883		esdhc0: esdhc@2140000 {
884			compatible = "fsl,esdhc";
885			reg = <0x0 0x2140000 0x0 0x10000>;
886			interrupts = <0 28 0x4>; /* Level high type */
887			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
888					    QORIQ_CLK_PLL_DIV(2)>;
889			dma-coherent;
890			voltage-ranges = <1800 1800 3300 3300>;
891			sdhci,auto-cmd12;
892			little-endian;
893			bus-width = <4>;
894			status = "disabled";
895		};
896
897		esdhc1: esdhc@2150000 {
898			compatible = "fsl,esdhc";
899			reg = <0x0 0x2150000 0x0 0x10000>;
900			interrupts = <0 63 0x4>; /* Level high type */
901			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
902					    QORIQ_CLK_PLL_DIV(2)>;
903			dma-coherent;
904			voltage-ranges = <1800 1800 3300 3300>;
905			sdhci,auto-cmd12;
906			broken-cd;
907			little-endian;
908			bus-width = <4>;
909			status = "disabled";
910		};
911
912		can0: can@2180000 {
913			compatible = "fsl,lx2160ar1-flexcan";
914			reg = <0x0 0x2180000 0x0 0x10000>;
915			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
916			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
917					    QORIQ_CLK_PLL_DIV(8)>,
918				 <&clockgen QORIQ_CLK_SYSCLK 0>;
919			clock-names = "ipg", "per";
920			fsl,clk-source = /bits/ 8 <0>;
921			status = "disabled";
922		};
923
924		can1: can@2190000 {
925			compatible = "fsl,lx2160ar1-flexcan";
926			reg = <0x0 0x2190000 0x0 0x10000>;
927			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
928			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
929					    QORIQ_CLK_PLL_DIV(8)>,
930				 <&clockgen QORIQ_CLK_SYSCLK 0>;
931			clock-names = "ipg", "per";
932			fsl,clk-source = /bits/ 8 <0>;
933			status = "disabled";
934		};
935
936		uart0: serial@21c0000 {
937			compatible = "arm,sbsa-uart","arm,pl011";
938			reg = <0x0 0x21c0000 0x0 0x1000>;
939			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
940			current-speed = <115200>;
941			status = "disabled";
942		};
943
944		uart1: serial@21d0000 {
945			compatible = "arm,sbsa-uart","arm,pl011";
946			reg = <0x0 0x21d0000 0x0 0x1000>;
947			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
948			current-speed = <115200>;
949			status = "disabled";
950		};
951
952		uart2: serial@21e0000 {
953			compatible = "arm,sbsa-uart","arm,pl011";
954			reg = <0x0 0x21e0000 0x0 0x1000>;
955			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
956			current-speed = <115200>;
957			status = "disabled";
958		};
959
960		uart3: serial@21f0000 {
961			compatible = "arm,sbsa-uart","arm,pl011";
962			reg = <0x0 0x21f0000 0x0 0x1000>;
963			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
964			current-speed = <115200>;
965			status = "disabled";
966		};
967
968		gpio0: gpio@2300000 {
969			compatible = "fsl,qoriq-gpio";
970			reg = <0x0 0x2300000 0x0 0x10000>;
971			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
972			gpio-controller;
973			little-endian;
974			#gpio-cells = <2>;
975			interrupt-controller;
976			#interrupt-cells = <2>;
977		};
978
979		gpio1: gpio@2310000 {
980			compatible = "fsl,qoriq-gpio";
981			reg = <0x0 0x2310000 0x0 0x10000>;
982			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
983			gpio-controller;
984			little-endian;
985			#gpio-cells = <2>;
986			interrupt-controller;
987			#interrupt-cells = <2>;
988		};
989
990		gpio2: gpio@2320000 {
991			compatible = "fsl,qoriq-gpio";
992			reg = <0x0 0x2320000 0x0 0x10000>;
993			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
994			gpio-controller;
995			little-endian;
996			#gpio-cells = <2>;
997			interrupt-controller;
998			#interrupt-cells = <2>;
999		};
1000
1001		gpio3: gpio@2330000 {
1002			compatible = "fsl,qoriq-gpio";
1003			reg = <0x0 0x2330000 0x0 0x10000>;
1004			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1005			gpio-controller;
1006			little-endian;
1007			#gpio-cells = <2>;
1008			interrupt-controller;
1009			#interrupt-cells = <2>;
1010		};
1011
1012		watchdog@23a0000 {
1013			compatible = "arm,sbsa-gwdt";
1014			reg = <0x0 0x23a0000 0 0x1000>,
1015			      <0x0 0x2390000 0 0x1000>;
1016			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1017			timeout-sec = <30>;
1018		};
1019
1020		rcpm: power-controller@1e34040 {
1021			compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1022			reg = <0x0 0x1e34040 0x0 0x1c>;
1023			#fsl,rcpm-wakeup-cells = <7>;
1024			little-endian;
1025		};
1026
1027		ftm_alarm0: timer@2800000 {
1028			compatible = "fsl,lx2160a-ftm-alarm";
1029			reg = <0x0 0x2800000 0x0 0x10000>;
1030			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1031			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1032		};
1033
1034		usb0: usb@3100000 {
1035			compatible = "snps,dwc3";
1036			reg = <0x0 0x3100000 0x0 0x10000>;
1037			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1038			dr_mode = "host";
1039			snps,quirk-frame-length-adjustment = <0x20>;
1040			usb3-lpm-capable;
1041			snps,dis_rxdet_inp3_quirk;
1042			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1043			status = "disabled";
1044		};
1045
1046		usb1: usb@3110000 {
1047			compatible = "snps,dwc3";
1048			reg = <0x0 0x3110000 0x0 0x10000>;
1049			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1050			dr_mode = "host";
1051			snps,quirk-frame-length-adjustment = <0x20>;
1052			usb3-lpm-capable;
1053			snps,dis_rxdet_inp3_quirk;
1054			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1055			status = "disabled";
1056		};
1057
1058		sata0: sata@3200000 {
1059			compatible = "fsl,lx2160a-ahci";
1060			reg = <0x0 0x3200000 0x0 0x10000>,
1061			      <0x7 0x100520 0x0 0x4>;
1062			reg-names = "ahci", "sata-ecc";
1063			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1064			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1065					    QORIQ_CLK_PLL_DIV(4)>;
1066			dma-coherent;
1067			status = "disabled";
1068		};
1069
1070		sata1: sata@3210000 {
1071			compatible = "fsl,lx2160a-ahci";
1072			reg = <0x0 0x3210000 0x0 0x10000>,
1073			      <0x7 0x100520 0x0 0x4>;
1074			reg-names = "ahci", "sata-ecc";
1075			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1076			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1077					    QORIQ_CLK_PLL_DIV(4)>;
1078			dma-coherent;
1079			status = "disabled";
1080		};
1081
1082		sata2: sata@3220000 {
1083			compatible = "fsl,lx2160a-ahci";
1084			reg = <0x0 0x3220000 0x0 0x10000>,
1085			      <0x7 0x100520 0x0 0x4>;
1086			reg-names = "ahci", "sata-ecc";
1087			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1088			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1089					    QORIQ_CLK_PLL_DIV(4)>;
1090			dma-coherent;
1091			status = "disabled";
1092		};
1093
1094		sata3: sata@3230000 {
1095			compatible = "fsl,lx2160a-ahci";
1096			reg = <0x0 0x3230000 0x0 0x10000>,
1097			      <0x7 0x100520 0x0 0x4>;
1098			reg-names = "ahci", "sata-ecc";
1099			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1100			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1101					    QORIQ_CLK_PLL_DIV(4)>;
1102			dma-coherent;
1103			status = "disabled";
1104		};
1105
1106		pcie1: pcie@3400000 {
1107			compatible = "fsl,lx2160a-pcie";
1108			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
1109			      <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1110			reg-names = "csr_axi_slave", "config_axi_slave";
1111			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1112				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1113				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1114			interrupt-names = "aer", "pme", "intr";
1115			#address-cells = <3>;
1116			#size-cells = <2>;
1117			device_type = "pci";
1118			dma-coherent;
1119			apio-wins = <8>;
1120			ppio-wins = <8>;
1121			bus-range = <0x0 0xff>;
1122			ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1123			msi-parent = <&its>;
1124			#interrupt-cells = <1>;
1125			interrupt-map-mask = <0 0 0 7>;
1126			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1127					<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1128					<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1129					<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1130			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1131			status = "disabled";
1132		};
1133
1134		pcie2: pcie@3500000 {
1135			compatible = "fsl,lx2160a-pcie";
1136			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
1137			      <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1138			reg-names = "csr_axi_slave", "config_axi_slave";
1139			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1140				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1141				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1142			interrupt-names = "aer", "pme", "intr";
1143			#address-cells = <3>;
1144			#size-cells = <2>;
1145			device_type = "pci";
1146			dma-coherent;
1147			apio-wins = <8>;
1148			ppio-wins = <8>;
1149			bus-range = <0x0 0xff>;
1150			ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1151			msi-parent = <&its>;
1152			#interrupt-cells = <1>;
1153			interrupt-map-mask = <0 0 0 7>;
1154			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1155					<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1156					<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1157					<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1158			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1159			status = "disabled";
1160		};
1161
1162		pcie3: pcie@3600000 {
1163			compatible = "fsl,lx2160a-pcie";
1164			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
1165			      <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1166			reg-names = "csr_axi_slave", "config_axi_slave";
1167			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1168				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1169				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1170			interrupt-names = "aer", "pme", "intr";
1171			#address-cells = <3>;
1172			#size-cells = <2>;
1173			device_type = "pci";
1174			dma-coherent;
1175			apio-wins = <256>;
1176			ppio-wins = <24>;
1177			bus-range = <0x0 0xff>;
1178			ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1179			msi-parent = <&its>;
1180			#interrupt-cells = <1>;
1181			interrupt-map-mask = <0 0 0 7>;
1182			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1183					<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1184					<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1185					<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1186			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1187			status = "disabled";
1188		};
1189
1190		pcie4: pcie@3700000 {
1191			compatible = "fsl,lx2160a-pcie";
1192			reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
1193			      <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1194			reg-names = "csr_axi_slave", "config_axi_slave";
1195			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1196				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1197				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1198			interrupt-names = "aer", "pme", "intr";
1199			#address-cells = <3>;
1200			#size-cells = <2>;
1201			device_type = "pci";
1202			dma-coherent;
1203			apio-wins = <8>;
1204			ppio-wins = <8>;
1205			bus-range = <0x0 0xff>;
1206			ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1207			msi-parent = <&its>;
1208			#interrupt-cells = <1>;
1209			interrupt-map-mask = <0 0 0 7>;
1210			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1211					<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1212					<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1213					<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1214			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1215			status = "disabled";
1216		};
1217
1218		pcie5: pcie@3800000 {
1219			compatible = "fsl,lx2160a-pcie";
1220			reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
1221			      <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1222			reg-names = "csr_axi_slave", "config_axi_slave";
1223			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1224				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1225				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1226			interrupt-names = "aer", "pme", "intr";
1227			#address-cells = <3>;
1228			#size-cells = <2>;
1229			device_type = "pci";
1230			dma-coherent;
1231			apio-wins = <256>;
1232			ppio-wins = <24>;
1233			bus-range = <0x0 0xff>;
1234			ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1235			msi-parent = <&its>;
1236			#interrupt-cells = <1>;
1237			interrupt-map-mask = <0 0 0 7>;
1238			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1239					<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1240					<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1241					<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1242			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1243			status = "disabled";
1244		};
1245
1246		pcie6: pcie@3900000 {
1247			compatible = "fsl,lx2160a-pcie";
1248			reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
1249			      <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1250			reg-names = "csr_axi_slave", "config_axi_slave";
1251			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1252				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1253				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1254			interrupt-names = "aer", "pme", "intr";
1255			#address-cells = <3>;
1256			#size-cells = <2>;
1257			device_type = "pci";
1258			dma-coherent;
1259			apio-wins = <8>;
1260			ppio-wins = <8>;
1261			bus-range = <0x0 0xff>;
1262			ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1263			msi-parent = <&its>;
1264			#interrupt-cells = <1>;
1265			interrupt-map-mask = <0 0 0 7>;
1266			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1267					<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1268					<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1269					<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1270			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1271			status = "disabled";
1272		};
1273
1274		smmu: iommu@5000000 {
1275			compatible = "arm,mmu-500";
1276			reg = <0 0x5000000 0 0x800000>;
1277			#iommu-cells = <1>;
1278			#global-interrupts = <14>;
1279				     // global secure fault
1280			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1281				     // combined secure
1282				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1283				     // global non-secure fault
1284				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1285				     // combined non-secure
1286				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1287				     // performance counter interrupts 0-9
1288				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1289				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1290				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1291				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1292				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1293				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1294				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1295				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1296				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1297				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1298				     // per context interrupt, 64 interrupts
1299				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1300				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1301				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1302				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1303				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1304				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1305				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1306				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1307				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1308				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1309				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1310				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1311				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1312				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1313				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1314				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1315				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1316				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1317				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1318				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1319				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1320				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1321				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1322				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1323				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1324				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1325				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1326				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1327				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1328				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1329				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1330				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1331				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1332				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1333				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1334				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1335				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1336				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1337				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1338				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1339				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1340				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1341				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1342				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1343				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1344				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1345				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1346				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1347				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1348				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1349				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1350				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1351				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1352				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1353				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1354				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1355				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1356				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1357				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1358				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1359				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1360				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1361				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1362				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1363			dma-coherent;
1364		};
1365
1366		console@8340020 {
1367			compatible = "fsl,dpaa2-console";
1368			reg = <0x00000000 0x08340020 0 0x2>;
1369		};
1370
1371		ptp-timer@8b95000 {
1372			compatible = "fsl,dpaa2-ptp";
1373			reg = <0x0 0x8b95000 0x0 0x100>;
1374			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1375					    QORIQ_CLK_PLL_DIV(2)>;
1376			little-endian;
1377			fsl,extts-fifo;
1378		};
1379
1380		/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1381		emdio1: mdio@8b96000 {
1382			compatible = "fsl,fman-memac-mdio";
1383			reg = <0x0 0x8b96000 0x0 0x1000>;
1384			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1385			#address-cells = <1>;
1386			#size-cells = <0>;
1387			little-endian;
1388			clock-frequency = <2500000>;
1389			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1390					    QORIQ_CLK_PLL_DIV(2)>;
1391			status = "disabled";
1392		};
1393
1394		emdio2: mdio@8b97000 {
1395			compatible = "fsl,fman-memac-mdio";
1396			reg = <0x0 0x8b97000 0x0 0x1000>;
1397			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1398			little-endian;
1399			#address-cells = <1>;
1400			#size-cells = <0>;
1401			clock-frequency = <2500000>;
1402			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1403					    QORIQ_CLK_PLL_DIV(2)>;
1404			status = "disabled";
1405		};
1406
1407		pcs_mdio1: mdio@8c07000 {
1408			compatible = "fsl,fman-memac-mdio";
1409			reg = <0x0 0x8c07000 0x0 0x1000>;
1410			little-endian;
1411			#address-cells = <1>;
1412			#size-cells = <0>;
1413			status = "disabled";
1414
1415			pcs1: ethernet-phy@0 {
1416				reg = <0>;
1417			};
1418		};
1419
1420		pcs_mdio2: mdio@8c0b000 {
1421			compatible = "fsl,fman-memac-mdio";
1422			reg = <0x0 0x8c0b000 0x0 0x1000>;
1423			little-endian;
1424			#address-cells = <1>;
1425			#size-cells = <0>;
1426			status = "disabled";
1427
1428			pcs2: ethernet-phy@0 {
1429				reg = <0>;
1430			};
1431		};
1432
1433		pcs_mdio3: mdio@8c0f000 {
1434			compatible = "fsl,fman-memac-mdio";
1435			reg = <0x0 0x8c0f000 0x0 0x1000>;
1436			little-endian;
1437			#address-cells = <1>;
1438			#size-cells = <0>;
1439			status = "disabled";
1440
1441			pcs3: ethernet-phy@0 {
1442				reg = <0>;
1443			};
1444		};
1445
1446		pcs_mdio4: mdio@8c13000 {
1447			compatible = "fsl,fman-memac-mdio";
1448			reg = <0x0 0x8c13000 0x0 0x1000>;
1449			little-endian;
1450			#address-cells = <1>;
1451			#size-cells = <0>;
1452			status = "disabled";
1453
1454			pcs4: ethernet-phy@0 {
1455				reg = <0>;
1456			};
1457		};
1458
1459		pcs_mdio5: mdio@8c17000 {
1460			compatible = "fsl,fman-memac-mdio";
1461			reg = <0x0 0x8c17000 0x0 0x1000>;
1462			little-endian;
1463			#address-cells = <1>;
1464			#size-cells = <0>;
1465			status = "disabled";
1466
1467			pcs5: ethernet-phy@0 {
1468				reg = <0>;
1469			};
1470		};
1471
1472		pcs_mdio6: mdio@8c1b000 {
1473			compatible = "fsl,fman-memac-mdio";
1474			reg = <0x0 0x8c1b000 0x0 0x1000>;
1475			little-endian;
1476			#address-cells = <1>;
1477			#size-cells = <0>;
1478			status = "disabled";
1479
1480			pcs6: ethernet-phy@0 {
1481				reg = <0>;
1482			};
1483		};
1484
1485		pcs_mdio7: mdio@8c1f000 {
1486			compatible = "fsl,fman-memac-mdio";
1487			reg = <0x0 0x8c1f000 0x0 0x1000>;
1488			little-endian;
1489			#address-cells = <1>;
1490			#size-cells = <0>;
1491			status = "disabled";
1492
1493			pcs7: ethernet-phy@0 {
1494				reg = <0>;
1495			};
1496		};
1497
1498		pcs_mdio8: mdio@8c23000 {
1499			compatible = "fsl,fman-memac-mdio";
1500			reg = <0x0 0x8c23000 0x0 0x1000>;
1501			little-endian;
1502			#address-cells = <1>;
1503			#size-cells = <0>;
1504			status = "disabled";
1505
1506			pcs8: ethernet-phy@0 {
1507				reg = <0>;
1508			};
1509		};
1510
1511		pcs_mdio9: mdio@8c27000 {
1512			compatible = "fsl,fman-memac-mdio";
1513			reg = <0x0 0x8c27000 0x0 0x1000>;
1514			little-endian;
1515			#address-cells = <1>;
1516			#size-cells = <0>;
1517			status = "disabled";
1518
1519			pcs9: ethernet-phy@0 {
1520				reg = <0>;
1521			};
1522		};
1523
1524		pcs_mdio10: mdio@8c2b000 {
1525			compatible = "fsl,fman-memac-mdio";
1526			reg = <0x0 0x8c2b000 0x0 0x1000>;
1527			little-endian;
1528			#address-cells = <1>;
1529			#size-cells = <0>;
1530			status = "disabled";
1531
1532			pcs10: ethernet-phy@0 {
1533				reg = <0>;
1534			};
1535		};
1536
1537		pcs_mdio11: mdio@8c2f000 {
1538			compatible = "fsl,fman-memac-mdio";
1539			reg = <0x0 0x8c2f000 0x0 0x1000>;
1540			little-endian;
1541			#address-cells = <1>;
1542			#size-cells = <0>;
1543			status = "disabled";
1544
1545			pcs11: ethernet-phy@0 {
1546				reg = <0>;
1547			};
1548		};
1549
1550		pcs_mdio12: mdio@8c33000 {
1551			compatible = "fsl,fman-memac-mdio";
1552			reg = <0x0 0x8c33000 0x0 0x1000>;
1553			little-endian;
1554			#address-cells = <1>;
1555			#size-cells = <0>;
1556			status = "disabled";
1557
1558			pcs12: ethernet-phy@0 {
1559				reg = <0>;
1560			};
1561		};
1562
1563		pcs_mdio13: mdio@8c37000 {
1564			compatible = "fsl,fman-memac-mdio";
1565			reg = <0x0 0x8c37000 0x0 0x1000>;
1566			little-endian;
1567			#address-cells = <1>;
1568			#size-cells = <0>;
1569			status = "disabled";
1570
1571			pcs13: ethernet-phy@0 {
1572				reg = <0>;
1573			};
1574		};
1575
1576		pcs_mdio14: mdio@8c3b000 {
1577			compatible = "fsl,fman-memac-mdio";
1578			reg = <0x0 0x8c3b000 0x0 0x1000>;
1579			little-endian;
1580			#address-cells = <1>;
1581			#size-cells = <0>;
1582			status = "disabled";
1583
1584			pcs14: ethernet-phy@0 {
1585				reg = <0>;
1586			};
1587		};
1588
1589		pcs_mdio15: mdio@8c3f000 {
1590			compatible = "fsl,fman-memac-mdio";
1591			reg = <0x0 0x8c3f000 0x0 0x1000>;
1592			little-endian;
1593			#address-cells = <1>;
1594			#size-cells = <0>;
1595			status = "disabled";
1596
1597			pcs15: ethernet-phy@0 {
1598				reg = <0>;
1599			};
1600		};
1601
1602		pcs_mdio16: mdio@8c43000 {
1603			compatible = "fsl,fman-memac-mdio";
1604			reg = <0x0 0x8c43000 0x0 0x1000>;
1605			little-endian;
1606			#address-cells = <1>;
1607			#size-cells = <0>;
1608			status = "disabled";
1609
1610			pcs16: ethernet-phy@0 {
1611				reg = <0>;
1612			};
1613		};
1614
1615		pcs_mdio17: mdio@8c47000 {
1616			compatible = "fsl,fman-memac-mdio";
1617			reg = <0x0 0x8c47000 0x0 0x1000>;
1618			little-endian;
1619			#address-cells = <1>;
1620			#size-cells = <0>;
1621			status = "disabled";
1622
1623			pcs17: ethernet-phy@0 {
1624				reg = <0>;
1625			};
1626		};
1627
1628		pcs_mdio18: mdio@8c4b000 {
1629			compatible = "fsl,fman-memac-mdio";
1630			reg = <0x0 0x8c4b000 0x0 0x1000>;
1631			little-endian;
1632			#address-cells = <1>;
1633			#size-cells = <0>;
1634			status = "disabled";
1635
1636			pcs18: ethernet-phy@0 {
1637				reg = <0>;
1638			};
1639		};
1640
1641		fsl_mc: fsl-mc@80c000000 {
1642			compatible = "fsl,qoriq-mc";
1643			reg = <0x00000008 0x0c000000 0 0x40>,
1644			      <0x00000000 0x08340000 0 0x40000>;
1645			msi-parent = <&its>;
1646			/* iommu-map property is fixed up by u-boot */
1647			iommu-map = <0 &smmu 0 0>;
1648			dma-coherent;
1649			#address-cells = <3>;
1650			#size-cells = <1>;
1651
1652			/*
1653			 * Region type 0x0 - MC portals
1654			 * Region type 0x1 - QBMAN portals
1655			 */
1656			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1657				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1658
1659			/*
1660			 * Define the maximum number of MACs present on the SoC.
1661			 */
1662			dpmacs {
1663				#address-cells = <1>;
1664				#size-cells = <0>;
1665
1666				dpmac1: ethernet@1 {
1667					compatible = "fsl,qoriq-mc-dpmac";
1668					reg = <0x1>;
1669					pcs-handle = <&pcs1>;
1670				};
1671
1672				dpmac2: ethernet@2 {
1673					compatible = "fsl,qoriq-mc-dpmac";
1674					reg = <0x2>;
1675					pcs-handle = <&pcs2>;
1676				};
1677
1678				dpmac3: ethernet@3 {
1679					compatible = "fsl,qoriq-mc-dpmac";
1680					reg = <0x3>;
1681					pcs-handle = <&pcs3>;
1682				};
1683
1684				dpmac4: ethernet@4 {
1685					compatible = "fsl,qoriq-mc-dpmac";
1686					reg = <0x4>;
1687					pcs-handle = <&pcs4>;
1688				};
1689
1690				dpmac5: ethernet@5 {
1691					compatible = "fsl,qoriq-mc-dpmac";
1692					reg = <0x5>;
1693					pcs-handle = <&pcs5>;
1694				};
1695
1696				dpmac6: ethernet@6 {
1697					compatible = "fsl,qoriq-mc-dpmac";
1698					reg = <0x6>;
1699					pcs-handle = <&pcs6>;
1700				};
1701
1702				dpmac7: ethernet@7 {
1703					compatible = "fsl,qoriq-mc-dpmac";
1704					reg = <0x7>;
1705					pcs-handle = <&pcs7>;
1706				};
1707
1708				dpmac8: ethernet@8 {
1709					compatible = "fsl,qoriq-mc-dpmac";
1710					reg = <0x8>;
1711					pcs-handle = <&pcs8>;
1712				};
1713
1714				dpmac9: ethernet@9 {
1715					compatible = "fsl,qoriq-mc-dpmac";
1716					reg = <0x9>;
1717					pcs-handle = <&pcs9>;
1718				};
1719
1720				dpmac10: ethernet@a {
1721					compatible = "fsl,qoriq-mc-dpmac";
1722					reg = <0xa>;
1723					pcs-handle = <&pcs10>;
1724				};
1725
1726				dpmac11: ethernet@b {
1727					compatible = "fsl,qoriq-mc-dpmac";
1728					reg = <0xb>;
1729					pcs-handle = <&pcs11>;
1730				};
1731
1732				dpmac12: ethernet@c {
1733					compatible = "fsl,qoriq-mc-dpmac";
1734					reg = <0xc>;
1735					pcs-handle = <&pcs12>;
1736				};
1737
1738				dpmac13: ethernet@d {
1739					compatible = "fsl,qoriq-mc-dpmac";
1740					reg = <0xd>;
1741					pcs-handle = <&pcs13>;
1742				};
1743
1744				dpmac14: ethernet@e {
1745					compatible = "fsl,qoriq-mc-dpmac";
1746					reg = <0xe>;
1747					pcs-handle = <&pcs14>;
1748				};
1749
1750				dpmac15: ethernet@f {
1751					compatible = "fsl,qoriq-mc-dpmac";
1752					reg = <0xf>;
1753					pcs-handle = <&pcs15>;
1754				};
1755
1756				dpmac16: ethernet@10 {
1757					compatible = "fsl,qoriq-mc-dpmac";
1758					reg = <0x10>;
1759					pcs-handle = <&pcs16>;
1760				};
1761
1762				dpmac17: ethernet@11 {
1763					compatible = "fsl,qoriq-mc-dpmac";
1764					reg = <0x11>;
1765					pcs-handle = <&pcs17>;
1766				};
1767
1768				dpmac18: ethernet@12 {
1769					compatible = "fsl,qoriq-mc-dpmac";
1770					reg = <0x12>;
1771					pcs-handle = <&pcs18>;
1772				};
1773			};
1774		};
1775	};
1776
1777	firmware {
1778		optee: optee {
1779			compatible = "linaro,optee-tz";
1780			method = "smc";
1781			status = "disabled";
1782		};
1783	};
1784};
1785