1d548c217SVabhav Sharma// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2d548c217SVabhav Sharma// 3d548c217SVabhav Sharma// Device Tree Include file for Layerscape-LX2160A family SoC. 4d548c217SVabhav Sharma// 566dfd959SWasim Khan// Copyright 2018-2020 NXP 6d548c217SVabhav Sharma 7d548c217SVabhav Sharma#include <dt-bindings/gpio/gpio.h> 8d548c217SVabhav Sharma#include <dt-bindings/interrupt-controller/arm-gic.h> 95363eaaeSYuantian Tang#include <dt-bindings/thermal/thermal.h> 10d548c217SVabhav Sharma 11d548c217SVabhav Sharma/memreserve/ 0x80000000 0x00010000; 12d548c217SVabhav Sharma 13d548c217SVabhav Sharma/ { 14d548c217SVabhav Sharma compatible = "fsl,lx2160a"; 15d548c217SVabhav Sharma interrupt-parent = <&gic>; 16d548c217SVabhav Sharma #address-cells = <2>; 17d548c217SVabhav Sharma #size-cells = <2>; 18d548c217SVabhav Sharma 19dca78e32SBiwen Li aliases { 20dca78e32SBiwen Li rtc1 = &ftm_alarm0; 21dca78e32SBiwen Li }; 22dca78e32SBiwen Li 23d548c217SVabhav Sharma cpus { 24d548c217SVabhav Sharma #address-cells = <1>; 25d548c217SVabhav Sharma #size-cells = <0>; 26d548c217SVabhav Sharma 27d548c217SVabhav Sharma // 8 clusters having 2 Cortex-A72 cores each 285363eaaeSYuantian Tang cpu0: cpu@0 { 29d548c217SVabhav Sharma device_type = "cpu"; 30d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 31d548c217SVabhav Sharma enable-method = "psci"; 32d548c217SVabhav Sharma reg = <0x0>; 33d548c217SVabhav Sharma clocks = <&clockgen 1 0>; 34d548c217SVabhav Sharma d-cache-size = <0x8000>; 35d548c217SVabhav Sharma d-cache-line-size = <64>; 36d548c217SVabhav Sharma d-cache-sets = <128>; 37d548c217SVabhav Sharma i-cache-size = <0xC000>; 38d548c217SVabhav Sharma i-cache-line-size = <64>; 39d548c217SVabhav Sharma i-cache-sets = <192>; 40d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 4107159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 425363eaaeSYuantian Tang #cooling-cells = <2>; 43d548c217SVabhav Sharma }; 44d548c217SVabhav Sharma 455363eaaeSYuantian Tang cpu1: cpu@1 { 46d548c217SVabhav Sharma device_type = "cpu"; 47d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 48d548c217SVabhav Sharma enable-method = "psci"; 49d548c217SVabhav Sharma reg = <0x1>; 50d548c217SVabhav Sharma clocks = <&clockgen 1 0>; 51d548c217SVabhav Sharma d-cache-size = <0x8000>; 52d548c217SVabhav Sharma d-cache-line-size = <64>; 53d548c217SVabhav Sharma d-cache-sets = <128>; 54d548c217SVabhav Sharma i-cache-size = <0xC000>; 55d548c217SVabhav Sharma i-cache-line-size = <64>; 56d548c217SVabhav Sharma i-cache-sets = <192>; 57d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 5807159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 595363eaaeSYuantian Tang #cooling-cells = <2>; 60d548c217SVabhav Sharma }; 61d548c217SVabhav Sharma 625363eaaeSYuantian Tang cpu100: cpu@100 { 63d548c217SVabhav Sharma device_type = "cpu"; 64d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 65d548c217SVabhav Sharma enable-method = "psci"; 66d548c217SVabhav Sharma reg = <0x100>; 67d548c217SVabhav Sharma clocks = <&clockgen 1 1>; 68d548c217SVabhav Sharma d-cache-size = <0x8000>; 69d548c217SVabhav Sharma d-cache-line-size = <64>; 70d548c217SVabhav Sharma d-cache-sets = <128>; 71d548c217SVabhav Sharma i-cache-size = <0xC000>; 72d548c217SVabhav Sharma i-cache-line-size = <64>; 73d548c217SVabhav Sharma i-cache-sets = <192>; 74d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 7507159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 765363eaaeSYuantian Tang #cooling-cells = <2>; 77d548c217SVabhav Sharma }; 78d548c217SVabhav Sharma 795363eaaeSYuantian Tang cpu101: cpu@101 { 80d548c217SVabhav Sharma device_type = "cpu"; 81d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 82d548c217SVabhav Sharma enable-method = "psci"; 83d548c217SVabhav Sharma reg = <0x101>; 84d548c217SVabhav Sharma clocks = <&clockgen 1 1>; 85d548c217SVabhav Sharma d-cache-size = <0x8000>; 86d548c217SVabhav Sharma d-cache-line-size = <64>; 87d548c217SVabhav Sharma d-cache-sets = <128>; 88d548c217SVabhav Sharma i-cache-size = <0xC000>; 89d548c217SVabhav Sharma i-cache-line-size = <64>; 90d548c217SVabhav Sharma i-cache-sets = <192>; 91d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 9207159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 935363eaaeSYuantian Tang #cooling-cells = <2>; 94d548c217SVabhav Sharma }; 95d548c217SVabhav Sharma 965363eaaeSYuantian Tang cpu200: cpu@200 { 97d548c217SVabhav Sharma device_type = "cpu"; 98d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 99d548c217SVabhav Sharma enable-method = "psci"; 100d548c217SVabhav Sharma reg = <0x200>; 101d548c217SVabhav Sharma clocks = <&clockgen 1 2>; 102d548c217SVabhav Sharma d-cache-size = <0x8000>; 103d548c217SVabhav Sharma d-cache-line-size = <64>; 104d548c217SVabhav Sharma d-cache-sets = <128>; 105d548c217SVabhav Sharma i-cache-size = <0xC000>; 106d548c217SVabhav Sharma i-cache-line-size = <64>; 107d548c217SVabhav Sharma i-cache-sets = <192>; 108d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 10907159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1105363eaaeSYuantian Tang #cooling-cells = <2>; 111d548c217SVabhav Sharma }; 112d548c217SVabhav Sharma 1135363eaaeSYuantian Tang cpu201: cpu@201 { 114d548c217SVabhav Sharma device_type = "cpu"; 115d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 116d548c217SVabhav Sharma enable-method = "psci"; 117d548c217SVabhav Sharma reg = <0x201>; 118d548c217SVabhav Sharma clocks = <&clockgen 1 2>; 119d548c217SVabhav Sharma d-cache-size = <0x8000>; 120d548c217SVabhav Sharma d-cache-line-size = <64>; 121d548c217SVabhav Sharma d-cache-sets = <128>; 122d548c217SVabhav Sharma i-cache-size = <0xC000>; 123d548c217SVabhav Sharma i-cache-line-size = <64>; 124d548c217SVabhav Sharma i-cache-sets = <192>; 125d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 12607159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1275363eaaeSYuantian Tang #cooling-cells = <2>; 128d548c217SVabhav Sharma }; 129d548c217SVabhav Sharma 1305363eaaeSYuantian Tang cpu300: cpu@300 { 131d548c217SVabhav Sharma device_type = "cpu"; 132d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 133d548c217SVabhav Sharma enable-method = "psci"; 134d548c217SVabhav Sharma reg = <0x300>; 135d548c217SVabhav Sharma clocks = <&clockgen 1 3>; 136d548c217SVabhav Sharma d-cache-size = <0x8000>; 137d548c217SVabhav Sharma d-cache-line-size = <64>; 138d548c217SVabhav Sharma d-cache-sets = <128>; 139d548c217SVabhav Sharma i-cache-size = <0xC000>; 140d548c217SVabhav Sharma i-cache-line-size = <64>; 141d548c217SVabhav Sharma i-cache-sets = <192>; 142d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 14307159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1445363eaaeSYuantian Tang #cooling-cells = <2>; 145d548c217SVabhav Sharma }; 146d548c217SVabhav Sharma 1475363eaaeSYuantian Tang cpu301: cpu@301 { 148d548c217SVabhav Sharma device_type = "cpu"; 149d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 150d548c217SVabhav Sharma enable-method = "psci"; 151d548c217SVabhav Sharma reg = <0x301>; 152d548c217SVabhav Sharma clocks = <&clockgen 1 3>; 153d548c217SVabhav Sharma d-cache-size = <0x8000>; 154d548c217SVabhav Sharma d-cache-line-size = <64>; 155d548c217SVabhav Sharma d-cache-sets = <128>; 156d548c217SVabhav Sharma i-cache-size = <0xC000>; 157d548c217SVabhav Sharma i-cache-line-size = <64>; 158d548c217SVabhav Sharma i-cache-sets = <192>; 159d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 16007159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1615363eaaeSYuantian Tang #cooling-cells = <2>; 162d548c217SVabhav Sharma }; 163d548c217SVabhav Sharma 1645363eaaeSYuantian Tang cpu400: cpu@400 { 165d548c217SVabhav Sharma device_type = "cpu"; 166d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 167d548c217SVabhav Sharma enable-method = "psci"; 168d548c217SVabhav Sharma reg = <0x400>; 169d548c217SVabhav Sharma clocks = <&clockgen 1 4>; 170d548c217SVabhav Sharma d-cache-size = <0x8000>; 171d548c217SVabhav Sharma d-cache-line-size = <64>; 172d548c217SVabhav Sharma d-cache-sets = <128>; 173d548c217SVabhav Sharma i-cache-size = <0xC000>; 174d548c217SVabhav Sharma i-cache-line-size = <64>; 175d548c217SVabhav Sharma i-cache-sets = <192>; 176d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 17707159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1785363eaaeSYuantian Tang #cooling-cells = <2>; 179d548c217SVabhav Sharma }; 180d548c217SVabhav Sharma 1815363eaaeSYuantian Tang cpu401: cpu@401 { 182d548c217SVabhav Sharma device_type = "cpu"; 183d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 184d548c217SVabhav Sharma enable-method = "psci"; 185d548c217SVabhav Sharma reg = <0x401>; 186d548c217SVabhav Sharma clocks = <&clockgen 1 4>; 187d548c217SVabhav Sharma d-cache-size = <0x8000>; 188d548c217SVabhav Sharma d-cache-line-size = <64>; 189d548c217SVabhav Sharma d-cache-sets = <128>; 190d548c217SVabhav Sharma i-cache-size = <0xC000>; 191d548c217SVabhav Sharma i-cache-line-size = <64>; 192d548c217SVabhav Sharma i-cache-sets = <192>; 193d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 19407159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1955363eaaeSYuantian Tang #cooling-cells = <2>; 196d548c217SVabhav Sharma }; 197d548c217SVabhav Sharma 1985363eaaeSYuantian Tang cpu500: cpu@500 { 199d548c217SVabhav Sharma device_type = "cpu"; 200d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 201d548c217SVabhav Sharma enable-method = "psci"; 202d548c217SVabhav Sharma reg = <0x500>; 203d548c217SVabhav Sharma clocks = <&clockgen 1 5>; 204d548c217SVabhav Sharma d-cache-size = <0x8000>; 205d548c217SVabhav Sharma d-cache-line-size = <64>; 206d548c217SVabhav Sharma d-cache-sets = <128>; 207d548c217SVabhav Sharma i-cache-size = <0xC000>; 208d548c217SVabhav Sharma i-cache-line-size = <64>; 209d548c217SVabhav Sharma i-cache-sets = <192>; 210d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 21107159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2125363eaaeSYuantian Tang #cooling-cells = <2>; 213d548c217SVabhav Sharma }; 214d548c217SVabhav Sharma 2155363eaaeSYuantian Tang cpu501: cpu@501 { 216d548c217SVabhav Sharma device_type = "cpu"; 217d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 218d548c217SVabhav Sharma enable-method = "psci"; 219d548c217SVabhav Sharma reg = <0x501>; 220d548c217SVabhav Sharma clocks = <&clockgen 1 5>; 221d548c217SVabhav Sharma d-cache-size = <0x8000>; 222d548c217SVabhav Sharma d-cache-line-size = <64>; 223d548c217SVabhav Sharma d-cache-sets = <128>; 224d548c217SVabhav Sharma i-cache-size = <0xC000>; 225d548c217SVabhav Sharma i-cache-line-size = <64>; 226d548c217SVabhav Sharma i-cache-sets = <192>; 227d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 22807159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2295363eaaeSYuantian Tang #cooling-cells = <2>; 230d548c217SVabhav Sharma }; 231d548c217SVabhav Sharma 2325363eaaeSYuantian Tang cpu600: cpu@600 { 233d548c217SVabhav Sharma device_type = "cpu"; 234d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 235d548c217SVabhav Sharma enable-method = "psci"; 236d548c217SVabhav Sharma reg = <0x600>; 237d548c217SVabhav Sharma clocks = <&clockgen 1 6>; 238d548c217SVabhav Sharma d-cache-size = <0x8000>; 239d548c217SVabhav Sharma d-cache-line-size = <64>; 240d548c217SVabhav Sharma d-cache-sets = <128>; 241d548c217SVabhav Sharma i-cache-size = <0xC000>; 242d548c217SVabhav Sharma i-cache-line-size = <64>; 243d548c217SVabhav Sharma i-cache-sets = <192>; 244d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 24507159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2465363eaaeSYuantian Tang #cooling-cells = <2>; 247d548c217SVabhav Sharma }; 248d548c217SVabhav Sharma 2495363eaaeSYuantian Tang cpu601: cpu@601 { 250d548c217SVabhav Sharma device_type = "cpu"; 251d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 252d548c217SVabhav Sharma enable-method = "psci"; 253d548c217SVabhav Sharma reg = <0x601>; 254d548c217SVabhav Sharma clocks = <&clockgen 1 6>; 255d548c217SVabhav Sharma d-cache-size = <0x8000>; 256d548c217SVabhav Sharma d-cache-line-size = <64>; 257d548c217SVabhav Sharma d-cache-sets = <128>; 258d548c217SVabhav Sharma i-cache-size = <0xC000>; 259d548c217SVabhav Sharma i-cache-line-size = <64>; 260d548c217SVabhav Sharma i-cache-sets = <192>; 261d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 26207159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2635363eaaeSYuantian Tang #cooling-cells = <2>; 264d548c217SVabhav Sharma }; 265d548c217SVabhav Sharma 2665363eaaeSYuantian Tang cpu700: cpu@700 { 267d548c217SVabhav Sharma device_type = "cpu"; 268d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 269d548c217SVabhav Sharma enable-method = "psci"; 270d548c217SVabhav Sharma reg = <0x700>; 271d548c217SVabhav Sharma clocks = <&clockgen 1 7>; 272d548c217SVabhav Sharma d-cache-size = <0x8000>; 273d548c217SVabhav Sharma d-cache-line-size = <64>; 274d548c217SVabhav Sharma d-cache-sets = <128>; 275d548c217SVabhav Sharma i-cache-size = <0xC000>; 276d548c217SVabhav Sharma i-cache-line-size = <64>; 277d548c217SVabhav Sharma i-cache-sets = <192>; 278d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 27907159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2805363eaaeSYuantian Tang #cooling-cells = <2>; 281d548c217SVabhav Sharma }; 282d548c217SVabhav Sharma 2835363eaaeSYuantian Tang cpu701: cpu@701 { 284d548c217SVabhav Sharma device_type = "cpu"; 285d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 286d548c217SVabhav Sharma enable-method = "psci"; 287d548c217SVabhav Sharma reg = <0x701>; 288d548c217SVabhav Sharma clocks = <&clockgen 1 7>; 289d548c217SVabhav Sharma d-cache-size = <0x8000>; 290d548c217SVabhav Sharma d-cache-line-size = <64>; 291d548c217SVabhav Sharma d-cache-sets = <128>; 292d548c217SVabhav Sharma i-cache-size = <0xC000>; 293d548c217SVabhav Sharma i-cache-line-size = <64>; 294d548c217SVabhav Sharma i-cache-sets = <192>; 295d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 29607159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2975363eaaeSYuantian Tang #cooling-cells = <2>; 298d548c217SVabhav Sharma }; 299d548c217SVabhav Sharma 300d548c217SVabhav Sharma cluster0_l2: l2-cache0 { 301d548c217SVabhav Sharma compatible = "cache"; 302d548c217SVabhav Sharma cache-size = <0x100000>; 303d548c217SVabhav Sharma cache-line-size = <64>; 304d548c217SVabhav Sharma cache-sets = <1024>; 305d548c217SVabhav Sharma cache-level = <2>; 306d548c217SVabhav Sharma }; 307d548c217SVabhav Sharma 308d548c217SVabhav Sharma cluster1_l2: l2-cache1 { 309d548c217SVabhav Sharma compatible = "cache"; 310d548c217SVabhav Sharma cache-size = <0x100000>; 311d548c217SVabhav Sharma cache-line-size = <64>; 312d548c217SVabhav Sharma cache-sets = <1024>; 313d548c217SVabhav Sharma cache-level = <2>; 314d548c217SVabhav Sharma }; 315d548c217SVabhav Sharma 316d548c217SVabhav Sharma cluster2_l2: l2-cache2 { 317d548c217SVabhav Sharma compatible = "cache"; 318d548c217SVabhav Sharma cache-size = <0x100000>; 319d548c217SVabhav Sharma cache-line-size = <64>; 320d548c217SVabhav Sharma cache-sets = <1024>; 321d548c217SVabhav Sharma cache-level = <2>; 322d548c217SVabhav Sharma }; 323d548c217SVabhav Sharma 324d548c217SVabhav Sharma cluster3_l2: l2-cache3 { 325d548c217SVabhav Sharma compatible = "cache"; 326d548c217SVabhav Sharma cache-size = <0x100000>; 327d548c217SVabhav Sharma cache-line-size = <64>; 328d548c217SVabhav Sharma cache-sets = <1024>; 329d548c217SVabhav Sharma cache-level = <2>; 330d548c217SVabhav Sharma }; 331d548c217SVabhav Sharma 332d548c217SVabhav Sharma cluster4_l2: l2-cache4 { 333d548c217SVabhav Sharma compatible = "cache"; 334d548c217SVabhav Sharma cache-size = <0x100000>; 335d548c217SVabhav Sharma cache-line-size = <64>; 336d548c217SVabhav Sharma cache-sets = <1024>; 337d548c217SVabhav Sharma cache-level = <2>; 338d548c217SVabhav Sharma }; 339d548c217SVabhav Sharma 340d548c217SVabhav Sharma cluster5_l2: l2-cache5 { 341d548c217SVabhav Sharma compatible = "cache"; 342d548c217SVabhav Sharma cache-size = <0x100000>; 343d548c217SVabhav Sharma cache-line-size = <64>; 344d548c217SVabhav Sharma cache-sets = <1024>; 345d548c217SVabhav Sharma cache-level = <2>; 346d548c217SVabhav Sharma }; 347d548c217SVabhav Sharma 348d548c217SVabhav Sharma cluster6_l2: l2-cache6 { 349d548c217SVabhav Sharma compatible = "cache"; 350d548c217SVabhav Sharma cache-size = <0x100000>; 351d548c217SVabhav Sharma cache-line-size = <64>; 352d548c217SVabhav Sharma cache-sets = <1024>; 353d548c217SVabhav Sharma cache-level = <2>; 354d548c217SVabhav Sharma }; 355d548c217SVabhav Sharma 356d548c217SVabhav Sharma cluster7_l2: l2-cache7 { 357d548c217SVabhav Sharma compatible = "cache"; 358d548c217SVabhav Sharma cache-size = <0x100000>; 359d548c217SVabhav Sharma cache-line-size = <64>; 360d548c217SVabhav Sharma cache-sets = <1024>; 361d548c217SVabhav Sharma cache-level = <2>; 362d548c217SVabhav Sharma }; 36300c5ce8aSRan Wang 36407159f67SRan Wang cpu_pw15: cpu-pw15 { 36500c5ce8aSRan Wang compatible = "arm,idle-state"; 36607159f67SRan Wang idle-state-name = "PW15"; 36700c5ce8aSRan Wang arm,psci-suspend-param = <0x0>; 36800c5ce8aSRan Wang entry-latency-us = <2000>; 36900c5ce8aSRan Wang exit-latency-us = <2000>; 37000c5ce8aSRan Wang min-residency-us = <6000>; 37100c5ce8aSRan Wang }; 372d548c217SVabhav Sharma }; 373d548c217SVabhav Sharma 374d548c217SVabhav Sharma gic: interrupt-controller@6000000 { 375d548c217SVabhav Sharma compatible = "arm,gic-v3"; 376d548c217SVabhav Sharma reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 377d548c217SVabhav Sharma <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 378d548c217SVabhav Sharma // SGI_base) 379d548c217SVabhav Sharma <0x0 0x0c0c0000 0 0x2000>, // GICC 380d548c217SVabhav Sharma <0x0 0x0c0d0000 0 0x1000>, // GICH 381d548c217SVabhav Sharma <0x0 0x0c0e0000 0 0x20000>; // GICV 382d548c217SVabhav Sharma #interrupt-cells = <3>; 383d548c217SVabhav Sharma #address-cells = <2>; 384d548c217SVabhav Sharma #size-cells = <2>; 385d548c217SVabhav Sharma ranges; 386d548c217SVabhav Sharma interrupt-controller; 387d548c217SVabhav Sharma interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 388d548c217SVabhav Sharma 389d548c217SVabhav Sharma its: gic-its@6020000 { 390d548c217SVabhav Sharma compatible = "arm,gic-v3-its"; 391d548c217SVabhav Sharma msi-controller; 392d548c217SVabhav Sharma reg = <0x0 0x6020000 0 0x20000>; 393d548c217SVabhav Sharma }; 394d548c217SVabhav Sharma }; 395d548c217SVabhav Sharma 396d548c217SVabhav Sharma timer { 397d548c217SVabhav Sharma compatible = "arm,armv8-timer"; 398d548c217SVabhav Sharma interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 399d548c217SVabhav Sharma <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 400d548c217SVabhav Sharma <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 401d548c217SVabhav Sharma <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 402d548c217SVabhav Sharma }; 403d548c217SVabhav Sharma 404d548c217SVabhav Sharma pmu { 405d548c217SVabhav Sharma compatible = "arm,cortex-a72-pmu"; 406d548c217SVabhav Sharma interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 407d548c217SVabhav Sharma }; 408d548c217SVabhav Sharma 409d548c217SVabhav Sharma psci { 410d548c217SVabhav Sharma compatible = "arm,psci-0.2"; 411d548c217SVabhav Sharma method = "smc"; 412d548c217SVabhav Sharma }; 413d548c217SVabhav Sharma 414d548c217SVabhav Sharma memory@80000000 { 415d548c217SVabhav Sharma // DRAM space - 1, size : 2 GB DRAM 416d548c217SVabhav Sharma device_type = "memory"; 417d548c217SVabhav Sharma reg = <0x00000000 0x80000000 0 0x80000000>; 418d548c217SVabhav Sharma }; 419d548c217SVabhav Sharma 420d548c217SVabhav Sharma ddr1: memory-controller@1080000 { 421d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 422d548c217SVabhav Sharma reg = <0x0 0x1080000 0x0 0x1000>; 423d548c217SVabhav Sharma interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 424d548c217SVabhav Sharma little-endian; 425d548c217SVabhav Sharma }; 426d548c217SVabhav Sharma 427d548c217SVabhav Sharma ddr2: memory-controller@1090000 { 428d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 429d548c217SVabhav Sharma reg = <0x0 0x1090000 0x0 0x1000>; 430d548c217SVabhav Sharma interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 431d548c217SVabhav Sharma little-endian; 432d548c217SVabhav Sharma }; 433d548c217SVabhav Sharma 434d548c217SVabhav Sharma // One clock unit-sysclk node which bootloader require during DT fix-up 435d548c217SVabhav Sharma sysclk: sysclk { 436d548c217SVabhav Sharma compatible = "fixed-clock"; 437d548c217SVabhav Sharma #clock-cells = <0>; 438d548c217SVabhav Sharma clock-frequency = <100000000>; // fixed up by bootloader 439d548c217SVabhav Sharma clock-output-names = "sysclk"; 440d548c217SVabhav Sharma }; 441d548c217SVabhav Sharma 4425363eaaeSYuantian Tang thermal-zones { 443ac082ea8SYuantian Tang cluster6-7 { 4445363eaaeSYuantian Tang polling-delay-passive = <1000>; 4455363eaaeSYuantian Tang polling-delay = <5000>; 4465363eaaeSYuantian Tang thermal-sensors = <&tmu 0>; 4475363eaaeSYuantian Tang 4485363eaaeSYuantian Tang trips { 449ac082ea8SYuantian Tang cluster6_7_alert: cluster6-7-alert { 4505363eaaeSYuantian Tang temperature = <85000>; 4515363eaaeSYuantian Tang hysteresis = <2000>; 4525363eaaeSYuantian Tang type = "passive"; 4535363eaaeSYuantian Tang }; 4545363eaaeSYuantian Tang 455ac082ea8SYuantian Tang cluster6_7_crit: cluster6-7-crit { 4565363eaaeSYuantian Tang temperature = <95000>; 4575363eaaeSYuantian Tang hysteresis = <2000>; 4585363eaaeSYuantian Tang type = "critical"; 4595363eaaeSYuantian Tang }; 4605363eaaeSYuantian Tang }; 4615363eaaeSYuantian Tang 4625363eaaeSYuantian Tang cooling-maps { 4635363eaaeSYuantian Tang map0 { 464ac082ea8SYuantian Tang trip = <&cluster6_7_alert>; 4655363eaaeSYuantian Tang cooling-device = 4665363eaaeSYuantian Tang <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675363eaaeSYuantian Tang <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685363eaaeSYuantian Tang <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4695363eaaeSYuantian Tang <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4705363eaaeSYuantian Tang <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4715363eaaeSYuantian Tang <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725363eaaeSYuantian Tang <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4735363eaaeSYuantian Tang <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4745363eaaeSYuantian Tang <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4755363eaaeSYuantian Tang <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765363eaaeSYuantian Tang <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775363eaaeSYuantian Tang <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4785363eaaeSYuantian Tang <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4795363eaaeSYuantian Tang <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4805363eaaeSYuantian Tang <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815363eaaeSYuantian Tang <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4825363eaaeSYuantian Tang }; 4835363eaaeSYuantian Tang }; 4845363eaaeSYuantian Tang }; 485ac082ea8SYuantian Tang 486ac082ea8SYuantian Tang ddr-cluster5 { 487ac082ea8SYuantian Tang polling-delay-passive = <1000>; 488ac082ea8SYuantian Tang polling-delay = <5000>; 489ac082ea8SYuantian Tang thermal-sensors = <&tmu 1>; 490ac082ea8SYuantian Tang 491ac082ea8SYuantian Tang trips { 492ac082ea8SYuantian Tang ddr-cluster5-alert { 493ac082ea8SYuantian Tang temperature = <85000>; 494ac082ea8SYuantian Tang hysteresis = <2000>; 495ac082ea8SYuantian Tang type = "passive"; 496ac082ea8SYuantian Tang }; 497ac082ea8SYuantian Tang 498ac082ea8SYuantian Tang ddr-cluster5-crit { 499ac082ea8SYuantian Tang temperature = <95000>; 500ac082ea8SYuantian Tang hysteresis = <2000>; 501ac082ea8SYuantian Tang type = "critical"; 502ac082ea8SYuantian Tang }; 503ac082ea8SYuantian Tang }; 504ac082ea8SYuantian Tang }; 505ac082ea8SYuantian Tang 506ac082ea8SYuantian Tang wriop { 507ac082ea8SYuantian Tang polling-delay-passive = <1000>; 508ac082ea8SYuantian Tang polling-delay = <5000>; 509ac082ea8SYuantian Tang thermal-sensors = <&tmu 2>; 510ac082ea8SYuantian Tang 511ac082ea8SYuantian Tang trips { 512ac082ea8SYuantian Tang wriop-alert { 513ac082ea8SYuantian Tang temperature = <85000>; 514ac082ea8SYuantian Tang hysteresis = <2000>; 515ac082ea8SYuantian Tang type = "passive"; 516ac082ea8SYuantian Tang }; 517ac082ea8SYuantian Tang 518ac082ea8SYuantian Tang wriop-crit { 519ac082ea8SYuantian Tang temperature = <95000>; 520ac082ea8SYuantian Tang hysteresis = <2000>; 521ac082ea8SYuantian Tang type = "critical"; 522ac082ea8SYuantian Tang }; 523ac082ea8SYuantian Tang }; 524ac082ea8SYuantian Tang }; 525ac082ea8SYuantian Tang 526ac082ea8SYuantian Tang dce-qbman-hsio2 { 527ac082ea8SYuantian Tang polling-delay-passive = <1000>; 528ac082ea8SYuantian Tang polling-delay = <5000>; 529ac082ea8SYuantian Tang thermal-sensors = <&tmu 3>; 530ac082ea8SYuantian Tang 531ac082ea8SYuantian Tang trips { 532ac082ea8SYuantian Tang dce-qbman-alert { 533ac082ea8SYuantian Tang temperature = <85000>; 534ac082ea8SYuantian Tang hysteresis = <2000>; 535ac082ea8SYuantian Tang type = "passive"; 536ac082ea8SYuantian Tang }; 537ac082ea8SYuantian Tang 538ac082ea8SYuantian Tang dce-qbman-crit { 539ac082ea8SYuantian Tang temperature = <95000>; 540ac082ea8SYuantian Tang hysteresis = <2000>; 541ac082ea8SYuantian Tang type = "critical"; 542ac082ea8SYuantian Tang }; 543ac082ea8SYuantian Tang }; 544ac082ea8SYuantian Tang }; 545ac082ea8SYuantian Tang 546ac082ea8SYuantian Tang ccn-dpaa-tbu { 547ac082ea8SYuantian Tang polling-delay-passive = <1000>; 548ac082ea8SYuantian Tang polling-delay = <5000>; 549ac082ea8SYuantian Tang thermal-sensors = <&tmu 4>; 550ac082ea8SYuantian Tang 551ac082ea8SYuantian Tang trips { 552ac082ea8SYuantian Tang ccn-dpaa-alert { 553ac082ea8SYuantian Tang temperature = <85000>; 554ac082ea8SYuantian Tang hysteresis = <2000>; 555ac082ea8SYuantian Tang type = "passive"; 556ac082ea8SYuantian Tang }; 557ac082ea8SYuantian Tang 558ac082ea8SYuantian Tang ccn-dpaa-crit { 559ac082ea8SYuantian Tang temperature = <95000>; 560ac082ea8SYuantian Tang hysteresis = <2000>; 561ac082ea8SYuantian Tang type = "critical"; 562ac082ea8SYuantian Tang }; 563ac082ea8SYuantian Tang }; 564ac082ea8SYuantian Tang }; 565ac082ea8SYuantian Tang 566ac082ea8SYuantian Tang cluster4-hsio3 { 567ac082ea8SYuantian Tang polling-delay-passive = <1000>; 568ac082ea8SYuantian Tang polling-delay = <5000>; 569ac082ea8SYuantian Tang thermal-sensors = <&tmu 5>; 570ac082ea8SYuantian Tang 571ac082ea8SYuantian Tang trips { 572ac082ea8SYuantian Tang clust4-hsio3-alert { 573ac082ea8SYuantian Tang temperature = <85000>; 574ac082ea8SYuantian Tang hysteresis = <2000>; 575ac082ea8SYuantian Tang type = "passive"; 576ac082ea8SYuantian Tang }; 577ac082ea8SYuantian Tang 578ac082ea8SYuantian Tang clust4-hsio3-crit { 579ac082ea8SYuantian Tang temperature = <95000>; 580ac082ea8SYuantian Tang hysteresis = <2000>; 581ac082ea8SYuantian Tang type = "critical"; 582ac082ea8SYuantian Tang }; 583ac082ea8SYuantian Tang }; 584ac082ea8SYuantian Tang }; 585ac082ea8SYuantian Tang 586ac082ea8SYuantian Tang cluster2-3 { 587ac082ea8SYuantian Tang polling-delay-passive = <1000>; 588ac082ea8SYuantian Tang polling-delay = <5000>; 589ac082ea8SYuantian Tang thermal-sensors = <&tmu 6>; 590ac082ea8SYuantian Tang 591ac082ea8SYuantian Tang trips { 592ac082ea8SYuantian Tang cluster2-3-alert { 593ac082ea8SYuantian Tang temperature = <85000>; 594ac082ea8SYuantian Tang hysteresis = <2000>; 595ac082ea8SYuantian Tang type = "passive"; 596ac082ea8SYuantian Tang }; 597ac082ea8SYuantian Tang 598ac082ea8SYuantian Tang cluster2-3-crit { 599ac082ea8SYuantian Tang temperature = <95000>; 600ac082ea8SYuantian Tang hysteresis = <2000>; 601ac082ea8SYuantian Tang type = "critical"; 602ac082ea8SYuantian Tang }; 603ac082ea8SYuantian Tang }; 604ac082ea8SYuantian Tang }; 6055363eaaeSYuantian Tang }; 6065363eaaeSYuantian Tang 607d548c217SVabhav Sharma soc { 608d548c217SVabhav Sharma compatible = "simple-bus"; 609d548c217SVabhav Sharma #address-cells = <2>; 610d548c217SVabhav Sharma #size-cells = <2>; 611d548c217SVabhav Sharma ranges; 6120154878dSIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 613d548c217SVabhav Sharma 614d548c217SVabhav Sharma crypto: crypto@8000000 { 615d548c217SVabhav Sharma compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 616d548c217SVabhav Sharma fsl,sec-era = <10>; 617d548c217SVabhav Sharma #address-cells = <1>; 618d548c217SVabhav Sharma #size-cells = <1>; 619d548c217SVabhav Sharma ranges = <0x0 0x00 0x8000000 0x100000>; 620d548c217SVabhav Sharma reg = <0x00 0x8000000 0x0 0x100000>; 621d548c217SVabhav Sharma interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 622d548c217SVabhav Sharma dma-coherent; 623d548c217SVabhav Sharma status = "disabled"; 624d548c217SVabhav Sharma 625d548c217SVabhav Sharma sec_jr0: jr@10000 { 626d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 627d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 628d548c217SVabhav Sharma reg = <0x10000 0x10000>; 629d548c217SVabhav Sharma interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 630d548c217SVabhav Sharma }; 631d548c217SVabhav Sharma 632d548c217SVabhav Sharma sec_jr1: jr@20000 { 633d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 634d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 635d548c217SVabhav Sharma reg = <0x20000 0x10000>; 636d548c217SVabhav Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 637d548c217SVabhav Sharma }; 638d548c217SVabhav Sharma 639d548c217SVabhav Sharma sec_jr2: jr@30000 { 640d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 641d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 642d548c217SVabhav Sharma reg = <0x30000 0x10000>; 643d548c217SVabhav Sharma interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 644d548c217SVabhav Sharma }; 645d548c217SVabhav Sharma 646d548c217SVabhav Sharma sec_jr3: jr@40000 { 647d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 648d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 649d548c217SVabhav Sharma reg = <0x40000 0x10000>; 650d548c217SVabhav Sharma interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 651d548c217SVabhav Sharma }; 652d548c217SVabhav Sharma }; 653d548c217SVabhav Sharma 654d548c217SVabhav Sharma clockgen: clock-controller@1300000 { 655d548c217SVabhav Sharma compatible = "fsl,lx2160a-clockgen"; 656d548c217SVabhav Sharma reg = <0 0x1300000 0 0xa0000>; 657d548c217SVabhav Sharma #clock-cells = <2>; 658d548c217SVabhav Sharma clocks = <&sysclk>; 659d548c217SVabhav Sharma }; 660d548c217SVabhav Sharma 661d548c217SVabhav Sharma dcfg: syscon@1e00000 { 662d548c217SVabhav Sharma compatible = "fsl,lx2160a-dcfg", "syscon"; 663d548c217SVabhav Sharma reg = <0x0 0x1e00000 0x0 0x10000>; 664d548c217SVabhav Sharma little-endian; 665d548c217SVabhav Sharma }; 666d548c217SVabhav Sharma 6675363eaaeSYuantian Tang tmu: tmu@1f80000 { 6685363eaaeSYuantian Tang compatible = "fsl,qoriq-tmu"; 6695363eaaeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 6705363eaaeSYuantian Tang interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 6715363eaaeSYuantian Tang fsl,tmu-range = <0x800000e6 0x8001017d>; 6725363eaaeSYuantian Tang fsl,tmu-calibration = 6735363eaaeSYuantian Tang /* Calibration data group 1 */ 6745363eaaeSYuantian Tang <0x00000000 0x00000035 6755363eaaeSYuantian Tang /* Calibration data group 2 */ 676ac082ea8SYuantian Tang 0x00000001 0x00000154>; 6775363eaaeSYuantian Tang little-endian; 6785363eaaeSYuantian Tang #thermal-sensor-cells = <1>; 6795363eaaeSYuantian Tang }; 6805363eaaeSYuantian Tang 681d548c217SVabhav Sharma i2c0: i2c@2000000 { 682d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 683d548c217SVabhav Sharma #address-cells = <1>; 684d548c217SVabhav Sharma #size-cells = <0>; 685d548c217SVabhav Sharma reg = <0x0 0x2000000 0x0 0x10000>; 686d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 687d548c217SVabhav Sharma clock-names = "i2c"; 6887cb220a7SChuanhua Han clocks = <&clockgen 4 15>; 689d548c217SVabhav Sharma scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; 690d548c217SVabhav Sharma status = "disabled"; 691d548c217SVabhav Sharma }; 692d548c217SVabhav Sharma 693d548c217SVabhav Sharma i2c1: i2c@2010000 { 694d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 695d548c217SVabhav Sharma #address-cells = <1>; 696d548c217SVabhav Sharma #size-cells = <0>; 697d548c217SVabhav Sharma reg = <0x0 0x2010000 0x0 0x10000>; 698d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 699d548c217SVabhav Sharma clock-names = "i2c"; 7007cb220a7SChuanhua Han clocks = <&clockgen 4 15>; 701d548c217SVabhav Sharma status = "disabled"; 702d548c217SVabhav Sharma }; 703d548c217SVabhav Sharma 704d548c217SVabhav Sharma i2c2: i2c@2020000 { 705d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 706d548c217SVabhav Sharma #address-cells = <1>; 707d548c217SVabhav Sharma #size-cells = <0>; 708d548c217SVabhav Sharma reg = <0x0 0x2020000 0x0 0x10000>; 709d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 710d548c217SVabhav Sharma clock-names = "i2c"; 7117cb220a7SChuanhua Han clocks = <&clockgen 4 15>; 712d548c217SVabhav Sharma status = "disabled"; 713d548c217SVabhav Sharma }; 714d548c217SVabhav Sharma 715d548c217SVabhav Sharma i2c3: i2c@2030000 { 716d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 717d548c217SVabhav Sharma #address-cells = <1>; 718d548c217SVabhav Sharma #size-cells = <0>; 719d548c217SVabhav Sharma reg = <0x0 0x2030000 0x0 0x10000>; 720d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 721d548c217SVabhav Sharma clock-names = "i2c"; 7227cb220a7SChuanhua Han clocks = <&clockgen 4 15>; 723d548c217SVabhav Sharma status = "disabled"; 724d548c217SVabhav Sharma }; 725d548c217SVabhav Sharma 726d548c217SVabhav Sharma i2c4: i2c@2040000 { 727d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 728d548c217SVabhav Sharma #address-cells = <1>; 729d548c217SVabhav Sharma #size-cells = <0>; 730d548c217SVabhav Sharma reg = <0x0 0x2040000 0x0 0x10000>; 731d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 732d548c217SVabhav Sharma clock-names = "i2c"; 7337cb220a7SChuanhua Han clocks = <&clockgen 4 15>; 734d548c217SVabhav Sharma scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; 735d548c217SVabhav Sharma status = "disabled"; 736d548c217SVabhav Sharma }; 737d548c217SVabhav Sharma 738d548c217SVabhav Sharma i2c5: i2c@2050000 { 739d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 740d548c217SVabhav Sharma #address-cells = <1>; 741d548c217SVabhav Sharma #size-cells = <0>; 742d548c217SVabhav Sharma reg = <0x0 0x2050000 0x0 0x10000>; 743d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 744d548c217SVabhav Sharma clock-names = "i2c"; 7457cb220a7SChuanhua Han clocks = <&clockgen 4 15>; 746d548c217SVabhav Sharma status = "disabled"; 747d548c217SVabhav Sharma }; 748d548c217SVabhav Sharma 749d548c217SVabhav Sharma i2c6: i2c@2060000 { 750d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 751d548c217SVabhav Sharma #address-cells = <1>; 752d548c217SVabhav Sharma #size-cells = <0>; 753d548c217SVabhav Sharma reg = <0x0 0x2060000 0x0 0x10000>; 754d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 755d548c217SVabhav Sharma clock-names = "i2c"; 7567cb220a7SChuanhua Han clocks = <&clockgen 4 15>; 757d548c217SVabhav Sharma status = "disabled"; 758d548c217SVabhav Sharma }; 759d548c217SVabhav Sharma 760d548c217SVabhav Sharma i2c7: i2c@2070000 { 761d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 762d548c217SVabhav Sharma #address-cells = <1>; 763d548c217SVabhav Sharma #size-cells = <0>; 764d548c217SVabhav Sharma reg = <0x0 0x2070000 0x0 0x10000>; 765d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 766d548c217SVabhav Sharma clock-names = "i2c"; 7677cb220a7SChuanhua Han clocks = <&clockgen 4 15>; 768d548c217SVabhav Sharma status = "disabled"; 769d548c217SVabhav Sharma }; 770d548c217SVabhav Sharma 7711ffeef4eSYogesh Narayan Gaur fspi: spi@20c0000 { 7721ffeef4eSYogesh Narayan Gaur compatible = "nxp,lx2160a-fspi"; 7731ffeef4eSYogesh Narayan Gaur #address-cells = <1>; 7741ffeef4eSYogesh Narayan Gaur #size-cells = <0>; 7751ffeef4eSYogesh Narayan Gaur reg = <0x0 0x20c0000 0x0 0x10000>, 7761ffeef4eSYogesh Narayan Gaur <0x0 0x20000000 0x0 0x10000000>; 7771ffeef4eSYogesh Narayan Gaur reg-names = "fspi_base", "fspi_mmap"; 7781ffeef4eSYogesh Narayan Gaur interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 7791ffeef4eSYogesh Narayan Gaur clocks = <&clockgen 4 3>, <&clockgen 4 3>; 7801ffeef4eSYogesh Narayan Gaur clock-names = "fspi_en", "fspi"; 7811ffeef4eSYogesh Narayan Gaur status = "disabled"; 7821ffeef4eSYogesh Narayan Gaur }; 7831ffeef4eSYogesh Narayan Gaur 78483ebd4a5SChuanhua Han dspi0: spi@2100000 { 78583ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 78683ebd4a5SChuanhua Han #address-cells = <1>; 78783ebd4a5SChuanhua Han #size-cells = <0>; 78883ebd4a5SChuanhua Han reg = <0x0 0x2100000 0x0 0x10000>; 78983ebd4a5SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 79083ebd4a5SChuanhua Han clocks = <&clockgen 4 7>; 79183ebd4a5SChuanhua Han clock-names = "dspi"; 79283ebd4a5SChuanhua Han spi-num-chipselects = <5>; 79383ebd4a5SChuanhua Han bus-num = <0>; 79483ebd4a5SChuanhua Han status = "disabled"; 79583ebd4a5SChuanhua Han }; 79683ebd4a5SChuanhua Han 79783ebd4a5SChuanhua Han dspi1: spi@2110000 { 79883ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 79983ebd4a5SChuanhua Han #address-cells = <1>; 80083ebd4a5SChuanhua Han #size-cells = <0>; 80183ebd4a5SChuanhua Han reg = <0x0 0x2110000 0x0 0x10000>; 80283ebd4a5SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 80383ebd4a5SChuanhua Han clocks = <&clockgen 4 7>; 80483ebd4a5SChuanhua Han clock-names = "dspi"; 80583ebd4a5SChuanhua Han spi-num-chipselects = <5>; 80683ebd4a5SChuanhua Han bus-num = <1>; 80783ebd4a5SChuanhua Han status = "disabled"; 80883ebd4a5SChuanhua Han }; 80983ebd4a5SChuanhua Han 81083ebd4a5SChuanhua Han dspi2: spi@2120000 { 81183ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 81283ebd4a5SChuanhua Han #address-cells = <1>; 81383ebd4a5SChuanhua Han #size-cells = <0>; 81483ebd4a5SChuanhua Han reg = <0x0 0x2120000 0x0 0x10000>; 81583ebd4a5SChuanhua Han interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 81683ebd4a5SChuanhua Han clocks = <&clockgen 4 7>; 81783ebd4a5SChuanhua Han clock-names = "dspi"; 81883ebd4a5SChuanhua Han spi-num-chipselects = <5>; 81983ebd4a5SChuanhua Han bus-num = <2>; 82083ebd4a5SChuanhua Han status = "disabled"; 82183ebd4a5SChuanhua Han }; 82283ebd4a5SChuanhua Han 823d548c217SVabhav Sharma esdhc0: esdhc@2140000 { 824d548c217SVabhav Sharma compatible = "fsl,esdhc"; 825d548c217SVabhav Sharma reg = <0x0 0x2140000 0x0 0x10000>; 826d548c217SVabhav Sharma interrupts = <0 28 0x4>; /* Level high type */ 827d548c217SVabhav Sharma clocks = <&clockgen 4 1>; 82862b4359cSRussell King dma-coherent; 829d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 830d548c217SVabhav Sharma sdhci,auto-cmd12; 831d548c217SVabhav Sharma little-endian; 832d548c217SVabhav Sharma bus-width = <4>; 833d548c217SVabhav Sharma status = "disabled"; 834d548c217SVabhav Sharma }; 835d548c217SVabhav Sharma 836d548c217SVabhav Sharma esdhc1: esdhc@2150000 { 837d548c217SVabhav Sharma compatible = "fsl,esdhc"; 838d548c217SVabhav Sharma reg = <0x0 0x2150000 0x0 0x10000>; 839d548c217SVabhav Sharma interrupts = <0 63 0x4>; /* Level high type */ 840d548c217SVabhav Sharma clocks = <&clockgen 4 1>; 84162b4359cSRussell King dma-coherent; 842d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 843d548c217SVabhav Sharma sdhci,auto-cmd12; 844d548c217SVabhav Sharma broken-cd; 845d548c217SVabhav Sharma little-endian; 846d548c217SVabhav Sharma bus-width = <4>; 847d548c217SVabhav Sharma status = "disabled"; 848d548c217SVabhav Sharma }; 849d548c217SVabhav Sharma 850d548c217SVabhav Sharma uart0: serial@21c0000 { 851d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 852d548c217SVabhav Sharma reg = <0x0 0x21c0000 0x0 0x1000>; 853d548c217SVabhav Sharma interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 854d548c217SVabhav Sharma current-speed = <115200>; 855d548c217SVabhav Sharma status = "disabled"; 856d548c217SVabhav Sharma }; 857d548c217SVabhav Sharma 858d548c217SVabhav Sharma uart1: serial@21d0000 { 859d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 860d548c217SVabhav Sharma reg = <0x0 0x21d0000 0x0 0x1000>; 861d548c217SVabhav Sharma interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 862d548c217SVabhav Sharma current-speed = <115200>; 863d548c217SVabhav Sharma status = "disabled"; 864d548c217SVabhav Sharma }; 865d548c217SVabhav Sharma 866d548c217SVabhav Sharma uart2: serial@21e0000 { 867d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 868d548c217SVabhav Sharma reg = <0x0 0x21e0000 0x0 0x1000>; 869d548c217SVabhav Sharma interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 870d548c217SVabhav Sharma current-speed = <115200>; 871d548c217SVabhav Sharma status = "disabled"; 872d548c217SVabhav Sharma }; 873d548c217SVabhav Sharma 874d548c217SVabhav Sharma uart3: serial@21f0000 { 875d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 876d548c217SVabhav Sharma reg = <0x0 0x21f0000 0x0 0x1000>; 877d548c217SVabhav Sharma interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 878d548c217SVabhav Sharma current-speed = <115200>; 879d548c217SVabhav Sharma status = "disabled"; 880d548c217SVabhav Sharma }; 881d548c217SVabhav Sharma 882d548c217SVabhav Sharma gpio0: gpio@2300000 { 883d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 884d548c217SVabhav Sharma reg = <0x0 0x2300000 0x0 0x10000>; 885d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 886d548c217SVabhav Sharma gpio-controller; 887d548c217SVabhav Sharma little-endian; 888d548c217SVabhav Sharma #gpio-cells = <2>; 889d548c217SVabhav Sharma interrupt-controller; 890d548c217SVabhav Sharma #interrupt-cells = <2>; 891d548c217SVabhav Sharma }; 892d548c217SVabhav Sharma 893d548c217SVabhav Sharma gpio1: gpio@2310000 { 894d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 895d548c217SVabhav Sharma reg = <0x0 0x2310000 0x0 0x10000>; 896d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 897d548c217SVabhav Sharma gpio-controller; 898d548c217SVabhav Sharma little-endian; 899d548c217SVabhav Sharma #gpio-cells = <2>; 900d548c217SVabhav Sharma interrupt-controller; 901d548c217SVabhav Sharma #interrupt-cells = <2>; 902d548c217SVabhav Sharma }; 903d548c217SVabhav Sharma 904d548c217SVabhav Sharma gpio2: gpio@2320000 { 905d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 906d548c217SVabhav Sharma reg = <0x0 0x2320000 0x0 0x10000>; 907d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 908d548c217SVabhav Sharma gpio-controller; 909d548c217SVabhav Sharma little-endian; 910d548c217SVabhav Sharma #gpio-cells = <2>; 911d548c217SVabhav Sharma interrupt-controller; 912d548c217SVabhav Sharma #interrupt-cells = <2>; 913d548c217SVabhav Sharma }; 914d548c217SVabhav Sharma 915d548c217SVabhav Sharma gpio3: gpio@2330000 { 916d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 917d548c217SVabhav Sharma reg = <0x0 0x2330000 0x0 0x10000>; 918d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 919d548c217SVabhav Sharma gpio-controller; 920d548c217SVabhav Sharma little-endian; 921d548c217SVabhav Sharma #gpio-cells = <2>; 922d548c217SVabhav Sharma interrupt-controller; 923d548c217SVabhav Sharma #interrupt-cells = <2>; 924d548c217SVabhav Sharma }; 925d548c217SVabhav Sharma 926d548c217SVabhav Sharma watchdog@23a0000 { 927d548c217SVabhav Sharma compatible = "arm,sbsa-gwdt"; 928d548c217SVabhav Sharma reg = <0x0 0x23a0000 0 0x1000>, 929d548c217SVabhav Sharma <0x0 0x2390000 0 0x1000>; 930d548c217SVabhav Sharma interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 931d548c217SVabhav Sharma timeout-sec = <30>; 932d548c217SVabhav Sharma }; 933d548c217SVabhav Sharma 934dca78e32SBiwen Li rcpm: power-controller@1e34040 { 935dca78e32SBiwen Li compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 936dca78e32SBiwen Li reg = <0x0 0x1e34040 0x0 0x1c>; 937dca78e32SBiwen Li #fsl,rcpm-wakeup-cells = <7>; 938dca78e32SBiwen Li little-endian; 939dca78e32SBiwen Li }; 940dca78e32SBiwen Li 941dca78e32SBiwen Li ftm_alarm0: timer@2800000 { 942dca78e32SBiwen Li compatible = "fsl,lx2160a-ftm-alarm"; 943dca78e32SBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 944dca78e32SBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 945dca78e32SBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 946dca78e32SBiwen Li }; 947dca78e32SBiwen Li 948d548c217SVabhav Sharma usb0: usb@3100000 { 949d548c217SVabhav Sharma compatible = "snps,dwc3"; 950d548c217SVabhav Sharma reg = <0x0 0x3100000 0x0 0x10000>; 951d548c217SVabhav Sharma interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 952d548c217SVabhav Sharma dr_mode = "host"; 953d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 954d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 9551000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 956d548c217SVabhav Sharma status = "disabled"; 957d548c217SVabhav Sharma }; 958d548c217SVabhav Sharma 959d548c217SVabhav Sharma usb1: usb@3110000 { 960d548c217SVabhav Sharma compatible = "snps,dwc3"; 961d548c217SVabhav Sharma reg = <0x0 0x3110000 0x0 0x10000>; 962d548c217SVabhav Sharma interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 963d548c217SVabhav Sharma dr_mode = "host"; 964d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 965d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 9661000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 967d548c217SVabhav Sharma status = "disabled"; 968d548c217SVabhav Sharma }; 969d548c217SVabhav Sharma 970071f7855SPeng Ma sata0: sata@3200000 { 971071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 972071f7855SPeng Ma reg = <0x0 0x3200000 0x0 0x10000>, 973071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 974071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 975071f7855SPeng Ma interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 976071f7855SPeng Ma clocks = <&clockgen 4 3>; 977071f7855SPeng Ma dma-coherent; 978071f7855SPeng Ma status = "disabled"; 979071f7855SPeng Ma }; 980071f7855SPeng Ma 981071f7855SPeng Ma sata1: sata@3210000 { 982071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 983071f7855SPeng Ma reg = <0x0 0x3210000 0x0 0x10000>, 984071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 985071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 986071f7855SPeng Ma interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 987071f7855SPeng Ma clocks = <&clockgen 4 3>; 988071f7855SPeng Ma dma-coherent; 989071f7855SPeng Ma status = "disabled"; 990071f7855SPeng Ma }; 991071f7855SPeng Ma 992071f7855SPeng Ma sata2: sata@3220000 { 993071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 994071f7855SPeng Ma reg = <0x0 0x3220000 0x0 0x10000>, 995071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 996071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 997071f7855SPeng Ma interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 998071f7855SPeng Ma clocks = <&clockgen 4 3>; 999071f7855SPeng Ma dma-coherent; 1000071f7855SPeng Ma status = "disabled"; 1001071f7855SPeng Ma }; 1002071f7855SPeng Ma 1003071f7855SPeng Ma sata3: sata@3230000 { 1004071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1005071f7855SPeng Ma reg = <0x0 0x3230000 0x0 0x10000>, 1006071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1007071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1008071f7855SPeng Ma interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1009071f7855SPeng Ma clocks = <&clockgen 4 3>; 1010071f7855SPeng Ma dma-coherent; 1011071f7855SPeng Ma status = "disabled"; 1012071f7855SPeng Ma }; 1013071f7855SPeng Ma 1014f7d48ffcSWasim Khan pcie1: pcie@3400000 { 1015b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1016b1ad0e7dSHou Zhiqiang reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 101766dfd959SWasim Khan 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1018b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1019b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1020b1ad0e7dSHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1021b1ad0e7dSHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1022b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1023b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1024b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1025b1ad0e7dSHou Zhiqiang device_type = "pci"; 1026b1ad0e7dSHou Zhiqiang dma-coherent; 1027b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1028b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1029b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1030b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1031b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1032b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1033b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1034b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1035b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1036b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1037b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1038f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1039b1ad0e7dSHou Zhiqiang status = "disabled"; 1040b1ad0e7dSHou Zhiqiang }; 1041b1ad0e7dSHou Zhiqiang 1042f7d48ffcSWasim Khan pcie2: pcie@3500000 { 1043b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1044b1ad0e7dSHou Zhiqiang reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 104566dfd959SWasim Khan 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1046b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1047b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1048b1ad0e7dSHou Zhiqiang <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1049b1ad0e7dSHou Zhiqiang <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1050b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1051b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1052b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1053b1ad0e7dSHou Zhiqiang device_type = "pci"; 1054b1ad0e7dSHou Zhiqiang dma-coherent; 1055b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1056b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1057b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1058b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1059b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1060b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1061b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1062b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1063b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1064b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1065b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1066f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1067b1ad0e7dSHou Zhiqiang status = "disabled"; 1068b1ad0e7dSHou Zhiqiang }; 1069b1ad0e7dSHou Zhiqiang 1070f7d48ffcSWasim Khan pcie3: pcie@3600000 { 1071b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1072b1ad0e7dSHou Zhiqiang reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 107366dfd959SWasim Khan 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1074b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1075b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1076b1ad0e7dSHou Zhiqiang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1077b1ad0e7dSHou Zhiqiang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1078b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1079b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1080b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1081b1ad0e7dSHou Zhiqiang device_type = "pci"; 1082b1ad0e7dSHou Zhiqiang dma-coherent; 1083b1ad0e7dSHou Zhiqiang apio-wins = <256>; 1084b1ad0e7dSHou Zhiqiang ppio-wins = <24>; 1085b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1086b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1087b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1088b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1089b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1090b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1091b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1092b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1093b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1094f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1095b1ad0e7dSHou Zhiqiang status = "disabled"; 1096b1ad0e7dSHou Zhiqiang }; 1097b1ad0e7dSHou Zhiqiang 1098f7d48ffcSWasim Khan pcie4: pcie@3700000 { 1099b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1100b1ad0e7dSHou Zhiqiang reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 110166dfd959SWasim Khan 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1102b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1103b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1104b1ad0e7dSHou Zhiqiang <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1105b1ad0e7dSHou Zhiqiang <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1106b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1107b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1108b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1109b1ad0e7dSHou Zhiqiang device_type = "pci"; 1110b1ad0e7dSHou Zhiqiang dma-coherent; 1111b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1112b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1113b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1114b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1115b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1116b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1117b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1118b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1119b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1120b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1121b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1122f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1123b1ad0e7dSHou Zhiqiang status = "disabled"; 1124b1ad0e7dSHou Zhiqiang }; 1125b1ad0e7dSHou Zhiqiang 1126f7d48ffcSWasim Khan pcie5: pcie@3800000 { 1127b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1128b1ad0e7dSHou Zhiqiang reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ 112966dfd959SWasim Khan 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1130b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1131b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1132b1ad0e7dSHou Zhiqiang <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1133b1ad0e7dSHou Zhiqiang <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1134b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1135b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1136b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1137b1ad0e7dSHou Zhiqiang device_type = "pci"; 1138b1ad0e7dSHou Zhiqiang dma-coherent; 1139b1ad0e7dSHou Zhiqiang apio-wins = <256>; 1140b1ad0e7dSHou Zhiqiang ppio-wins = <24>; 1141b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1142b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1143b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1144b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1145b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1146b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1147b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1148b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1149b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1150f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1151b1ad0e7dSHou Zhiqiang status = "disabled"; 1152b1ad0e7dSHou Zhiqiang }; 1153b1ad0e7dSHou Zhiqiang 1154f7d48ffcSWasim Khan pcie6: pcie@3900000 { 1155b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1156b1ad0e7dSHou Zhiqiang reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ 115766dfd959SWasim Khan 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1158b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1159b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1160b1ad0e7dSHou Zhiqiang <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1161b1ad0e7dSHou Zhiqiang <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1162b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1163b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1164b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1165b1ad0e7dSHou Zhiqiang device_type = "pci"; 1166b1ad0e7dSHou Zhiqiang dma-coherent; 1167b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1168b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1169b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1170b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1171b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1172b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1173b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1174b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1175b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1176b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1177b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1178f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1179b1ad0e7dSHou Zhiqiang status = "disabled"; 1180b1ad0e7dSHou Zhiqiang }; 1181b1ad0e7dSHou Zhiqiang 1182d548c217SVabhav Sharma smmu: iommu@5000000 { 1183d548c217SVabhav Sharma compatible = "arm,mmu-500"; 1184d548c217SVabhav Sharma reg = <0 0x5000000 0 0x800000>; 1185d548c217SVabhav Sharma #iommu-cells = <1>; 1186d548c217SVabhav Sharma #global-interrupts = <14>; 1187d548c217SVabhav Sharma // global secure fault 1188d548c217SVabhav Sharma interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1189d548c217SVabhav Sharma // combined secure 1190d548c217SVabhav Sharma <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1191d548c217SVabhav Sharma // global non-secure fault 1192d548c217SVabhav Sharma <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1193d548c217SVabhav Sharma // combined non-secure 1194d548c217SVabhav Sharma <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1195d548c217SVabhav Sharma // performance counter interrupts 0-9 1196d548c217SVabhav Sharma <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1197d548c217SVabhav Sharma <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1198d548c217SVabhav Sharma <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1199d548c217SVabhav Sharma <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1200d548c217SVabhav Sharma <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1201d548c217SVabhav Sharma <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1202d548c217SVabhav Sharma <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1203d548c217SVabhav Sharma <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1204d548c217SVabhav Sharma <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1205d548c217SVabhav Sharma <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1206d548c217SVabhav Sharma // per context interrupt, 64 interrupts 1207d548c217SVabhav Sharma <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1208d548c217SVabhav Sharma <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1209d548c217SVabhav Sharma <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1210d548c217SVabhav Sharma <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1211d548c217SVabhav Sharma <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1212d548c217SVabhav Sharma <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1213d548c217SVabhav Sharma <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1214d548c217SVabhav Sharma <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1215d548c217SVabhav Sharma <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1216d548c217SVabhav Sharma <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1217d548c217SVabhav Sharma <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1218d548c217SVabhav Sharma <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1219d548c217SVabhav Sharma <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1220d548c217SVabhav Sharma <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1221d548c217SVabhav Sharma <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1222d548c217SVabhav Sharma <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1223d548c217SVabhav Sharma <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1224d548c217SVabhav Sharma <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1225d548c217SVabhav Sharma <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1226d548c217SVabhav Sharma <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1227d548c217SVabhav Sharma <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1228d548c217SVabhav Sharma <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1229d548c217SVabhav Sharma <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1230d548c217SVabhav Sharma <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1231d548c217SVabhav Sharma <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1232d548c217SVabhav Sharma <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1233d548c217SVabhav Sharma <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1234d548c217SVabhav Sharma <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1235d548c217SVabhav Sharma <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1236d548c217SVabhav Sharma <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1237d548c217SVabhav Sharma <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1238d548c217SVabhav Sharma <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1239d548c217SVabhav Sharma <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1240d548c217SVabhav Sharma <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1241d548c217SVabhav Sharma <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1242d548c217SVabhav Sharma <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1243d548c217SVabhav Sharma <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1244d548c217SVabhav Sharma <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1245d548c217SVabhav Sharma <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1246d548c217SVabhav Sharma <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1247d548c217SVabhav Sharma <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1248d548c217SVabhav Sharma <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1249d548c217SVabhav Sharma <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1250d548c217SVabhav Sharma <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1251d548c217SVabhav Sharma <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1252d548c217SVabhav Sharma <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1253d548c217SVabhav Sharma <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1254d548c217SVabhav Sharma <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1255d548c217SVabhav Sharma <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1256d548c217SVabhav Sharma <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1257d548c217SVabhav Sharma <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1258d548c217SVabhav Sharma <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1259d548c217SVabhav Sharma <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1260d548c217SVabhav Sharma <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1261d548c217SVabhav Sharma <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1262d548c217SVabhav Sharma <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1263d548c217SVabhav Sharma <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1264d548c217SVabhav Sharma <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1265d548c217SVabhav Sharma <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1266d548c217SVabhav Sharma <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1267d548c217SVabhav Sharma <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1268d548c217SVabhav Sharma <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1269d548c217SVabhav Sharma <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1270d548c217SVabhav Sharma <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1271d548c217SVabhav Sharma dma-coherent; 1272d548c217SVabhav Sharma }; 1273703c5e40SIoana Ciocoi Radulescu 1274546d92d3SIoana Ciornei console@8340020 { 1275546d92d3SIoana Ciornei compatible = "fsl,dpaa2-console"; 1276546d92d3SIoana Ciornei reg = <0x00000000 0x08340020 0 0x2>; 1277546d92d3SIoana Ciornei }; 1278546d92d3SIoana Ciornei 1279fe844f19SYangbo Lu ptp-timer@8b95000 { 1280fe844f19SYangbo Lu compatible = "fsl,dpaa2-ptp"; 1281fe844f19SYangbo Lu reg = <0x0 0x8b95000 0x0 0x100>; 1282fe844f19SYangbo Lu clocks = <&clockgen 4 1>; 1283fe844f19SYangbo Lu little-endian; 1284fe844f19SYangbo Lu fsl,extts-fifo; 1285fe844f19SYangbo Lu }; 1286fe844f19SYangbo Lu 12876e1b8faeSIoana Ciornei /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 12886e1b8faeSIoana Ciornei emdio1: mdio@8b96000 { 12896e1b8faeSIoana Ciornei compatible = "fsl,fman-memac-mdio"; 12906e1b8faeSIoana Ciornei reg = <0x0 0x8b96000 0x0 0x1000>; 12916e1b8faeSIoana Ciornei interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 12926e1b8faeSIoana Ciornei #address-cells = <1>; 12936e1b8faeSIoana Ciornei #size-cells = <0>; 12946e1b8faeSIoana Ciornei little-endian; 12956e1b8faeSIoana Ciornei status = "disabled"; 12966e1b8faeSIoana Ciornei }; 12976e1b8faeSIoana Ciornei 12985705b9dcSRussell King emdio2: mdio@8b97000 { 12995705b9dcSRussell King compatible = "fsl,fman-memac-mdio"; 13005705b9dcSRussell King reg = <0x0 0x8b97000 0x0 0x1000>; 13015705b9dcSRussell King interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 13025705b9dcSRussell King little-endian; 13035705b9dcSRussell King #address-cells = <1>; 13045705b9dcSRussell King #size-cells = <0>; 13055705b9dcSRussell King status = "disabled"; 13065705b9dcSRussell King }; 13075705b9dcSRussell King 1308703c5e40SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 1309703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 1310703c5e40SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, 1311703c5e40SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; 1312703c5e40SIoana Ciocoi Radulescu msi-parent = <&its>; 1313703c5e40SIoana Ciocoi Radulescu /* iommu-map property is fixed up by u-boot */ 1314703c5e40SIoana Ciocoi Radulescu iommu-map = <0 &smmu 0 0>; 1315703c5e40SIoana Ciocoi Radulescu dma-coherent; 1316703c5e40SIoana Ciocoi Radulescu #address-cells = <3>; 1317703c5e40SIoana Ciocoi Radulescu #size-cells = <1>; 1318703c5e40SIoana Ciocoi Radulescu 1319703c5e40SIoana Ciocoi Radulescu /* 1320703c5e40SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 1321703c5e40SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 1322703c5e40SIoana Ciocoi Radulescu */ 1323703c5e40SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1324703c5e40SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1325703c5e40SIoana Ciocoi Radulescu 1326703c5e40SIoana Ciocoi Radulescu /* 1327703c5e40SIoana Ciocoi Radulescu * Define the maximum number of MACs present on the SoC. 1328703c5e40SIoana Ciocoi Radulescu */ 1329703c5e40SIoana Ciocoi Radulescu dpmacs { 1330703c5e40SIoana Ciocoi Radulescu #address-cells = <1>; 1331703c5e40SIoana Ciocoi Radulescu #size-cells = <0>; 1332703c5e40SIoana Ciocoi Radulescu 1333703c5e40SIoana Ciocoi Radulescu dpmac1: dpmac@1 { 1334703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1335703c5e40SIoana Ciocoi Radulescu reg = <0x1>; 1336703c5e40SIoana Ciocoi Radulescu }; 1337703c5e40SIoana Ciocoi Radulescu 1338703c5e40SIoana Ciocoi Radulescu dpmac2: dpmac@2 { 1339703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1340703c5e40SIoana Ciocoi Radulescu reg = <0x2>; 1341703c5e40SIoana Ciocoi Radulescu }; 1342703c5e40SIoana Ciocoi Radulescu 1343703c5e40SIoana Ciocoi Radulescu dpmac3: dpmac@3 { 1344703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1345703c5e40SIoana Ciocoi Radulescu reg = <0x3>; 1346703c5e40SIoana Ciocoi Radulescu }; 1347703c5e40SIoana Ciocoi Radulescu 1348703c5e40SIoana Ciocoi Radulescu dpmac4: dpmac@4 { 1349703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1350703c5e40SIoana Ciocoi Radulescu reg = <0x4>; 1351703c5e40SIoana Ciocoi Radulescu }; 1352703c5e40SIoana Ciocoi Radulescu 1353703c5e40SIoana Ciocoi Radulescu dpmac5: dpmac@5 { 1354703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1355703c5e40SIoana Ciocoi Radulescu reg = <0x5>; 1356703c5e40SIoana Ciocoi Radulescu }; 1357703c5e40SIoana Ciocoi Radulescu 1358703c5e40SIoana Ciocoi Radulescu dpmac6: dpmac@6 { 1359703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1360703c5e40SIoana Ciocoi Radulescu reg = <0x6>; 1361703c5e40SIoana Ciocoi Radulescu }; 1362703c5e40SIoana Ciocoi Radulescu 1363703c5e40SIoana Ciocoi Radulescu dpmac7: dpmac@7 { 1364703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1365703c5e40SIoana Ciocoi Radulescu reg = <0x7>; 1366703c5e40SIoana Ciocoi Radulescu }; 1367703c5e40SIoana Ciocoi Radulescu 1368703c5e40SIoana Ciocoi Radulescu dpmac8: dpmac@8 { 1369703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1370703c5e40SIoana Ciocoi Radulescu reg = <0x8>; 1371703c5e40SIoana Ciocoi Radulescu }; 1372703c5e40SIoana Ciocoi Radulescu 1373703c5e40SIoana Ciocoi Radulescu dpmac9: dpmac@9 { 1374703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1375703c5e40SIoana Ciocoi Radulescu reg = <0x9>; 1376703c5e40SIoana Ciocoi Radulescu }; 1377703c5e40SIoana Ciocoi Radulescu 1378703c5e40SIoana Ciocoi Radulescu dpmac10: dpmac@a { 1379703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1380703c5e40SIoana Ciocoi Radulescu reg = <0xa>; 1381703c5e40SIoana Ciocoi Radulescu }; 1382703c5e40SIoana Ciocoi Radulescu 1383703c5e40SIoana Ciocoi Radulescu dpmac11: dpmac@b { 1384703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1385703c5e40SIoana Ciocoi Radulescu reg = <0xb>; 1386703c5e40SIoana Ciocoi Radulescu }; 1387703c5e40SIoana Ciocoi Radulescu 1388703c5e40SIoana Ciocoi Radulescu dpmac12: dpmac@c { 1389703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1390703c5e40SIoana Ciocoi Radulescu reg = <0xc>; 1391703c5e40SIoana Ciocoi Radulescu }; 1392703c5e40SIoana Ciocoi Radulescu 1393703c5e40SIoana Ciocoi Radulescu dpmac13: dpmac@d { 1394703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1395703c5e40SIoana Ciocoi Radulescu reg = <0xd>; 1396703c5e40SIoana Ciocoi Radulescu }; 1397703c5e40SIoana Ciocoi Radulescu 1398703c5e40SIoana Ciocoi Radulescu dpmac14: dpmac@e { 1399703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1400703c5e40SIoana Ciocoi Radulescu reg = <0xe>; 1401703c5e40SIoana Ciocoi Radulescu }; 1402703c5e40SIoana Ciocoi Radulescu 1403703c5e40SIoana Ciocoi Radulescu dpmac15: dpmac@f { 1404703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1405703c5e40SIoana Ciocoi Radulescu reg = <0xf>; 1406703c5e40SIoana Ciocoi Radulescu }; 1407703c5e40SIoana Ciocoi Radulescu 1408703c5e40SIoana Ciocoi Radulescu dpmac16: dpmac@10 { 1409703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1410703c5e40SIoana Ciocoi Radulescu reg = <0x10>; 1411703c5e40SIoana Ciocoi Radulescu }; 1412703c5e40SIoana Ciocoi Radulescu 1413703c5e40SIoana Ciocoi Radulescu dpmac17: dpmac@11 { 1414703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1415703c5e40SIoana Ciocoi Radulescu reg = <0x11>; 1416703c5e40SIoana Ciocoi Radulescu }; 1417703c5e40SIoana Ciocoi Radulescu 1418703c5e40SIoana Ciocoi Radulescu dpmac18: dpmac@12 { 1419703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1420703c5e40SIoana Ciocoi Radulescu reg = <0x12>; 1421703c5e40SIoana Ciocoi Radulescu }; 1422703c5e40SIoana Ciocoi Radulescu }; 1423703c5e40SIoana Ciocoi Radulescu }; 1424d548c217SVabhav Sharma }; 1425d548c217SVabhav Sharma}; 1426