1d548c217SVabhav Sharma// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2d548c217SVabhav Sharma// 3d548c217SVabhav Sharma// Device Tree Include file for Layerscape-LX2160A family SoC. 4d548c217SVabhav Sharma// 566dfd959SWasim Khan// Copyright 2018-2020 NXP 6d548c217SVabhav Sharma 78e9f7797SMichael Walle#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8d548c217SVabhav Sharma#include <dt-bindings/gpio/gpio.h> 9d548c217SVabhav Sharma#include <dt-bindings/interrupt-controller/arm-gic.h> 105363eaaeSYuantian Tang#include <dt-bindings/thermal/thermal.h> 11d548c217SVabhav Sharma 12d548c217SVabhav Sharma/memreserve/ 0x80000000 0x00010000; 13d548c217SVabhav Sharma 14d548c217SVabhav Sharma/ { 15d548c217SVabhav Sharma compatible = "fsl,lx2160a"; 16d548c217SVabhav Sharma interrupt-parent = <&gic>; 17d548c217SVabhav Sharma #address-cells = <2>; 18d548c217SVabhav Sharma #size-cells = <2>; 19d548c217SVabhav Sharma 20dca78e32SBiwen Li aliases { 21dca78e32SBiwen Li rtc1 = &ftm_alarm0; 22dca78e32SBiwen Li }; 23dca78e32SBiwen Li 24d548c217SVabhav Sharma cpus { 25d548c217SVabhav Sharma #address-cells = <1>; 26d548c217SVabhav Sharma #size-cells = <0>; 27d548c217SVabhav Sharma 28d548c217SVabhav Sharma // 8 clusters having 2 Cortex-A72 cores each 295363eaaeSYuantian Tang cpu0: cpu@0 { 30d548c217SVabhav Sharma device_type = "cpu"; 31d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 32d548c217SVabhav Sharma enable-method = "psci"; 33d548c217SVabhav Sharma reg = <0x0>; 348e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35d548c217SVabhav Sharma d-cache-size = <0x8000>; 36d548c217SVabhav Sharma d-cache-line-size = <64>; 37d548c217SVabhav Sharma d-cache-sets = <128>; 38d548c217SVabhav Sharma i-cache-size = <0xC000>; 39d548c217SVabhav Sharma i-cache-line-size = <64>; 40d548c217SVabhav Sharma i-cache-sets = <192>; 41d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 4207159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 435363eaaeSYuantian Tang #cooling-cells = <2>; 44d548c217SVabhav Sharma }; 45d548c217SVabhav Sharma 465363eaaeSYuantian Tang cpu1: cpu@1 { 47d548c217SVabhav Sharma device_type = "cpu"; 48d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 49d548c217SVabhav Sharma enable-method = "psci"; 50d548c217SVabhav Sharma reg = <0x1>; 518e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52d548c217SVabhav Sharma d-cache-size = <0x8000>; 53d548c217SVabhav Sharma d-cache-line-size = <64>; 54d548c217SVabhav Sharma d-cache-sets = <128>; 55d548c217SVabhav Sharma i-cache-size = <0xC000>; 56d548c217SVabhav Sharma i-cache-line-size = <64>; 57d548c217SVabhav Sharma i-cache-sets = <192>; 58d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 5907159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 605363eaaeSYuantian Tang #cooling-cells = <2>; 61d548c217SVabhav Sharma }; 62d548c217SVabhav Sharma 635363eaaeSYuantian Tang cpu100: cpu@100 { 64d548c217SVabhav Sharma device_type = "cpu"; 65d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 66d548c217SVabhav Sharma enable-method = "psci"; 67d548c217SVabhav Sharma reg = <0x100>; 688e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69d548c217SVabhav Sharma d-cache-size = <0x8000>; 70d548c217SVabhav Sharma d-cache-line-size = <64>; 71d548c217SVabhav Sharma d-cache-sets = <128>; 72d548c217SVabhav Sharma i-cache-size = <0xC000>; 73d548c217SVabhav Sharma i-cache-line-size = <64>; 74d548c217SVabhav Sharma i-cache-sets = <192>; 75d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 7607159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 775363eaaeSYuantian Tang #cooling-cells = <2>; 78d548c217SVabhav Sharma }; 79d548c217SVabhav Sharma 805363eaaeSYuantian Tang cpu101: cpu@101 { 81d548c217SVabhav Sharma device_type = "cpu"; 82d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 83d548c217SVabhav Sharma enable-method = "psci"; 84d548c217SVabhav Sharma reg = <0x101>; 858e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86d548c217SVabhav Sharma d-cache-size = <0x8000>; 87d548c217SVabhav Sharma d-cache-line-size = <64>; 88d548c217SVabhav Sharma d-cache-sets = <128>; 89d548c217SVabhav Sharma i-cache-size = <0xC000>; 90d548c217SVabhav Sharma i-cache-line-size = <64>; 91d548c217SVabhav Sharma i-cache-sets = <192>; 92d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 9307159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 945363eaaeSYuantian Tang #cooling-cells = <2>; 95d548c217SVabhav Sharma }; 96d548c217SVabhav Sharma 975363eaaeSYuantian Tang cpu200: cpu@200 { 98d548c217SVabhav Sharma device_type = "cpu"; 99d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 100d548c217SVabhav Sharma enable-method = "psci"; 101d548c217SVabhav Sharma reg = <0x200>; 1028e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103d548c217SVabhav Sharma d-cache-size = <0x8000>; 104d548c217SVabhav Sharma d-cache-line-size = <64>; 105d548c217SVabhav Sharma d-cache-sets = <128>; 106d548c217SVabhav Sharma i-cache-size = <0xC000>; 107d548c217SVabhav Sharma i-cache-line-size = <64>; 108d548c217SVabhav Sharma i-cache-sets = <192>; 109d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 11007159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1115363eaaeSYuantian Tang #cooling-cells = <2>; 112d548c217SVabhav Sharma }; 113d548c217SVabhav Sharma 1145363eaaeSYuantian Tang cpu201: cpu@201 { 115d548c217SVabhav Sharma device_type = "cpu"; 116d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 117d548c217SVabhav Sharma enable-method = "psci"; 118d548c217SVabhav Sharma reg = <0x201>; 1198e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120d548c217SVabhav Sharma d-cache-size = <0x8000>; 121d548c217SVabhav Sharma d-cache-line-size = <64>; 122d548c217SVabhav Sharma d-cache-sets = <128>; 123d548c217SVabhav Sharma i-cache-size = <0xC000>; 124d548c217SVabhav Sharma i-cache-line-size = <64>; 125d548c217SVabhav Sharma i-cache-sets = <192>; 126d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 12707159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1285363eaaeSYuantian Tang #cooling-cells = <2>; 129d548c217SVabhav Sharma }; 130d548c217SVabhav Sharma 1315363eaaeSYuantian Tang cpu300: cpu@300 { 132d548c217SVabhav Sharma device_type = "cpu"; 133d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 134d548c217SVabhav Sharma enable-method = "psci"; 135d548c217SVabhav Sharma reg = <0x300>; 1368e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137d548c217SVabhav Sharma d-cache-size = <0x8000>; 138d548c217SVabhav Sharma d-cache-line-size = <64>; 139d548c217SVabhav Sharma d-cache-sets = <128>; 140d548c217SVabhav Sharma i-cache-size = <0xC000>; 141d548c217SVabhav Sharma i-cache-line-size = <64>; 142d548c217SVabhav Sharma i-cache-sets = <192>; 143d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 14407159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1455363eaaeSYuantian Tang #cooling-cells = <2>; 146d548c217SVabhav Sharma }; 147d548c217SVabhav Sharma 1485363eaaeSYuantian Tang cpu301: cpu@301 { 149d548c217SVabhav Sharma device_type = "cpu"; 150d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 151d548c217SVabhav Sharma enable-method = "psci"; 152d548c217SVabhav Sharma reg = <0x301>; 1538e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154d548c217SVabhav Sharma d-cache-size = <0x8000>; 155d548c217SVabhav Sharma d-cache-line-size = <64>; 156d548c217SVabhav Sharma d-cache-sets = <128>; 157d548c217SVabhav Sharma i-cache-size = <0xC000>; 158d548c217SVabhav Sharma i-cache-line-size = <64>; 159d548c217SVabhav Sharma i-cache-sets = <192>; 160d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 16107159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1625363eaaeSYuantian Tang #cooling-cells = <2>; 163d548c217SVabhav Sharma }; 164d548c217SVabhav Sharma 1655363eaaeSYuantian Tang cpu400: cpu@400 { 166d548c217SVabhav Sharma device_type = "cpu"; 167d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 168d548c217SVabhav Sharma enable-method = "psci"; 169d548c217SVabhav Sharma reg = <0x400>; 1708e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171d548c217SVabhav Sharma d-cache-size = <0x8000>; 172d548c217SVabhav Sharma d-cache-line-size = <64>; 173d548c217SVabhav Sharma d-cache-sets = <128>; 174d548c217SVabhav Sharma i-cache-size = <0xC000>; 175d548c217SVabhav Sharma i-cache-line-size = <64>; 176d548c217SVabhav Sharma i-cache-sets = <192>; 177d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 17807159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1795363eaaeSYuantian Tang #cooling-cells = <2>; 180d548c217SVabhav Sharma }; 181d548c217SVabhav Sharma 1825363eaaeSYuantian Tang cpu401: cpu@401 { 183d548c217SVabhav Sharma device_type = "cpu"; 184d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 185d548c217SVabhav Sharma enable-method = "psci"; 186d548c217SVabhav Sharma reg = <0x401>; 1878e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188d548c217SVabhav Sharma d-cache-size = <0x8000>; 189d548c217SVabhav Sharma d-cache-line-size = <64>; 190d548c217SVabhav Sharma d-cache-sets = <128>; 191d548c217SVabhav Sharma i-cache-size = <0xC000>; 192d548c217SVabhav Sharma i-cache-line-size = <64>; 193d548c217SVabhav Sharma i-cache-sets = <192>; 194d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 19507159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1965363eaaeSYuantian Tang #cooling-cells = <2>; 197d548c217SVabhav Sharma }; 198d548c217SVabhav Sharma 1995363eaaeSYuantian Tang cpu500: cpu@500 { 200d548c217SVabhav Sharma device_type = "cpu"; 201d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 202d548c217SVabhav Sharma enable-method = "psci"; 203d548c217SVabhav Sharma reg = <0x500>; 2048e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205d548c217SVabhav Sharma d-cache-size = <0x8000>; 206d548c217SVabhav Sharma d-cache-line-size = <64>; 207d548c217SVabhav Sharma d-cache-sets = <128>; 208d548c217SVabhav Sharma i-cache-size = <0xC000>; 209d548c217SVabhav Sharma i-cache-line-size = <64>; 210d548c217SVabhav Sharma i-cache-sets = <192>; 211d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 21207159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2135363eaaeSYuantian Tang #cooling-cells = <2>; 214d548c217SVabhav Sharma }; 215d548c217SVabhav Sharma 2165363eaaeSYuantian Tang cpu501: cpu@501 { 217d548c217SVabhav Sharma device_type = "cpu"; 218d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 219d548c217SVabhav Sharma enable-method = "psci"; 220d548c217SVabhav Sharma reg = <0x501>; 2218e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222d548c217SVabhav Sharma d-cache-size = <0x8000>; 223d548c217SVabhav Sharma d-cache-line-size = <64>; 224d548c217SVabhav Sharma d-cache-sets = <128>; 225d548c217SVabhav Sharma i-cache-size = <0xC000>; 226d548c217SVabhav Sharma i-cache-line-size = <64>; 227d548c217SVabhav Sharma i-cache-sets = <192>; 228d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 22907159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2305363eaaeSYuantian Tang #cooling-cells = <2>; 231d548c217SVabhav Sharma }; 232d548c217SVabhav Sharma 2335363eaaeSYuantian Tang cpu600: cpu@600 { 234d548c217SVabhav Sharma device_type = "cpu"; 235d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 236d548c217SVabhav Sharma enable-method = "psci"; 237d548c217SVabhav Sharma reg = <0x600>; 2388e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239d548c217SVabhav Sharma d-cache-size = <0x8000>; 240d548c217SVabhav Sharma d-cache-line-size = <64>; 241d548c217SVabhav Sharma d-cache-sets = <128>; 242d548c217SVabhav Sharma i-cache-size = <0xC000>; 243d548c217SVabhav Sharma i-cache-line-size = <64>; 244d548c217SVabhav Sharma i-cache-sets = <192>; 245d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 24607159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2475363eaaeSYuantian Tang #cooling-cells = <2>; 248d548c217SVabhav Sharma }; 249d548c217SVabhav Sharma 2505363eaaeSYuantian Tang cpu601: cpu@601 { 251d548c217SVabhav Sharma device_type = "cpu"; 252d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 253d548c217SVabhav Sharma enable-method = "psci"; 254d548c217SVabhav Sharma reg = <0x601>; 2558e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256d548c217SVabhav Sharma d-cache-size = <0x8000>; 257d548c217SVabhav Sharma d-cache-line-size = <64>; 258d548c217SVabhav Sharma d-cache-sets = <128>; 259d548c217SVabhav Sharma i-cache-size = <0xC000>; 260d548c217SVabhav Sharma i-cache-line-size = <64>; 261d548c217SVabhav Sharma i-cache-sets = <192>; 262d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 26307159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2645363eaaeSYuantian Tang #cooling-cells = <2>; 265d548c217SVabhav Sharma }; 266d548c217SVabhav Sharma 2675363eaaeSYuantian Tang cpu700: cpu@700 { 268d548c217SVabhav Sharma device_type = "cpu"; 269d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 270d548c217SVabhav Sharma enable-method = "psci"; 271d548c217SVabhav Sharma reg = <0x700>; 2728e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273d548c217SVabhav Sharma d-cache-size = <0x8000>; 274d548c217SVabhav Sharma d-cache-line-size = <64>; 275d548c217SVabhav Sharma d-cache-sets = <128>; 276d548c217SVabhav Sharma i-cache-size = <0xC000>; 277d548c217SVabhav Sharma i-cache-line-size = <64>; 278d548c217SVabhav Sharma i-cache-sets = <192>; 279d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 28007159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2815363eaaeSYuantian Tang #cooling-cells = <2>; 282d548c217SVabhav Sharma }; 283d548c217SVabhav Sharma 2845363eaaeSYuantian Tang cpu701: cpu@701 { 285d548c217SVabhav Sharma device_type = "cpu"; 286d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 287d548c217SVabhav Sharma enable-method = "psci"; 288d548c217SVabhav Sharma reg = <0x701>; 2898e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290d548c217SVabhav Sharma d-cache-size = <0x8000>; 291d548c217SVabhav Sharma d-cache-line-size = <64>; 292d548c217SVabhav Sharma d-cache-sets = <128>; 293d548c217SVabhav Sharma i-cache-size = <0xC000>; 294d548c217SVabhav Sharma i-cache-line-size = <64>; 295d548c217SVabhav Sharma i-cache-sets = <192>; 296d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 29707159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2985363eaaeSYuantian Tang #cooling-cells = <2>; 299d548c217SVabhav Sharma }; 300d548c217SVabhav Sharma 301d548c217SVabhav Sharma cluster0_l2: l2-cache0 { 302d548c217SVabhav Sharma compatible = "cache"; 303d548c217SVabhav Sharma cache-size = <0x100000>; 304d548c217SVabhav Sharma cache-line-size = <64>; 305d548c217SVabhav Sharma cache-sets = <1024>; 306d548c217SVabhav Sharma cache-level = <2>; 307d548c217SVabhav Sharma }; 308d548c217SVabhav Sharma 309d548c217SVabhav Sharma cluster1_l2: l2-cache1 { 310d548c217SVabhav Sharma compatible = "cache"; 311d548c217SVabhav Sharma cache-size = <0x100000>; 312d548c217SVabhav Sharma cache-line-size = <64>; 313d548c217SVabhav Sharma cache-sets = <1024>; 314d548c217SVabhav Sharma cache-level = <2>; 315d548c217SVabhav Sharma }; 316d548c217SVabhav Sharma 317d548c217SVabhav Sharma cluster2_l2: l2-cache2 { 318d548c217SVabhav Sharma compatible = "cache"; 319d548c217SVabhav Sharma cache-size = <0x100000>; 320d548c217SVabhav Sharma cache-line-size = <64>; 321d548c217SVabhav Sharma cache-sets = <1024>; 322d548c217SVabhav Sharma cache-level = <2>; 323d548c217SVabhav Sharma }; 324d548c217SVabhav Sharma 325d548c217SVabhav Sharma cluster3_l2: l2-cache3 { 326d548c217SVabhav Sharma compatible = "cache"; 327d548c217SVabhav Sharma cache-size = <0x100000>; 328d548c217SVabhav Sharma cache-line-size = <64>; 329d548c217SVabhav Sharma cache-sets = <1024>; 330d548c217SVabhav Sharma cache-level = <2>; 331d548c217SVabhav Sharma }; 332d548c217SVabhav Sharma 333d548c217SVabhav Sharma cluster4_l2: l2-cache4 { 334d548c217SVabhav Sharma compatible = "cache"; 335d548c217SVabhav Sharma cache-size = <0x100000>; 336d548c217SVabhav Sharma cache-line-size = <64>; 337d548c217SVabhav Sharma cache-sets = <1024>; 338d548c217SVabhav Sharma cache-level = <2>; 339d548c217SVabhav Sharma }; 340d548c217SVabhav Sharma 341d548c217SVabhav Sharma cluster5_l2: l2-cache5 { 342d548c217SVabhav Sharma compatible = "cache"; 343d548c217SVabhav Sharma cache-size = <0x100000>; 344d548c217SVabhav Sharma cache-line-size = <64>; 345d548c217SVabhav Sharma cache-sets = <1024>; 346d548c217SVabhav Sharma cache-level = <2>; 347d548c217SVabhav Sharma }; 348d548c217SVabhav Sharma 349d548c217SVabhav Sharma cluster6_l2: l2-cache6 { 350d548c217SVabhav Sharma compatible = "cache"; 351d548c217SVabhav Sharma cache-size = <0x100000>; 352d548c217SVabhav Sharma cache-line-size = <64>; 353d548c217SVabhav Sharma cache-sets = <1024>; 354d548c217SVabhav Sharma cache-level = <2>; 355d548c217SVabhav Sharma }; 356d548c217SVabhav Sharma 357d548c217SVabhav Sharma cluster7_l2: l2-cache7 { 358d548c217SVabhav Sharma compatible = "cache"; 359d548c217SVabhav Sharma cache-size = <0x100000>; 360d548c217SVabhav Sharma cache-line-size = <64>; 361d548c217SVabhav Sharma cache-sets = <1024>; 362d548c217SVabhav Sharma cache-level = <2>; 363d548c217SVabhav Sharma }; 36400c5ce8aSRan Wang 36507159f67SRan Wang cpu_pw15: cpu-pw15 { 36600c5ce8aSRan Wang compatible = "arm,idle-state"; 36707159f67SRan Wang idle-state-name = "PW15"; 36800c5ce8aSRan Wang arm,psci-suspend-param = <0x0>; 36900c5ce8aSRan Wang entry-latency-us = <2000>; 37000c5ce8aSRan Wang exit-latency-us = <2000>; 37100c5ce8aSRan Wang min-residency-us = <6000>; 37200c5ce8aSRan Wang }; 373d548c217SVabhav Sharma }; 374d548c217SVabhav Sharma 375d548c217SVabhav Sharma gic: interrupt-controller@6000000 { 376d548c217SVabhav Sharma compatible = "arm,gic-v3"; 377d548c217SVabhav Sharma reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 378d548c217SVabhav Sharma <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 379d548c217SVabhav Sharma // SGI_base) 380d548c217SVabhav Sharma <0x0 0x0c0c0000 0 0x2000>, // GICC 381d548c217SVabhav Sharma <0x0 0x0c0d0000 0 0x1000>, // GICH 382d548c217SVabhav Sharma <0x0 0x0c0e0000 0 0x20000>; // GICV 383d548c217SVabhav Sharma #interrupt-cells = <3>; 384d548c217SVabhav Sharma #address-cells = <2>; 385d548c217SVabhav Sharma #size-cells = <2>; 386d548c217SVabhav Sharma ranges; 387d548c217SVabhav Sharma interrupt-controller; 388d548c217SVabhav Sharma interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 389d548c217SVabhav Sharma 390d548c217SVabhav Sharma its: gic-its@6020000 { 391d548c217SVabhav Sharma compatible = "arm,gic-v3-its"; 392d548c217SVabhav Sharma msi-controller; 393d548c217SVabhav Sharma reg = <0x0 0x6020000 0 0x20000>; 394d548c217SVabhav Sharma }; 395d548c217SVabhav Sharma }; 396d548c217SVabhav Sharma 397d548c217SVabhav Sharma timer { 398d548c217SVabhav Sharma compatible = "arm,armv8-timer"; 399d548c217SVabhav Sharma interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 400d548c217SVabhav Sharma <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 401d548c217SVabhav Sharma <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 402d548c217SVabhav Sharma <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 403d548c217SVabhav Sharma }; 404d548c217SVabhav Sharma 405d548c217SVabhav Sharma pmu { 406d548c217SVabhav Sharma compatible = "arm,cortex-a72-pmu"; 407d548c217SVabhav Sharma interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 408d548c217SVabhav Sharma }; 409d548c217SVabhav Sharma 410d548c217SVabhav Sharma psci { 411d548c217SVabhav Sharma compatible = "arm,psci-0.2"; 412d548c217SVabhav Sharma method = "smc"; 413d548c217SVabhav Sharma }; 414d548c217SVabhav Sharma 415d548c217SVabhav Sharma memory@80000000 { 416d548c217SVabhav Sharma // DRAM space - 1, size : 2 GB DRAM 417d548c217SVabhav Sharma device_type = "memory"; 418d548c217SVabhav Sharma reg = <0x00000000 0x80000000 0 0x80000000>; 419d548c217SVabhav Sharma }; 420d548c217SVabhav Sharma 421d548c217SVabhav Sharma ddr1: memory-controller@1080000 { 422d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 423d548c217SVabhav Sharma reg = <0x0 0x1080000 0x0 0x1000>; 424d548c217SVabhav Sharma interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 425d548c217SVabhav Sharma little-endian; 426d548c217SVabhav Sharma }; 427d548c217SVabhav Sharma 428d548c217SVabhav Sharma ddr2: memory-controller@1090000 { 429d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 430d548c217SVabhav Sharma reg = <0x0 0x1090000 0x0 0x1000>; 431d548c217SVabhav Sharma interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 432d548c217SVabhav Sharma little-endian; 433d548c217SVabhav Sharma }; 434d548c217SVabhav Sharma 435d548c217SVabhav Sharma // One clock unit-sysclk node which bootloader require during DT fix-up 436d548c217SVabhav Sharma sysclk: sysclk { 437d548c217SVabhav Sharma compatible = "fixed-clock"; 438d548c217SVabhav Sharma #clock-cells = <0>; 439d548c217SVabhav Sharma clock-frequency = <100000000>; // fixed up by bootloader 440d548c217SVabhav Sharma clock-output-names = "sysclk"; 441d548c217SVabhav Sharma }; 442d548c217SVabhav Sharma 4435363eaaeSYuantian Tang thermal-zones { 444ac082ea8SYuantian Tang cluster6-7 { 4455363eaaeSYuantian Tang polling-delay-passive = <1000>; 4465363eaaeSYuantian Tang polling-delay = <5000>; 4475363eaaeSYuantian Tang thermal-sensors = <&tmu 0>; 4485363eaaeSYuantian Tang 4495363eaaeSYuantian Tang trips { 450ac082ea8SYuantian Tang cluster6_7_alert: cluster6-7-alert { 4515363eaaeSYuantian Tang temperature = <85000>; 4525363eaaeSYuantian Tang hysteresis = <2000>; 4535363eaaeSYuantian Tang type = "passive"; 4545363eaaeSYuantian Tang }; 4555363eaaeSYuantian Tang 456ac082ea8SYuantian Tang cluster6_7_crit: cluster6-7-crit { 4575363eaaeSYuantian Tang temperature = <95000>; 4585363eaaeSYuantian Tang hysteresis = <2000>; 4595363eaaeSYuantian Tang type = "critical"; 4605363eaaeSYuantian Tang }; 4615363eaaeSYuantian Tang }; 4625363eaaeSYuantian Tang 4635363eaaeSYuantian Tang cooling-maps { 4645363eaaeSYuantian Tang map0 { 465ac082ea8SYuantian Tang trip = <&cluster6_7_alert>; 4665363eaaeSYuantian Tang cooling-device = 4675363eaaeSYuantian Tang <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685363eaaeSYuantian Tang <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4695363eaaeSYuantian Tang <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4705363eaaeSYuantian Tang <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4715363eaaeSYuantian Tang <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725363eaaeSYuantian Tang <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4735363eaaeSYuantian Tang <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4745363eaaeSYuantian Tang <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4755363eaaeSYuantian Tang <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765363eaaeSYuantian Tang <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775363eaaeSYuantian Tang <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4785363eaaeSYuantian Tang <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4795363eaaeSYuantian Tang <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4805363eaaeSYuantian Tang <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815363eaaeSYuantian Tang <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4825363eaaeSYuantian Tang <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4835363eaaeSYuantian Tang }; 4845363eaaeSYuantian Tang }; 4855363eaaeSYuantian Tang }; 486ac082ea8SYuantian Tang 487ac082ea8SYuantian Tang ddr-cluster5 { 488ac082ea8SYuantian Tang polling-delay-passive = <1000>; 489ac082ea8SYuantian Tang polling-delay = <5000>; 490ac082ea8SYuantian Tang thermal-sensors = <&tmu 1>; 491ac082ea8SYuantian Tang 492ac082ea8SYuantian Tang trips { 493ac082ea8SYuantian Tang ddr-cluster5-alert { 494ac082ea8SYuantian Tang temperature = <85000>; 495ac082ea8SYuantian Tang hysteresis = <2000>; 496ac082ea8SYuantian Tang type = "passive"; 497ac082ea8SYuantian Tang }; 498ac082ea8SYuantian Tang 499ac082ea8SYuantian Tang ddr-cluster5-crit { 500ac082ea8SYuantian Tang temperature = <95000>; 501ac082ea8SYuantian Tang hysteresis = <2000>; 502ac082ea8SYuantian Tang type = "critical"; 503ac082ea8SYuantian Tang }; 504ac082ea8SYuantian Tang }; 505ac082ea8SYuantian Tang }; 506ac082ea8SYuantian Tang 507ac082ea8SYuantian Tang wriop { 508ac082ea8SYuantian Tang polling-delay-passive = <1000>; 509ac082ea8SYuantian Tang polling-delay = <5000>; 510ac082ea8SYuantian Tang thermal-sensors = <&tmu 2>; 511ac082ea8SYuantian Tang 512ac082ea8SYuantian Tang trips { 513ac082ea8SYuantian Tang wriop-alert { 514ac082ea8SYuantian Tang temperature = <85000>; 515ac082ea8SYuantian Tang hysteresis = <2000>; 516ac082ea8SYuantian Tang type = "passive"; 517ac082ea8SYuantian Tang }; 518ac082ea8SYuantian Tang 519ac082ea8SYuantian Tang wriop-crit { 520ac082ea8SYuantian Tang temperature = <95000>; 521ac082ea8SYuantian Tang hysteresis = <2000>; 522ac082ea8SYuantian Tang type = "critical"; 523ac082ea8SYuantian Tang }; 524ac082ea8SYuantian Tang }; 525ac082ea8SYuantian Tang }; 526ac082ea8SYuantian Tang 527ac082ea8SYuantian Tang dce-qbman-hsio2 { 528ac082ea8SYuantian Tang polling-delay-passive = <1000>; 529ac082ea8SYuantian Tang polling-delay = <5000>; 530ac082ea8SYuantian Tang thermal-sensors = <&tmu 3>; 531ac082ea8SYuantian Tang 532ac082ea8SYuantian Tang trips { 533ac082ea8SYuantian Tang dce-qbman-alert { 534ac082ea8SYuantian Tang temperature = <85000>; 535ac082ea8SYuantian Tang hysteresis = <2000>; 536ac082ea8SYuantian Tang type = "passive"; 537ac082ea8SYuantian Tang }; 538ac082ea8SYuantian Tang 539ac082ea8SYuantian Tang dce-qbman-crit { 540ac082ea8SYuantian Tang temperature = <95000>; 541ac082ea8SYuantian Tang hysteresis = <2000>; 542ac082ea8SYuantian Tang type = "critical"; 543ac082ea8SYuantian Tang }; 544ac082ea8SYuantian Tang }; 545ac082ea8SYuantian Tang }; 546ac082ea8SYuantian Tang 547ac082ea8SYuantian Tang ccn-dpaa-tbu { 548ac082ea8SYuantian Tang polling-delay-passive = <1000>; 549ac082ea8SYuantian Tang polling-delay = <5000>; 550ac082ea8SYuantian Tang thermal-sensors = <&tmu 4>; 551ac082ea8SYuantian Tang 552ac082ea8SYuantian Tang trips { 553ac082ea8SYuantian Tang ccn-dpaa-alert { 554ac082ea8SYuantian Tang temperature = <85000>; 555ac082ea8SYuantian Tang hysteresis = <2000>; 556ac082ea8SYuantian Tang type = "passive"; 557ac082ea8SYuantian Tang }; 558ac082ea8SYuantian Tang 559ac082ea8SYuantian Tang ccn-dpaa-crit { 560ac082ea8SYuantian Tang temperature = <95000>; 561ac082ea8SYuantian Tang hysteresis = <2000>; 562ac082ea8SYuantian Tang type = "critical"; 563ac082ea8SYuantian Tang }; 564ac082ea8SYuantian Tang }; 565ac082ea8SYuantian Tang }; 566ac082ea8SYuantian Tang 567ac082ea8SYuantian Tang cluster4-hsio3 { 568ac082ea8SYuantian Tang polling-delay-passive = <1000>; 569ac082ea8SYuantian Tang polling-delay = <5000>; 570ac082ea8SYuantian Tang thermal-sensors = <&tmu 5>; 571ac082ea8SYuantian Tang 572ac082ea8SYuantian Tang trips { 573ac082ea8SYuantian Tang clust4-hsio3-alert { 574ac082ea8SYuantian Tang temperature = <85000>; 575ac082ea8SYuantian Tang hysteresis = <2000>; 576ac082ea8SYuantian Tang type = "passive"; 577ac082ea8SYuantian Tang }; 578ac082ea8SYuantian Tang 579ac082ea8SYuantian Tang clust4-hsio3-crit { 580ac082ea8SYuantian Tang temperature = <95000>; 581ac082ea8SYuantian Tang hysteresis = <2000>; 582ac082ea8SYuantian Tang type = "critical"; 583ac082ea8SYuantian Tang }; 584ac082ea8SYuantian Tang }; 585ac082ea8SYuantian Tang }; 586ac082ea8SYuantian Tang 587ac082ea8SYuantian Tang cluster2-3 { 588ac082ea8SYuantian Tang polling-delay-passive = <1000>; 589ac082ea8SYuantian Tang polling-delay = <5000>; 590ac082ea8SYuantian Tang thermal-sensors = <&tmu 6>; 591ac082ea8SYuantian Tang 592ac082ea8SYuantian Tang trips { 593ac082ea8SYuantian Tang cluster2-3-alert { 594ac082ea8SYuantian Tang temperature = <85000>; 595ac082ea8SYuantian Tang hysteresis = <2000>; 596ac082ea8SYuantian Tang type = "passive"; 597ac082ea8SYuantian Tang }; 598ac082ea8SYuantian Tang 599ac082ea8SYuantian Tang cluster2-3-crit { 600ac082ea8SYuantian Tang temperature = <95000>; 601ac082ea8SYuantian Tang hysteresis = <2000>; 602ac082ea8SYuantian Tang type = "critical"; 603ac082ea8SYuantian Tang }; 604ac082ea8SYuantian Tang }; 605ac082ea8SYuantian Tang }; 6065363eaaeSYuantian Tang }; 6075363eaaeSYuantian Tang 608d548c217SVabhav Sharma soc { 609d548c217SVabhav Sharma compatible = "simple-bus"; 610d548c217SVabhav Sharma #address-cells = <2>; 611d548c217SVabhav Sharma #size-cells = <2>; 612d548c217SVabhav Sharma ranges; 6130154878dSIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 614d548c217SVabhav Sharma 6153cbe93a1SIoana Ciornei serdes_1: phy@1ea0000 { 6163cbe93a1SIoana Ciornei compatible = "fsl,lynx-28g"; 6173cbe93a1SIoana Ciornei reg = <0x0 0x1ea0000 0x0 0x1e30>; 6183cbe93a1SIoana Ciornei #phy-cells = <1>; 6193cbe93a1SIoana Ciornei }; 6203cbe93a1SIoana Ciornei 621d548c217SVabhav Sharma crypto: crypto@8000000 { 622d548c217SVabhav Sharma compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 623d548c217SVabhav Sharma fsl,sec-era = <10>; 624d548c217SVabhav Sharma #address-cells = <1>; 625d548c217SVabhav Sharma #size-cells = <1>; 626d548c217SVabhav Sharma ranges = <0x0 0x00 0x8000000 0x100000>; 627d548c217SVabhav Sharma reg = <0x00 0x8000000 0x0 0x100000>; 628d548c217SVabhav Sharma interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 629d548c217SVabhav Sharma dma-coherent; 630d548c217SVabhav Sharma status = "disabled"; 631d548c217SVabhav Sharma 632d548c217SVabhav Sharma sec_jr0: jr@10000 { 633d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 634d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 635d548c217SVabhav Sharma reg = <0x10000 0x10000>; 636d548c217SVabhav Sharma interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 637d548c217SVabhav Sharma }; 638d548c217SVabhav Sharma 639d548c217SVabhav Sharma sec_jr1: jr@20000 { 640d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 641d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 642d548c217SVabhav Sharma reg = <0x20000 0x10000>; 643d548c217SVabhav Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 644d548c217SVabhav Sharma }; 645d548c217SVabhav Sharma 646d548c217SVabhav Sharma sec_jr2: jr@30000 { 647d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 648d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 649d548c217SVabhav Sharma reg = <0x30000 0x10000>; 650d548c217SVabhav Sharma interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 651d548c217SVabhav Sharma }; 652d548c217SVabhav Sharma 653d548c217SVabhav Sharma sec_jr3: jr@40000 { 654d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 655d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 656d548c217SVabhav Sharma reg = <0x40000 0x10000>; 657d548c217SVabhav Sharma interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 658d548c217SVabhav Sharma }; 659d548c217SVabhav Sharma }; 660d548c217SVabhav Sharma 661d548c217SVabhav Sharma clockgen: clock-controller@1300000 { 662d548c217SVabhav Sharma compatible = "fsl,lx2160a-clockgen"; 663d548c217SVabhav Sharma reg = <0 0x1300000 0 0xa0000>; 664d548c217SVabhav Sharma #clock-cells = <2>; 665d548c217SVabhav Sharma clocks = <&sysclk>; 666d548c217SVabhav Sharma }; 667d548c217SVabhav Sharma 668d548c217SVabhav Sharma dcfg: syscon@1e00000 { 669d548c217SVabhav Sharma compatible = "fsl,lx2160a-dcfg", "syscon"; 670d548c217SVabhav Sharma reg = <0x0 0x1e00000 0x0 0x10000>; 671d548c217SVabhav Sharma little-endian; 672d548c217SVabhav Sharma }; 673d548c217SVabhav Sharma 674*e0f6d9ebSSean Anderson sfp: efuse@1e80000 { 675*e0f6d9ebSSean Anderson compatible = "fsl,ls1028a-sfp"; 676*e0f6d9ebSSean Anderson reg = <0x0 0x1e80000 0x0 0x10000>; 677*e0f6d9ebSSean Anderson clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 678*e0f6d9ebSSean Anderson QORIQ_CLK_PLL_DIV(4)>; 679*e0f6d9ebSSean Anderson clock-names = "sfp"; 680*e0f6d9ebSSean Anderson }; 681*e0f6d9ebSSean Anderson 682332b6a79SBiwen Li isc: syscon@1f70000 { 683332b6a79SBiwen Li compatible = "fsl,lx2160a-isc", "syscon"; 684332b6a79SBiwen Li reg = <0x0 0x1f70000 0x0 0x10000>; 685332b6a79SBiwen Li little-endian; 686332b6a79SBiwen Li #address-cells = <1>; 687332b6a79SBiwen Li #size-cells = <1>; 688332b6a79SBiwen Li ranges = <0x0 0x0 0x1f70000 0x10000>; 689332b6a79SBiwen Li 690332b6a79SBiwen Li extirq: interrupt-controller@14 { 691332b6a79SBiwen Li compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 692332b6a79SBiwen Li #interrupt-cells = <2>; 693332b6a79SBiwen Li #address-cells = <0>; 694332b6a79SBiwen Li interrupt-controller; 695332b6a79SBiwen Li reg = <0x14 4>; 696332b6a79SBiwen Li interrupt-map = 6971447c635SVladimir Oltean <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 6981447c635SVladimir Oltean <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 6991447c635SVladimir Oltean <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 7001447c635SVladimir Oltean <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7011447c635SVladimir Oltean <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7021447c635SVladimir Oltean <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 7031447c635SVladimir Oltean <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 7041447c635SVladimir Oltean <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 7051447c635SVladimir Oltean <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7061447c635SVladimir Oltean <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 7071447c635SVladimir Oltean <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 7081447c635SVladimir Oltean <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 709339c8beaSMichael Walle interrupt-map-mask = <0xf 0x0>; 710332b6a79SBiwen Li }; 711332b6a79SBiwen Li }; 712332b6a79SBiwen Li 7135363eaaeSYuantian Tang tmu: tmu@1f80000 { 7145363eaaeSYuantian Tang compatible = "fsl,qoriq-tmu"; 7155363eaaeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 7165363eaaeSYuantian Tang interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 7175363eaaeSYuantian Tang fsl,tmu-range = <0x800000e6 0x8001017d>; 7185363eaaeSYuantian Tang fsl,tmu-calibration = 7195363eaaeSYuantian Tang /* Calibration data group 1 */ 7205363eaaeSYuantian Tang <0x00000000 0x00000035 7215363eaaeSYuantian Tang /* Calibration data group 2 */ 722ac082ea8SYuantian Tang 0x00000001 0x00000154>; 7235363eaaeSYuantian Tang little-endian; 7245363eaaeSYuantian Tang #thermal-sensor-cells = <1>; 7255363eaaeSYuantian Tang }; 7265363eaaeSYuantian Tang 727d548c217SVabhav Sharma i2c0: i2c@2000000 { 728d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 729d548c217SVabhav Sharma #address-cells = <1>; 730d548c217SVabhav Sharma #size-cells = <0>; 731d548c217SVabhav Sharma reg = <0x0 0x2000000 0x0 0x10000>; 732d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 733d548c217SVabhav Sharma clock-names = "i2c"; 7348e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7358e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 736849e087bSZhang Ying-22455 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 737d548c217SVabhav Sharma status = "disabled"; 738d548c217SVabhav Sharma }; 739d548c217SVabhav Sharma 740d548c217SVabhav Sharma i2c1: i2c@2010000 { 741d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 742d548c217SVabhav Sharma #address-cells = <1>; 743d548c217SVabhav Sharma #size-cells = <0>; 744d548c217SVabhav Sharma reg = <0x0 0x2010000 0x0 0x10000>; 745d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 746d548c217SVabhav Sharma clock-names = "i2c"; 7478e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7488e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 749d548c217SVabhav Sharma status = "disabled"; 750d548c217SVabhav Sharma }; 751d548c217SVabhav Sharma 752d548c217SVabhav Sharma i2c2: i2c@2020000 { 753d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 754d548c217SVabhav Sharma #address-cells = <1>; 755d548c217SVabhav Sharma #size-cells = <0>; 756d548c217SVabhav Sharma reg = <0x0 0x2020000 0x0 0x10000>; 757d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 758d548c217SVabhav Sharma clock-names = "i2c"; 7598e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7608e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 761d548c217SVabhav Sharma status = "disabled"; 762d548c217SVabhav Sharma }; 763d548c217SVabhav Sharma 764d548c217SVabhav Sharma i2c3: i2c@2030000 { 765d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 766d548c217SVabhav Sharma #address-cells = <1>; 767d548c217SVabhav Sharma #size-cells = <0>; 768d548c217SVabhav Sharma reg = <0x0 0x2030000 0x0 0x10000>; 769d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 770d548c217SVabhav Sharma clock-names = "i2c"; 7718e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7728e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 773d548c217SVabhav Sharma status = "disabled"; 774d548c217SVabhav Sharma }; 775d548c217SVabhav Sharma 776d548c217SVabhav Sharma i2c4: i2c@2040000 { 777d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 778d548c217SVabhav Sharma #address-cells = <1>; 779d548c217SVabhav Sharma #size-cells = <0>; 780d548c217SVabhav Sharma reg = <0x0 0x2040000 0x0 0x10000>; 781d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 782d548c217SVabhav Sharma clock-names = "i2c"; 7838e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7848e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 785849e087bSZhang Ying-22455 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 786d548c217SVabhav Sharma status = "disabled"; 787d548c217SVabhav Sharma }; 788d548c217SVabhav Sharma 789d548c217SVabhav Sharma i2c5: i2c@2050000 { 790d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 791d548c217SVabhav Sharma #address-cells = <1>; 792d548c217SVabhav Sharma #size-cells = <0>; 793d548c217SVabhav Sharma reg = <0x0 0x2050000 0x0 0x10000>; 794d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 795d548c217SVabhav Sharma clock-names = "i2c"; 7968e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 7978e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 798d548c217SVabhav Sharma status = "disabled"; 799d548c217SVabhav Sharma }; 800d548c217SVabhav Sharma 801d548c217SVabhav Sharma i2c6: i2c@2060000 { 802d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 803d548c217SVabhav Sharma #address-cells = <1>; 804d548c217SVabhav Sharma #size-cells = <0>; 805d548c217SVabhav Sharma reg = <0x0 0x2060000 0x0 0x10000>; 806d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 807d548c217SVabhav Sharma clock-names = "i2c"; 8088e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8098e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 810d548c217SVabhav Sharma status = "disabled"; 811d548c217SVabhav Sharma }; 812d548c217SVabhav Sharma 813d548c217SVabhav Sharma i2c7: i2c@2070000 { 814d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 815d548c217SVabhav Sharma #address-cells = <1>; 816d548c217SVabhav Sharma #size-cells = <0>; 817d548c217SVabhav Sharma reg = <0x0 0x2070000 0x0 0x10000>; 818d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 819d548c217SVabhav Sharma clock-names = "i2c"; 8208e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8218e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 822d548c217SVabhav Sharma status = "disabled"; 823d548c217SVabhav Sharma }; 824d548c217SVabhav Sharma 8251ffeef4eSYogesh Narayan Gaur fspi: spi@20c0000 { 8261ffeef4eSYogesh Narayan Gaur compatible = "nxp,lx2160a-fspi"; 8271ffeef4eSYogesh Narayan Gaur #address-cells = <1>; 8281ffeef4eSYogesh Narayan Gaur #size-cells = <0>; 8291ffeef4eSYogesh Narayan Gaur reg = <0x0 0x20c0000 0x0 0x10000>, 8301ffeef4eSYogesh Narayan Gaur <0x0 0x20000000 0x0 0x10000000>; 8311ffeef4eSYogesh Narayan Gaur reg-names = "fspi_base", "fspi_mmap"; 8321ffeef4eSYogesh Narayan Gaur interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 8338e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8348e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>, 8358e9f7797SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 8368e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 8371ffeef4eSYogesh Narayan Gaur clock-names = "fspi_en", "fspi"; 8381ffeef4eSYogesh Narayan Gaur status = "disabled"; 8391ffeef4eSYogesh Narayan Gaur }; 8401ffeef4eSYogesh Narayan Gaur 84183ebd4a5SChuanhua Han dspi0: spi@2100000 { 84283ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 84383ebd4a5SChuanhua Han #address-cells = <1>; 84483ebd4a5SChuanhua Han #size-cells = <0>; 84583ebd4a5SChuanhua Han reg = <0x0 0x2100000 0x0 0x10000>; 84683ebd4a5SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 8478e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8488e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 84983ebd4a5SChuanhua Han clock-names = "dspi"; 85083ebd4a5SChuanhua Han spi-num-chipselects = <5>; 85183ebd4a5SChuanhua Han bus-num = <0>; 85283ebd4a5SChuanhua Han status = "disabled"; 85383ebd4a5SChuanhua Han }; 85483ebd4a5SChuanhua Han 85583ebd4a5SChuanhua Han dspi1: spi@2110000 { 85683ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 85783ebd4a5SChuanhua Han #address-cells = <1>; 85883ebd4a5SChuanhua Han #size-cells = <0>; 85983ebd4a5SChuanhua Han reg = <0x0 0x2110000 0x0 0x10000>; 86083ebd4a5SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 8618e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8628e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 86383ebd4a5SChuanhua Han clock-names = "dspi"; 86483ebd4a5SChuanhua Han spi-num-chipselects = <5>; 86583ebd4a5SChuanhua Han bus-num = <1>; 86683ebd4a5SChuanhua Han status = "disabled"; 86783ebd4a5SChuanhua Han }; 86883ebd4a5SChuanhua Han 86983ebd4a5SChuanhua Han dspi2: spi@2120000 { 87083ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 87183ebd4a5SChuanhua Han #address-cells = <1>; 87283ebd4a5SChuanhua Han #size-cells = <0>; 87383ebd4a5SChuanhua Han reg = <0x0 0x2120000 0x0 0x10000>; 87483ebd4a5SChuanhua Han interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 8758e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8768e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 87783ebd4a5SChuanhua Han clock-names = "dspi"; 87883ebd4a5SChuanhua Han spi-num-chipselects = <5>; 87983ebd4a5SChuanhua Han bus-num = <2>; 88083ebd4a5SChuanhua Han status = "disabled"; 88183ebd4a5SChuanhua Han }; 88283ebd4a5SChuanhua Han 883d548c217SVabhav Sharma esdhc0: esdhc@2140000 { 884d548c217SVabhav Sharma compatible = "fsl,esdhc"; 885d548c217SVabhav Sharma reg = <0x0 0x2140000 0x0 0x10000>; 886d548c217SVabhav Sharma interrupts = <0 28 0x4>; /* Level high type */ 8878e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 8888e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 88962b4359cSRussell King dma-coherent; 890d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 891d548c217SVabhav Sharma sdhci,auto-cmd12; 892d548c217SVabhav Sharma little-endian; 893d548c217SVabhav Sharma bus-width = <4>; 894d548c217SVabhav Sharma status = "disabled"; 895d548c217SVabhav Sharma }; 896d548c217SVabhav Sharma 897d548c217SVabhav Sharma esdhc1: esdhc@2150000 { 898d548c217SVabhav Sharma compatible = "fsl,esdhc"; 899d548c217SVabhav Sharma reg = <0x0 0x2150000 0x0 0x10000>; 900d548c217SVabhav Sharma interrupts = <0 63 0x4>; /* Level high type */ 9018e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 9028e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 90362b4359cSRussell King dma-coherent; 904d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 905d548c217SVabhav Sharma sdhci,auto-cmd12; 906d548c217SVabhav Sharma broken-cd; 907d548c217SVabhav Sharma little-endian; 908d548c217SVabhav Sharma bus-width = <4>; 909d548c217SVabhav Sharma status = "disabled"; 910d548c217SVabhav Sharma }; 911d548c217SVabhav Sharma 912930a0968SKuldeep Singh can0: can@2180000 { 913930a0968SKuldeep Singh compatible = "fsl,lx2160ar1-flexcan"; 914930a0968SKuldeep Singh reg = <0x0 0x2180000 0x0 0x10000>; 915930a0968SKuldeep Singh interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 916930a0968SKuldeep Singh clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 917930a0968SKuldeep Singh QORIQ_CLK_PLL_DIV(8)>, 918930a0968SKuldeep Singh <&clockgen QORIQ_CLK_SYSCLK 0>; 919930a0968SKuldeep Singh clock-names = "ipg", "per"; 9207cbeeb05SKuldeep Singh fsl,clk-source = /bits/ 8 <0>; 921930a0968SKuldeep Singh status = "disabled"; 922930a0968SKuldeep Singh }; 923930a0968SKuldeep Singh 924930a0968SKuldeep Singh can1: can@2190000 { 925930a0968SKuldeep Singh compatible = "fsl,lx2160ar1-flexcan"; 926930a0968SKuldeep Singh reg = <0x0 0x2190000 0x0 0x10000>; 927930a0968SKuldeep Singh interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 928930a0968SKuldeep Singh clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 929930a0968SKuldeep Singh QORIQ_CLK_PLL_DIV(8)>, 930930a0968SKuldeep Singh <&clockgen QORIQ_CLK_SYSCLK 0>; 931930a0968SKuldeep Singh clock-names = "ipg", "per"; 9327cbeeb05SKuldeep Singh fsl,clk-source = /bits/ 8 <0>; 933930a0968SKuldeep Singh status = "disabled"; 934930a0968SKuldeep Singh }; 935930a0968SKuldeep Singh 936d548c217SVabhav Sharma uart0: serial@21c0000 { 937d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 938d548c217SVabhav Sharma reg = <0x0 0x21c0000 0x0 0x1000>; 939d548c217SVabhav Sharma interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 940d548c217SVabhav Sharma current-speed = <115200>; 941d548c217SVabhav Sharma status = "disabled"; 942d548c217SVabhav Sharma }; 943d548c217SVabhav Sharma 944d548c217SVabhav Sharma uart1: serial@21d0000 { 945d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 946d548c217SVabhav Sharma reg = <0x0 0x21d0000 0x0 0x1000>; 947d548c217SVabhav Sharma interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 948d548c217SVabhav Sharma current-speed = <115200>; 949d548c217SVabhav Sharma status = "disabled"; 950d548c217SVabhav Sharma }; 951d548c217SVabhav Sharma 952d548c217SVabhav Sharma uart2: serial@21e0000 { 953d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 954d548c217SVabhav Sharma reg = <0x0 0x21e0000 0x0 0x1000>; 955d548c217SVabhav Sharma interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 956d548c217SVabhav Sharma current-speed = <115200>; 957d548c217SVabhav Sharma status = "disabled"; 958d548c217SVabhav Sharma }; 959d548c217SVabhav Sharma 960d548c217SVabhav Sharma uart3: serial@21f0000 { 961d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 962d548c217SVabhav Sharma reg = <0x0 0x21f0000 0x0 0x1000>; 963d548c217SVabhav Sharma interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 964d548c217SVabhav Sharma current-speed = <115200>; 965d548c217SVabhav Sharma status = "disabled"; 966d548c217SVabhav Sharma }; 967d548c217SVabhav Sharma 968d548c217SVabhav Sharma gpio0: gpio@2300000 { 969d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 970d548c217SVabhav Sharma reg = <0x0 0x2300000 0x0 0x10000>; 971d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 972d548c217SVabhav Sharma gpio-controller; 973d548c217SVabhav Sharma little-endian; 974d548c217SVabhav Sharma #gpio-cells = <2>; 975d548c217SVabhav Sharma interrupt-controller; 976d548c217SVabhav Sharma #interrupt-cells = <2>; 977d548c217SVabhav Sharma }; 978d548c217SVabhav Sharma 979d548c217SVabhav Sharma gpio1: gpio@2310000 { 980d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 981d548c217SVabhav Sharma reg = <0x0 0x2310000 0x0 0x10000>; 982d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 983d548c217SVabhav Sharma gpio-controller; 984d548c217SVabhav Sharma little-endian; 985d548c217SVabhav Sharma #gpio-cells = <2>; 986d548c217SVabhav Sharma interrupt-controller; 987d548c217SVabhav Sharma #interrupt-cells = <2>; 988d548c217SVabhav Sharma }; 989d548c217SVabhav Sharma 990d548c217SVabhav Sharma gpio2: gpio@2320000 { 991d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 992d548c217SVabhav Sharma reg = <0x0 0x2320000 0x0 0x10000>; 993d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 994d548c217SVabhav Sharma gpio-controller; 995d548c217SVabhav Sharma little-endian; 996d548c217SVabhav Sharma #gpio-cells = <2>; 997d548c217SVabhav Sharma interrupt-controller; 998d548c217SVabhav Sharma #interrupt-cells = <2>; 999d548c217SVabhav Sharma }; 1000d548c217SVabhav Sharma 1001d548c217SVabhav Sharma gpio3: gpio@2330000 { 1002d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 1003d548c217SVabhav Sharma reg = <0x0 0x2330000 0x0 0x10000>; 1004d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1005d548c217SVabhav Sharma gpio-controller; 1006d548c217SVabhav Sharma little-endian; 1007d548c217SVabhav Sharma #gpio-cells = <2>; 1008d548c217SVabhav Sharma interrupt-controller; 1009d548c217SVabhav Sharma #interrupt-cells = <2>; 1010d548c217SVabhav Sharma }; 1011d548c217SVabhav Sharma 1012d548c217SVabhav Sharma watchdog@23a0000 { 1013d548c217SVabhav Sharma compatible = "arm,sbsa-gwdt"; 1014d548c217SVabhav Sharma reg = <0x0 0x23a0000 0 0x1000>, 1015d548c217SVabhav Sharma <0x0 0x2390000 0 0x1000>; 1016d548c217SVabhav Sharma interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1017d548c217SVabhav Sharma timeout-sec = <30>; 1018d548c217SVabhav Sharma }; 1019d548c217SVabhav Sharma 1020dca78e32SBiwen Li rcpm: power-controller@1e34040 { 1021dca78e32SBiwen Li compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1022dca78e32SBiwen Li reg = <0x0 0x1e34040 0x0 0x1c>; 1023dca78e32SBiwen Li #fsl,rcpm-wakeup-cells = <7>; 1024dca78e32SBiwen Li little-endian; 1025dca78e32SBiwen Li }; 1026dca78e32SBiwen Li 1027dca78e32SBiwen Li ftm_alarm0: timer@2800000 { 1028dca78e32SBiwen Li compatible = "fsl,lx2160a-ftm-alarm"; 1029dca78e32SBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 1030dca78e32SBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1031dca78e32SBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1032dca78e32SBiwen Li }; 1033dca78e32SBiwen Li 1034d548c217SVabhav Sharma usb0: usb@3100000 { 1035d548c217SVabhav Sharma compatible = "snps,dwc3"; 1036d548c217SVabhav Sharma reg = <0x0 0x3100000 0x0 0x10000>; 1037d548c217SVabhav Sharma interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1038d548c217SVabhav Sharma dr_mode = "host"; 1039d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 1040a5b13770SRan Wang usb3-lpm-capable; 1041d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 10421000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1043d548c217SVabhav Sharma status = "disabled"; 1044d548c217SVabhav Sharma }; 1045d548c217SVabhav Sharma 1046d548c217SVabhav Sharma usb1: usb@3110000 { 1047d548c217SVabhav Sharma compatible = "snps,dwc3"; 1048d548c217SVabhav Sharma reg = <0x0 0x3110000 0x0 0x10000>; 1049d548c217SVabhav Sharma interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1050d548c217SVabhav Sharma dr_mode = "host"; 1051d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 1052a5b13770SRan Wang usb3-lpm-capable; 1053d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 10541000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1055d548c217SVabhav Sharma status = "disabled"; 1056d548c217SVabhav Sharma }; 1057d548c217SVabhav Sharma 1058071f7855SPeng Ma sata0: sata@3200000 { 1059071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1060071f7855SPeng Ma reg = <0x0 0x3200000 0x0 0x10000>, 1061071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1062071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1063071f7855SPeng Ma interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 10648e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 10658e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1066071f7855SPeng Ma dma-coherent; 1067071f7855SPeng Ma status = "disabled"; 1068071f7855SPeng Ma }; 1069071f7855SPeng Ma 1070071f7855SPeng Ma sata1: sata@3210000 { 1071071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1072071f7855SPeng Ma reg = <0x0 0x3210000 0x0 0x10000>, 1073071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1074071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1075071f7855SPeng Ma interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 10768e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 10778e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1078071f7855SPeng Ma dma-coherent; 1079071f7855SPeng Ma status = "disabled"; 1080071f7855SPeng Ma }; 1081071f7855SPeng Ma 1082071f7855SPeng Ma sata2: sata@3220000 { 1083071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1084071f7855SPeng Ma reg = <0x0 0x3220000 0x0 0x10000>, 1085071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1086071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1087071f7855SPeng Ma interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 10888e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 10898e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1090071f7855SPeng Ma dma-coherent; 1091071f7855SPeng Ma status = "disabled"; 1092071f7855SPeng Ma }; 1093071f7855SPeng Ma 1094071f7855SPeng Ma sata3: sata@3230000 { 1095071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1096071f7855SPeng Ma reg = <0x0 0x3230000 0x0 0x10000>, 1097071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1098071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1099071f7855SPeng Ma interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 11008e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 11018e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1102071f7855SPeng Ma dma-coherent; 1103071f7855SPeng Ma status = "disabled"; 1104071f7855SPeng Ma }; 1105071f7855SPeng Ma 1106f7d48ffcSWasim Khan pcie1: pcie@3400000 { 1107b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1108ce87d936SZhen Lei reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 1109ce87d936SZhen Lei <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1110b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1111b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1112b1ad0e7dSHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1113b1ad0e7dSHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1114b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1115b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1116b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1117b1ad0e7dSHou Zhiqiang device_type = "pci"; 1118b1ad0e7dSHou Zhiqiang dma-coherent; 1119b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1120b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1121b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1122b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1123b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1124b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1125b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1126b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1127b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1128b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1129b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1130f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1131b1ad0e7dSHou Zhiqiang status = "disabled"; 1132b1ad0e7dSHou Zhiqiang }; 1133b1ad0e7dSHou Zhiqiang 1134f7d48ffcSWasim Khan pcie2: pcie@3500000 { 1135b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1136ce87d936SZhen Lei reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 1137ce87d936SZhen Lei <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1138b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1139b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1140b1ad0e7dSHou Zhiqiang <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1141b1ad0e7dSHou Zhiqiang <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1142b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1143b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1144b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1145b1ad0e7dSHou Zhiqiang device_type = "pci"; 1146b1ad0e7dSHou Zhiqiang dma-coherent; 1147b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1148b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1149b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1150b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1151b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1152b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1153b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1154b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1155b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1156b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1157b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1158f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1159b1ad0e7dSHou Zhiqiang status = "disabled"; 1160b1ad0e7dSHou Zhiqiang }; 1161b1ad0e7dSHou Zhiqiang 1162f7d48ffcSWasim Khan pcie3: pcie@3600000 { 1163b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1164ce87d936SZhen Lei reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 1165ce87d936SZhen Lei <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1166b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1167b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1168b1ad0e7dSHou Zhiqiang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1169b1ad0e7dSHou Zhiqiang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1170b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1171b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1172b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1173b1ad0e7dSHou Zhiqiang device_type = "pci"; 1174b1ad0e7dSHou Zhiqiang dma-coherent; 1175b1ad0e7dSHou Zhiqiang apio-wins = <256>; 1176b1ad0e7dSHou Zhiqiang ppio-wins = <24>; 1177b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1178b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1179b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1180b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1181b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1182b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1183b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1184b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1185b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1186f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1187b1ad0e7dSHou Zhiqiang status = "disabled"; 1188b1ad0e7dSHou Zhiqiang }; 1189b1ad0e7dSHou Zhiqiang 1190f7d48ffcSWasim Khan pcie4: pcie@3700000 { 1191b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1192ce87d936SZhen Lei reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 1193ce87d936SZhen Lei <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1194b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1195b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1196b1ad0e7dSHou Zhiqiang <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1197b1ad0e7dSHou Zhiqiang <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1198b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1199b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1200b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1201b1ad0e7dSHou Zhiqiang device_type = "pci"; 1202b1ad0e7dSHou Zhiqiang dma-coherent; 1203b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1204b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1205b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1206b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1207b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1208b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1209b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1210b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1211b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1212b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1213b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1214f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1215b1ad0e7dSHou Zhiqiang status = "disabled"; 1216b1ad0e7dSHou Zhiqiang }; 1217b1ad0e7dSHou Zhiqiang 1218f7d48ffcSWasim Khan pcie5: pcie@3800000 { 1219b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1220ce87d936SZhen Lei reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ 1221ce87d936SZhen Lei <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1222b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1223b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1224b1ad0e7dSHou Zhiqiang <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1225b1ad0e7dSHou Zhiqiang <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1226b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1227b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1228b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1229b1ad0e7dSHou Zhiqiang device_type = "pci"; 1230b1ad0e7dSHou Zhiqiang dma-coherent; 1231b1ad0e7dSHou Zhiqiang apio-wins = <256>; 1232b1ad0e7dSHou Zhiqiang ppio-wins = <24>; 1233b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1234b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1235b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1236b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1237b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1238b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1239b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1240b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1241b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1242f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1243b1ad0e7dSHou Zhiqiang status = "disabled"; 1244b1ad0e7dSHou Zhiqiang }; 1245b1ad0e7dSHou Zhiqiang 1246f7d48ffcSWasim Khan pcie6: pcie@3900000 { 1247b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1248ce87d936SZhen Lei reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ 1249ce87d936SZhen Lei <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1250b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1251b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1252b1ad0e7dSHou Zhiqiang <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1253b1ad0e7dSHou Zhiqiang <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1254b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1255b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1256b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1257b1ad0e7dSHou Zhiqiang device_type = "pci"; 1258b1ad0e7dSHou Zhiqiang dma-coherent; 1259b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1260b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1261b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1262b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1263b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1264b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1265b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1266b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1267b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1268b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1269b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1270f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1271b1ad0e7dSHou Zhiqiang status = "disabled"; 1272b1ad0e7dSHou Zhiqiang }; 1273b1ad0e7dSHou Zhiqiang 1274d548c217SVabhav Sharma smmu: iommu@5000000 { 1275d548c217SVabhav Sharma compatible = "arm,mmu-500"; 1276d548c217SVabhav Sharma reg = <0 0x5000000 0 0x800000>; 1277d548c217SVabhav Sharma #iommu-cells = <1>; 1278d548c217SVabhav Sharma #global-interrupts = <14>; 1279d548c217SVabhav Sharma // global secure fault 1280d548c217SVabhav Sharma interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1281d548c217SVabhav Sharma // combined secure 1282d548c217SVabhav Sharma <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1283d548c217SVabhav Sharma // global non-secure fault 1284d548c217SVabhav Sharma <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1285d548c217SVabhav Sharma // combined non-secure 1286d548c217SVabhav Sharma <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1287d548c217SVabhav Sharma // performance counter interrupts 0-9 1288d548c217SVabhav Sharma <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1289d548c217SVabhav Sharma <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1290d548c217SVabhav Sharma <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1291d548c217SVabhav Sharma <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1292d548c217SVabhav Sharma <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1293d548c217SVabhav Sharma <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1294d548c217SVabhav Sharma <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1295d548c217SVabhav Sharma <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1296d548c217SVabhav Sharma <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1297d548c217SVabhav Sharma <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1298d548c217SVabhav Sharma // per context interrupt, 64 interrupts 1299d548c217SVabhav Sharma <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1300d548c217SVabhav Sharma <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1301d548c217SVabhav Sharma <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1302d548c217SVabhav Sharma <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1303d548c217SVabhav Sharma <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1304d548c217SVabhav Sharma <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1305d548c217SVabhav Sharma <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1306d548c217SVabhav Sharma <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1307d548c217SVabhav Sharma <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1308d548c217SVabhav Sharma <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1309d548c217SVabhav Sharma <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1310d548c217SVabhav Sharma <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1311d548c217SVabhav Sharma <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1312d548c217SVabhav Sharma <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1313d548c217SVabhav Sharma <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1314d548c217SVabhav Sharma <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1315d548c217SVabhav Sharma <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1316d548c217SVabhav Sharma <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1317d548c217SVabhav Sharma <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1318d548c217SVabhav Sharma <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1319d548c217SVabhav Sharma <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1320d548c217SVabhav Sharma <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1321d548c217SVabhav Sharma <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1322d548c217SVabhav Sharma <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1323d548c217SVabhav Sharma <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1324d548c217SVabhav Sharma <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1325d548c217SVabhav Sharma <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1326d548c217SVabhav Sharma <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1327d548c217SVabhav Sharma <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1328d548c217SVabhav Sharma <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1329d548c217SVabhav Sharma <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1330d548c217SVabhav Sharma <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1331d548c217SVabhav Sharma <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1332d548c217SVabhav Sharma <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1333d548c217SVabhav Sharma <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1334d548c217SVabhav Sharma <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1335d548c217SVabhav Sharma <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1336d548c217SVabhav Sharma <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1337d548c217SVabhav Sharma <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1338d548c217SVabhav Sharma <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1339d548c217SVabhav Sharma <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1340d548c217SVabhav Sharma <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1341d548c217SVabhav Sharma <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1342d548c217SVabhav Sharma <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1343d548c217SVabhav Sharma <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1344d548c217SVabhav Sharma <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1345d548c217SVabhav Sharma <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1346d548c217SVabhav Sharma <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1347d548c217SVabhav Sharma <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1348d548c217SVabhav Sharma <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1349d548c217SVabhav Sharma <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1350d548c217SVabhav Sharma <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1351d548c217SVabhav Sharma <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1352d548c217SVabhav Sharma <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1353d548c217SVabhav Sharma <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1354d548c217SVabhav Sharma <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1355d548c217SVabhav Sharma <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1356d548c217SVabhav Sharma <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1357d548c217SVabhav Sharma <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1358d548c217SVabhav Sharma <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1359d548c217SVabhav Sharma <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1360d548c217SVabhav Sharma <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1361d548c217SVabhav Sharma <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1362d548c217SVabhav Sharma <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1363d548c217SVabhav Sharma dma-coherent; 1364d548c217SVabhav Sharma }; 1365703c5e40SIoana Ciocoi Radulescu 1366546d92d3SIoana Ciornei console@8340020 { 1367546d92d3SIoana Ciornei compatible = "fsl,dpaa2-console"; 1368546d92d3SIoana Ciornei reg = <0x00000000 0x08340020 0 0x2>; 1369546d92d3SIoana Ciornei }; 1370546d92d3SIoana Ciornei 1371fe844f19SYangbo Lu ptp-timer@8b95000 { 1372fe844f19SYangbo Lu compatible = "fsl,dpaa2-ptp"; 1373fe844f19SYangbo Lu reg = <0x0 0x8b95000 0x0 0x100>; 13748e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 13758e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 1376fe844f19SYangbo Lu little-endian; 1377fe844f19SYangbo Lu fsl,extts-fifo; 1378fe844f19SYangbo Lu }; 1379fe844f19SYangbo Lu 13806e1b8faeSIoana Ciornei /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 13816e1b8faeSIoana Ciornei emdio1: mdio@8b96000 { 13826e1b8faeSIoana Ciornei compatible = "fsl,fman-memac-mdio"; 13836e1b8faeSIoana Ciornei reg = <0x0 0x8b96000 0x0 0x1000>; 13846e1b8faeSIoana Ciornei interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 13856e1b8faeSIoana Ciornei #address-cells = <1>; 13866e1b8faeSIoana Ciornei #size-cells = <0>; 13876e1b8faeSIoana Ciornei little-endian; 13886e1b8faeSIoana Ciornei status = "disabled"; 13896e1b8faeSIoana Ciornei }; 13906e1b8faeSIoana Ciornei 13915705b9dcSRussell King emdio2: mdio@8b97000 { 13925705b9dcSRussell King compatible = "fsl,fman-memac-mdio"; 13935705b9dcSRussell King reg = <0x0 0x8b97000 0x0 0x1000>; 13945705b9dcSRussell King interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 13955705b9dcSRussell King little-endian; 13965705b9dcSRussell King #address-cells = <1>; 13975705b9dcSRussell King #size-cells = <0>; 13985705b9dcSRussell King status = "disabled"; 13995705b9dcSRussell King }; 14005705b9dcSRussell King 1401f94cfe32SIoana Ciornei pcs_mdio1: mdio@8c07000 { 1402f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1403f94cfe32SIoana Ciornei reg = <0x0 0x8c07000 0x0 0x1000>; 1404f94cfe32SIoana Ciornei little-endian; 1405f94cfe32SIoana Ciornei #address-cells = <1>; 1406f94cfe32SIoana Ciornei #size-cells = <0>; 1407f94cfe32SIoana Ciornei status = "disabled"; 1408f94cfe32SIoana Ciornei 1409f94cfe32SIoana Ciornei pcs1: ethernet-phy@0 { 1410f94cfe32SIoana Ciornei reg = <0>; 1411f94cfe32SIoana Ciornei }; 1412f94cfe32SIoana Ciornei }; 1413f94cfe32SIoana Ciornei 1414f94cfe32SIoana Ciornei pcs_mdio2: mdio@8c0b000 { 1415f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1416f94cfe32SIoana Ciornei reg = <0x0 0x8c0b000 0x0 0x1000>; 1417f94cfe32SIoana Ciornei little-endian; 1418f94cfe32SIoana Ciornei #address-cells = <1>; 1419f94cfe32SIoana Ciornei #size-cells = <0>; 1420f94cfe32SIoana Ciornei status = "disabled"; 1421f94cfe32SIoana Ciornei 1422f94cfe32SIoana Ciornei pcs2: ethernet-phy@0 { 1423f94cfe32SIoana Ciornei reg = <0>; 1424f94cfe32SIoana Ciornei }; 1425f94cfe32SIoana Ciornei }; 1426f94cfe32SIoana Ciornei 1427f94cfe32SIoana Ciornei pcs_mdio3: mdio@8c0f000 { 1428f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1429f94cfe32SIoana Ciornei reg = <0x0 0x8c0f000 0x0 0x1000>; 1430f94cfe32SIoana Ciornei little-endian; 1431f94cfe32SIoana Ciornei #address-cells = <1>; 1432f94cfe32SIoana Ciornei #size-cells = <0>; 1433f94cfe32SIoana Ciornei status = "disabled"; 1434f94cfe32SIoana Ciornei 1435f94cfe32SIoana Ciornei pcs3: ethernet-phy@0 { 1436f94cfe32SIoana Ciornei reg = <0>; 1437f94cfe32SIoana Ciornei }; 1438f94cfe32SIoana Ciornei }; 1439f94cfe32SIoana Ciornei 1440f94cfe32SIoana Ciornei pcs_mdio4: mdio@8c13000 { 1441f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1442f94cfe32SIoana Ciornei reg = <0x0 0x8c13000 0x0 0x1000>; 1443f94cfe32SIoana Ciornei little-endian; 1444f94cfe32SIoana Ciornei #address-cells = <1>; 1445f94cfe32SIoana Ciornei #size-cells = <0>; 1446f94cfe32SIoana Ciornei status = "disabled"; 1447f94cfe32SIoana Ciornei 1448f94cfe32SIoana Ciornei pcs4: ethernet-phy@0 { 1449f94cfe32SIoana Ciornei reg = <0>; 1450f94cfe32SIoana Ciornei }; 1451f94cfe32SIoana Ciornei }; 1452f94cfe32SIoana Ciornei 1453f94cfe32SIoana Ciornei pcs_mdio5: mdio@8c17000 { 1454f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1455f94cfe32SIoana Ciornei reg = <0x0 0x8c17000 0x0 0x1000>; 1456f94cfe32SIoana Ciornei little-endian; 1457f94cfe32SIoana Ciornei #address-cells = <1>; 1458f94cfe32SIoana Ciornei #size-cells = <0>; 1459f94cfe32SIoana Ciornei status = "disabled"; 1460f94cfe32SIoana Ciornei 1461f94cfe32SIoana Ciornei pcs5: ethernet-phy@0 { 1462f94cfe32SIoana Ciornei reg = <0>; 1463f94cfe32SIoana Ciornei }; 1464f94cfe32SIoana Ciornei }; 1465f94cfe32SIoana Ciornei 1466f94cfe32SIoana Ciornei pcs_mdio6: mdio@8c1b000 { 1467f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1468f94cfe32SIoana Ciornei reg = <0x0 0x8c1b000 0x0 0x1000>; 1469f94cfe32SIoana Ciornei little-endian; 1470f94cfe32SIoana Ciornei #address-cells = <1>; 1471f94cfe32SIoana Ciornei #size-cells = <0>; 1472f94cfe32SIoana Ciornei status = "disabled"; 1473f94cfe32SIoana Ciornei 1474f94cfe32SIoana Ciornei pcs6: ethernet-phy@0 { 1475f94cfe32SIoana Ciornei reg = <0>; 1476f94cfe32SIoana Ciornei }; 1477f94cfe32SIoana Ciornei }; 1478f94cfe32SIoana Ciornei 1479f94cfe32SIoana Ciornei pcs_mdio7: mdio@8c1f000 { 1480f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1481f94cfe32SIoana Ciornei reg = <0x0 0x8c1f000 0x0 0x1000>; 1482f94cfe32SIoana Ciornei little-endian; 1483f94cfe32SIoana Ciornei #address-cells = <1>; 1484f94cfe32SIoana Ciornei #size-cells = <0>; 1485f94cfe32SIoana Ciornei status = "disabled"; 1486f94cfe32SIoana Ciornei 1487f94cfe32SIoana Ciornei pcs7: ethernet-phy@0 { 1488f94cfe32SIoana Ciornei reg = <0>; 1489f94cfe32SIoana Ciornei }; 1490f94cfe32SIoana Ciornei }; 1491f94cfe32SIoana Ciornei 1492f94cfe32SIoana Ciornei pcs_mdio8: mdio@8c23000 { 1493f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1494f94cfe32SIoana Ciornei reg = <0x0 0x8c23000 0x0 0x1000>; 1495f94cfe32SIoana Ciornei little-endian; 1496f94cfe32SIoana Ciornei #address-cells = <1>; 1497f94cfe32SIoana Ciornei #size-cells = <0>; 1498f94cfe32SIoana Ciornei status = "disabled"; 1499f94cfe32SIoana Ciornei 1500f94cfe32SIoana Ciornei pcs8: ethernet-phy@0 { 1501f94cfe32SIoana Ciornei reg = <0>; 1502f94cfe32SIoana Ciornei }; 1503f94cfe32SIoana Ciornei }; 1504f94cfe32SIoana Ciornei 1505f94cfe32SIoana Ciornei pcs_mdio9: mdio@8c27000 { 1506f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1507f94cfe32SIoana Ciornei reg = <0x0 0x8c27000 0x0 0x1000>; 1508f94cfe32SIoana Ciornei little-endian; 1509f94cfe32SIoana Ciornei #address-cells = <1>; 1510f94cfe32SIoana Ciornei #size-cells = <0>; 1511f94cfe32SIoana Ciornei status = "disabled"; 1512f94cfe32SIoana Ciornei 1513f94cfe32SIoana Ciornei pcs9: ethernet-phy@0 { 1514f94cfe32SIoana Ciornei reg = <0>; 1515f94cfe32SIoana Ciornei }; 1516f94cfe32SIoana Ciornei }; 1517f94cfe32SIoana Ciornei 1518f94cfe32SIoana Ciornei pcs_mdio10: mdio@8c2b000 { 1519f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1520f94cfe32SIoana Ciornei reg = <0x0 0x8c2b000 0x0 0x1000>; 1521f94cfe32SIoana Ciornei little-endian; 1522f94cfe32SIoana Ciornei #address-cells = <1>; 1523f94cfe32SIoana Ciornei #size-cells = <0>; 1524f94cfe32SIoana Ciornei status = "disabled"; 1525f94cfe32SIoana Ciornei 1526f94cfe32SIoana Ciornei pcs10: ethernet-phy@0 { 1527f94cfe32SIoana Ciornei reg = <0>; 1528f94cfe32SIoana Ciornei }; 1529f94cfe32SIoana Ciornei }; 1530f94cfe32SIoana Ciornei 1531f94cfe32SIoana Ciornei pcs_mdio11: mdio@8c2f000 { 1532f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1533f94cfe32SIoana Ciornei reg = <0x0 0x8c2f000 0x0 0x1000>; 1534f94cfe32SIoana Ciornei little-endian; 1535f94cfe32SIoana Ciornei #address-cells = <1>; 1536f94cfe32SIoana Ciornei #size-cells = <0>; 1537f94cfe32SIoana Ciornei status = "disabled"; 1538f94cfe32SIoana Ciornei 1539f94cfe32SIoana Ciornei pcs11: ethernet-phy@0 { 1540f94cfe32SIoana Ciornei reg = <0>; 1541f94cfe32SIoana Ciornei }; 1542f94cfe32SIoana Ciornei }; 1543f94cfe32SIoana Ciornei 1544f94cfe32SIoana Ciornei pcs_mdio12: mdio@8c33000 { 1545f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1546f94cfe32SIoana Ciornei reg = <0x0 0x8c33000 0x0 0x1000>; 1547f94cfe32SIoana Ciornei little-endian; 1548f94cfe32SIoana Ciornei #address-cells = <1>; 1549f94cfe32SIoana Ciornei #size-cells = <0>; 1550f94cfe32SIoana Ciornei status = "disabled"; 1551f94cfe32SIoana Ciornei 1552f94cfe32SIoana Ciornei pcs12: ethernet-phy@0 { 1553f94cfe32SIoana Ciornei reg = <0>; 1554f94cfe32SIoana Ciornei }; 1555f94cfe32SIoana Ciornei }; 1556f94cfe32SIoana Ciornei 1557f94cfe32SIoana Ciornei pcs_mdio13: mdio@8c37000 { 1558f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1559f94cfe32SIoana Ciornei reg = <0x0 0x8c37000 0x0 0x1000>; 1560f94cfe32SIoana Ciornei little-endian; 1561f94cfe32SIoana Ciornei #address-cells = <1>; 1562f94cfe32SIoana Ciornei #size-cells = <0>; 1563f94cfe32SIoana Ciornei status = "disabled"; 1564f94cfe32SIoana Ciornei 1565f94cfe32SIoana Ciornei pcs13: ethernet-phy@0 { 1566f94cfe32SIoana Ciornei reg = <0>; 1567f94cfe32SIoana Ciornei }; 1568f94cfe32SIoana Ciornei }; 1569f94cfe32SIoana Ciornei 1570f94cfe32SIoana Ciornei pcs_mdio14: mdio@8c3b000 { 1571f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1572f94cfe32SIoana Ciornei reg = <0x0 0x8c3b000 0x0 0x1000>; 1573f94cfe32SIoana Ciornei little-endian; 1574f94cfe32SIoana Ciornei #address-cells = <1>; 1575f94cfe32SIoana Ciornei #size-cells = <0>; 1576f94cfe32SIoana Ciornei status = "disabled"; 1577f94cfe32SIoana Ciornei 1578f94cfe32SIoana Ciornei pcs14: ethernet-phy@0 { 1579f94cfe32SIoana Ciornei reg = <0>; 1580f94cfe32SIoana Ciornei }; 1581f94cfe32SIoana Ciornei }; 1582f94cfe32SIoana Ciornei 1583f94cfe32SIoana Ciornei pcs_mdio15: mdio@8c3f000 { 1584f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1585f94cfe32SIoana Ciornei reg = <0x0 0x8c3f000 0x0 0x1000>; 1586f94cfe32SIoana Ciornei little-endian; 1587f94cfe32SIoana Ciornei #address-cells = <1>; 1588f94cfe32SIoana Ciornei #size-cells = <0>; 1589f94cfe32SIoana Ciornei status = "disabled"; 1590f94cfe32SIoana Ciornei 1591f94cfe32SIoana Ciornei pcs15: ethernet-phy@0 { 1592f94cfe32SIoana Ciornei reg = <0>; 1593f94cfe32SIoana Ciornei }; 1594f94cfe32SIoana Ciornei }; 1595f94cfe32SIoana Ciornei 1596f94cfe32SIoana Ciornei pcs_mdio16: mdio@8c43000 { 1597f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1598f94cfe32SIoana Ciornei reg = <0x0 0x8c43000 0x0 0x1000>; 1599f94cfe32SIoana Ciornei little-endian; 1600f94cfe32SIoana Ciornei #address-cells = <1>; 1601f94cfe32SIoana Ciornei #size-cells = <0>; 1602f94cfe32SIoana Ciornei status = "disabled"; 1603f94cfe32SIoana Ciornei 1604f94cfe32SIoana Ciornei pcs16: ethernet-phy@0 { 1605f94cfe32SIoana Ciornei reg = <0>; 1606f94cfe32SIoana Ciornei }; 1607f94cfe32SIoana Ciornei }; 1608f94cfe32SIoana Ciornei 1609f94cfe32SIoana Ciornei pcs_mdio17: mdio@8c47000 { 1610f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1611f94cfe32SIoana Ciornei reg = <0x0 0x8c47000 0x0 0x1000>; 1612f94cfe32SIoana Ciornei little-endian; 1613f94cfe32SIoana Ciornei #address-cells = <1>; 1614f94cfe32SIoana Ciornei #size-cells = <0>; 1615f94cfe32SIoana Ciornei status = "disabled"; 1616f94cfe32SIoana Ciornei 1617f94cfe32SIoana Ciornei pcs17: ethernet-phy@0 { 1618f94cfe32SIoana Ciornei reg = <0>; 1619f94cfe32SIoana Ciornei }; 1620f94cfe32SIoana Ciornei }; 1621f94cfe32SIoana Ciornei 1622f94cfe32SIoana Ciornei pcs_mdio18: mdio@8c4b000 { 1623f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1624f94cfe32SIoana Ciornei reg = <0x0 0x8c4b000 0x0 0x1000>; 1625f94cfe32SIoana Ciornei little-endian; 1626f94cfe32SIoana Ciornei #address-cells = <1>; 1627f94cfe32SIoana Ciornei #size-cells = <0>; 1628f94cfe32SIoana Ciornei status = "disabled"; 1629f94cfe32SIoana Ciornei 1630f94cfe32SIoana Ciornei pcs18: ethernet-phy@0 { 1631f94cfe32SIoana Ciornei reg = <0>; 1632f94cfe32SIoana Ciornei }; 1633f94cfe32SIoana Ciornei }; 1634f94cfe32SIoana Ciornei 1635703c5e40SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 1636703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 1637703c5e40SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, 1638703c5e40SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; 1639703c5e40SIoana Ciocoi Radulescu msi-parent = <&its>; 1640703c5e40SIoana Ciocoi Radulescu /* iommu-map property is fixed up by u-boot */ 1641703c5e40SIoana Ciocoi Radulescu iommu-map = <0 &smmu 0 0>; 1642703c5e40SIoana Ciocoi Radulescu dma-coherent; 1643703c5e40SIoana Ciocoi Radulescu #address-cells = <3>; 1644703c5e40SIoana Ciocoi Radulescu #size-cells = <1>; 1645703c5e40SIoana Ciocoi Radulescu 1646703c5e40SIoana Ciocoi Radulescu /* 1647703c5e40SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 1648703c5e40SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 1649703c5e40SIoana Ciocoi Radulescu */ 1650703c5e40SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1651703c5e40SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1652703c5e40SIoana Ciocoi Radulescu 1653703c5e40SIoana Ciocoi Radulescu /* 1654703c5e40SIoana Ciocoi Radulescu * Define the maximum number of MACs present on the SoC. 1655703c5e40SIoana Ciocoi Radulescu */ 1656703c5e40SIoana Ciocoi Radulescu dpmacs { 1657703c5e40SIoana Ciocoi Radulescu #address-cells = <1>; 1658703c5e40SIoana Ciocoi Radulescu #size-cells = <0>; 1659703c5e40SIoana Ciocoi Radulescu 1660f94cfe32SIoana Ciornei dpmac1: ethernet@1 { 1661703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1662703c5e40SIoana Ciocoi Radulescu reg = <0x1>; 1663f94cfe32SIoana Ciornei pcs-handle = <&pcs1>; 1664703c5e40SIoana Ciocoi Radulescu }; 1665703c5e40SIoana Ciocoi Radulescu 1666f94cfe32SIoana Ciornei dpmac2: ethernet@2 { 1667703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1668703c5e40SIoana Ciocoi Radulescu reg = <0x2>; 1669f94cfe32SIoana Ciornei pcs-handle = <&pcs2>; 1670703c5e40SIoana Ciocoi Radulescu }; 1671703c5e40SIoana Ciocoi Radulescu 1672f94cfe32SIoana Ciornei dpmac3: ethernet@3 { 1673703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1674703c5e40SIoana Ciocoi Radulescu reg = <0x3>; 1675f94cfe32SIoana Ciornei pcs-handle = <&pcs3>; 1676703c5e40SIoana Ciocoi Radulescu }; 1677703c5e40SIoana Ciocoi Radulescu 1678f94cfe32SIoana Ciornei dpmac4: ethernet@4 { 1679703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1680703c5e40SIoana Ciocoi Radulescu reg = <0x4>; 1681f94cfe32SIoana Ciornei pcs-handle = <&pcs4>; 1682703c5e40SIoana Ciocoi Radulescu }; 1683703c5e40SIoana Ciocoi Radulescu 1684f94cfe32SIoana Ciornei dpmac5: ethernet@5 { 1685703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1686703c5e40SIoana Ciocoi Radulescu reg = <0x5>; 1687f94cfe32SIoana Ciornei pcs-handle = <&pcs5>; 1688703c5e40SIoana Ciocoi Radulescu }; 1689703c5e40SIoana Ciocoi Radulescu 1690f94cfe32SIoana Ciornei dpmac6: ethernet@6 { 1691703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1692703c5e40SIoana Ciocoi Radulescu reg = <0x6>; 1693f94cfe32SIoana Ciornei pcs-handle = <&pcs6>; 1694703c5e40SIoana Ciocoi Radulescu }; 1695703c5e40SIoana Ciocoi Radulescu 1696f94cfe32SIoana Ciornei dpmac7: ethernet@7 { 1697703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1698703c5e40SIoana Ciocoi Radulescu reg = <0x7>; 1699f94cfe32SIoana Ciornei pcs-handle = <&pcs7>; 1700703c5e40SIoana Ciocoi Radulescu }; 1701703c5e40SIoana Ciocoi Radulescu 1702f94cfe32SIoana Ciornei dpmac8: ethernet@8 { 1703703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1704703c5e40SIoana Ciocoi Radulescu reg = <0x8>; 1705f94cfe32SIoana Ciornei pcs-handle = <&pcs8>; 1706703c5e40SIoana Ciocoi Radulescu }; 1707703c5e40SIoana Ciocoi Radulescu 1708f94cfe32SIoana Ciornei dpmac9: ethernet@9 { 1709703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1710703c5e40SIoana Ciocoi Radulescu reg = <0x9>; 1711f94cfe32SIoana Ciornei pcs-handle = <&pcs9>; 1712703c5e40SIoana Ciocoi Radulescu }; 1713703c5e40SIoana Ciocoi Radulescu 1714f94cfe32SIoana Ciornei dpmac10: ethernet@a { 1715703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1716703c5e40SIoana Ciocoi Radulescu reg = <0xa>; 1717f94cfe32SIoana Ciornei pcs-handle = <&pcs10>; 1718703c5e40SIoana Ciocoi Radulescu }; 1719703c5e40SIoana Ciocoi Radulescu 1720f94cfe32SIoana Ciornei dpmac11: ethernet@b { 1721703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1722703c5e40SIoana Ciocoi Radulescu reg = <0xb>; 1723f94cfe32SIoana Ciornei pcs-handle = <&pcs11>; 1724703c5e40SIoana Ciocoi Radulescu }; 1725703c5e40SIoana Ciocoi Radulescu 1726f94cfe32SIoana Ciornei dpmac12: ethernet@c { 1727703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1728703c5e40SIoana Ciocoi Radulescu reg = <0xc>; 1729f94cfe32SIoana Ciornei pcs-handle = <&pcs12>; 1730703c5e40SIoana Ciocoi Radulescu }; 1731703c5e40SIoana Ciocoi Radulescu 1732f94cfe32SIoana Ciornei dpmac13: ethernet@d { 1733703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1734703c5e40SIoana Ciocoi Radulescu reg = <0xd>; 1735f94cfe32SIoana Ciornei pcs-handle = <&pcs13>; 1736703c5e40SIoana Ciocoi Radulescu }; 1737703c5e40SIoana Ciocoi Radulescu 1738f94cfe32SIoana Ciornei dpmac14: ethernet@e { 1739703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1740703c5e40SIoana Ciocoi Radulescu reg = <0xe>; 1741f94cfe32SIoana Ciornei pcs-handle = <&pcs14>; 1742703c5e40SIoana Ciocoi Radulescu }; 1743703c5e40SIoana Ciocoi Radulescu 1744f94cfe32SIoana Ciornei dpmac15: ethernet@f { 1745703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1746703c5e40SIoana Ciocoi Radulescu reg = <0xf>; 1747f94cfe32SIoana Ciornei pcs-handle = <&pcs15>; 1748703c5e40SIoana Ciocoi Radulescu }; 1749703c5e40SIoana Ciocoi Radulescu 1750f94cfe32SIoana Ciornei dpmac16: ethernet@10 { 1751703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1752703c5e40SIoana Ciocoi Radulescu reg = <0x10>; 1753f94cfe32SIoana Ciornei pcs-handle = <&pcs16>; 1754703c5e40SIoana Ciocoi Radulescu }; 1755703c5e40SIoana Ciocoi Radulescu 1756f94cfe32SIoana Ciornei dpmac17: ethernet@11 { 1757703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1758703c5e40SIoana Ciocoi Radulescu reg = <0x11>; 1759f94cfe32SIoana Ciornei pcs-handle = <&pcs17>; 1760703c5e40SIoana Ciocoi Radulescu }; 1761703c5e40SIoana Ciocoi Radulescu 1762f94cfe32SIoana Ciornei dpmac18: ethernet@12 { 1763703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1764703c5e40SIoana Ciocoi Radulescu reg = <0x12>; 1765f94cfe32SIoana Ciornei pcs-handle = <&pcs18>; 1766703c5e40SIoana Ciocoi Radulescu }; 1767703c5e40SIoana Ciocoi Radulescu }; 1768703c5e40SIoana Ciocoi Radulescu }; 1769d548c217SVabhav Sharma }; 1770519bace3SPankaj Gupta 1771519bace3SPankaj Gupta firmware { 1772519bace3SPankaj Gupta optee: optee { 1773519bace3SPankaj Gupta compatible = "linaro,optee-tz"; 1774519bace3SPankaj Gupta method = "smc"; 1775519bace3SPankaj Gupta status = "disabled"; 1776519bace3SPankaj Gupta }; 1777519bace3SPankaj Gupta }; 1778d548c217SVabhav Sharma}; 1779