1d548c217SVabhav Sharma// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2d548c217SVabhav Sharma// 3d548c217SVabhav Sharma// Device Tree Include file for Layerscape-LX2160A family SoC. 4d548c217SVabhav Sharma// 566dfd959SWasim Khan// Copyright 2018-2020 NXP 6d548c217SVabhav Sharma 7*8e9f7797SMichael Walle#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8d548c217SVabhav Sharma#include <dt-bindings/gpio/gpio.h> 9d548c217SVabhav Sharma#include <dt-bindings/interrupt-controller/arm-gic.h> 105363eaaeSYuantian Tang#include <dt-bindings/thermal/thermal.h> 11d548c217SVabhav Sharma 12d548c217SVabhav Sharma/memreserve/ 0x80000000 0x00010000; 13d548c217SVabhav Sharma 14d548c217SVabhav Sharma/ { 15d548c217SVabhav Sharma compatible = "fsl,lx2160a"; 16d548c217SVabhav Sharma interrupt-parent = <&gic>; 17d548c217SVabhav Sharma #address-cells = <2>; 18d548c217SVabhav Sharma #size-cells = <2>; 19d548c217SVabhav Sharma 20dca78e32SBiwen Li aliases { 21dca78e32SBiwen Li rtc1 = &ftm_alarm0; 22dca78e32SBiwen Li }; 23dca78e32SBiwen Li 24d548c217SVabhav Sharma cpus { 25d548c217SVabhav Sharma #address-cells = <1>; 26d548c217SVabhav Sharma #size-cells = <0>; 27d548c217SVabhav Sharma 28d548c217SVabhav Sharma // 8 clusters having 2 Cortex-A72 cores each 295363eaaeSYuantian Tang cpu0: cpu@0 { 30d548c217SVabhav Sharma device_type = "cpu"; 31d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 32d548c217SVabhav Sharma enable-method = "psci"; 33d548c217SVabhav Sharma reg = <0x0>; 34*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35d548c217SVabhav Sharma d-cache-size = <0x8000>; 36d548c217SVabhav Sharma d-cache-line-size = <64>; 37d548c217SVabhav Sharma d-cache-sets = <128>; 38d548c217SVabhav Sharma i-cache-size = <0xC000>; 39d548c217SVabhav Sharma i-cache-line-size = <64>; 40d548c217SVabhav Sharma i-cache-sets = <192>; 41d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 4207159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 435363eaaeSYuantian Tang #cooling-cells = <2>; 44d548c217SVabhav Sharma }; 45d548c217SVabhav Sharma 465363eaaeSYuantian Tang cpu1: cpu@1 { 47d548c217SVabhav Sharma device_type = "cpu"; 48d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 49d548c217SVabhav Sharma enable-method = "psci"; 50d548c217SVabhav Sharma reg = <0x1>; 51*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52d548c217SVabhav Sharma d-cache-size = <0x8000>; 53d548c217SVabhav Sharma d-cache-line-size = <64>; 54d548c217SVabhav Sharma d-cache-sets = <128>; 55d548c217SVabhav Sharma i-cache-size = <0xC000>; 56d548c217SVabhav Sharma i-cache-line-size = <64>; 57d548c217SVabhav Sharma i-cache-sets = <192>; 58d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 5907159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 605363eaaeSYuantian Tang #cooling-cells = <2>; 61d548c217SVabhav Sharma }; 62d548c217SVabhav Sharma 635363eaaeSYuantian Tang cpu100: cpu@100 { 64d548c217SVabhav Sharma device_type = "cpu"; 65d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 66d548c217SVabhav Sharma enable-method = "psci"; 67d548c217SVabhav Sharma reg = <0x100>; 68*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69d548c217SVabhav Sharma d-cache-size = <0x8000>; 70d548c217SVabhav Sharma d-cache-line-size = <64>; 71d548c217SVabhav Sharma d-cache-sets = <128>; 72d548c217SVabhav Sharma i-cache-size = <0xC000>; 73d548c217SVabhav Sharma i-cache-line-size = <64>; 74d548c217SVabhav Sharma i-cache-sets = <192>; 75d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 7607159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 775363eaaeSYuantian Tang #cooling-cells = <2>; 78d548c217SVabhav Sharma }; 79d548c217SVabhav Sharma 805363eaaeSYuantian Tang cpu101: cpu@101 { 81d548c217SVabhav Sharma device_type = "cpu"; 82d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 83d548c217SVabhav Sharma enable-method = "psci"; 84d548c217SVabhav Sharma reg = <0x101>; 85*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86d548c217SVabhav Sharma d-cache-size = <0x8000>; 87d548c217SVabhav Sharma d-cache-line-size = <64>; 88d548c217SVabhav Sharma d-cache-sets = <128>; 89d548c217SVabhav Sharma i-cache-size = <0xC000>; 90d548c217SVabhav Sharma i-cache-line-size = <64>; 91d548c217SVabhav Sharma i-cache-sets = <192>; 92d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 9307159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 945363eaaeSYuantian Tang #cooling-cells = <2>; 95d548c217SVabhav Sharma }; 96d548c217SVabhav Sharma 975363eaaeSYuantian Tang cpu200: cpu@200 { 98d548c217SVabhav Sharma device_type = "cpu"; 99d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 100d548c217SVabhav Sharma enable-method = "psci"; 101d548c217SVabhav Sharma reg = <0x200>; 102*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103d548c217SVabhav Sharma d-cache-size = <0x8000>; 104d548c217SVabhav Sharma d-cache-line-size = <64>; 105d548c217SVabhav Sharma d-cache-sets = <128>; 106d548c217SVabhav Sharma i-cache-size = <0xC000>; 107d548c217SVabhav Sharma i-cache-line-size = <64>; 108d548c217SVabhav Sharma i-cache-sets = <192>; 109d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 11007159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1115363eaaeSYuantian Tang #cooling-cells = <2>; 112d548c217SVabhav Sharma }; 113d548c217SVabhav Sharma 1145363eaaeSYuantian Tang cpu201: cpu@201 { 115d548c217SVabhav Sharma device_type = "cpu"; 116d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 117d548c217SVabhav Sharma enable-method = "psci"; 118d548c217SVabhav Sharma reg = <0x201>; 119*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120d548c217SVabhav Sharma d-cache-size = <0x8000>; 121d548c217SVabhav Sharma d-cache-line-size = <64>; 122d548c217SVabhav Sharma d-cache-sets = <128>; 123d548c217SVabhav Sharma i-cache-size = <0xC000>; 124d548c217SVabhav Sharma i-cache-line-size = <64>; 125d548c217SVabhav Sharma i-cache-sets = <192>; 126d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 12707159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1285363eaaeSYuantian Tang #cooling-cells = <2>; 129d548c217SVabhav Sharma }; 130d548c217SVabhav Sharma 1315363eaaeSYuantian Tang cpu300: cpu@300 { 132d548c217SVabhav Sharma device_type = "cpu"; 133d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 134d548c217SVabhav Sharma enable-method = "psci"; 135d548c217SVabhav Sharma reg = <0x300>; 136*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137d548c217SVabhav Sharma d-cache-size = <0x8000>; 138d548c217SVabhav Sharma d-cache-line-size = <64>; 139d548c217SVabhav Sharma d-cache-sets = <128>; 140d548c217SVabhav Sharma i-cache-size = <0xC000>; 141d548c217SVabhav Sharma i-cache-line-size = <64>; 142d548c217SVabhav Sharma i-cache-sets = <192>; 143d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 14407159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1455363eaaeSYuantian Tang #cooling-cells = <2>; 146d548c217SVabhav Sharma }; 147d548c217SVabhav Sharma 1485363eaaeSYuantian Tang cpu301: cpu@301 { 149d548c217SVabhav Sharma device_type = "cpu"; 150d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 151d548c217SVabhav Sharma enable-method = "psci"; 152d548c217SVabhav Sharma reg = <0x301>; 153*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154d548c217SVabhav Sharma d-cache-size = <0x8000>; 155d548c217SVabhav Sharma d-cache-line-size = <64>; 156d548c217SVabhav Sharma d-cache-sets = <128>; 157d548c217SVabhav Sharma i-cache-size = <0xC000>; 158d548c217SVabhav Sharma i-cache-line-size = <64>; 159d548c217SVabhav Sharma i-cache-sets = <192>; 160d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 16107159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1625363eaaeSYuantian Tang #cooling-cells = <2>; 163d548c217SVabhav Sharma }; 164d548c217SVabhav Sharma 1655363eaaeSYuantian Tang cpu400: cpu@400 { 166d548c217SVabhav Sharma device_type = "cpu"; 167d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 168d548c217SVabhav Sharma enable-method = "psci"; 169d548c217SVabhav Sharma reg = <0x400>; 170*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171d548c217SVabhav Sharma d-cache-size = <0x8000>; 172d548c217SVabhav Sharma d-cache-line-size = <64>; 173d548c217SVabhav Sharma d-cache-sets = <128>; 174d548c217SVabhav Sharma i-cache-size = <0xC000>; 175d548c217SVabhav Sharma i-cache-line-size = <64>; 176d548c217SVabhav Sharma i-cache-sets = <192>; 177d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 17807159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1795363eaaeSYuantian Tang #cooling-cells = <2>; 180d548c217SVabhav Sharma }; 181d548c217SVabhav Sharma 1825363eaaeSYuantian Tang cpu401: cpu@401 { 183d548c217SVabhav Sharma device_type = "cpu"; 184d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 185d548c217SVabhav Sharma enable-method = "psci"; 186d548c217SVabhav Sharma reg = <0x401>; 187*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188d548c217SVabhav Sharma d-cache-size = <0x8000>; 189d548c217SVabhav Sharma d-cache-line-size = <64>; 190d548c217SVabhav Sharma d-cache-sets = <128>; 191d548c217SVabhav Sharma i-cache-size = <0xC000>; 192d548c217SVabhav Sharma i-cache-line-size = <64>; 193d548c217SVabhav Sharma i-cache-sets = <192>; 194d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 19507159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 1965363eaaeSYuantian Tang #cooling-cells = <2>; 197d548c217SVabhav Sharma }; 198d548c217SVabhav Sharma 1995363eaaeSYuantian Tang cpu500: cpu@500 { 200d548c217SVabhav Sharma device_type = "cpu"; 201d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 202d548c217SVabhav Sharma enable-method = "psci"; 203d548c217SVabhav Sharma reg = <0x500>; 204*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205d548c217SVabhav Sharma d-cache-size = <0x8000>; 206d548c217SVabhav Sharma d-cache-line-size = <64>; 207d548c217SVabhav Sharma d-cache-sets = <128>; 208d548c217SVabhav Sharma i-cache-size = <0xC000>; 209d548c217SVabhav Sharma i-cache-line-size = <64>; 210d548c217SVabhav Sharma i-cache-sets = <192>; 211d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 21207159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2135363eaaeSYuantian Tang #cooling-cells = <2>; 214d548c217SVabhav Sharma }; 215d548c217SVabhav Sharma 2165363eaaeSYuantian Tang cpu501: cpu@501 { 217d548c217SVabhav Sharma device_type = "cpu"; 218d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 219d548c217SVabhav Sharma enable-method = "psci"; 220d548c217SVabhav Sharma reg = <0x501>; 221*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222d548c217SVabhav Sharma d-cache-size = <0x8000>; 223d548c217SVabhav Sharma d-cache-line-size = <64>; 224d548c217SVabhav Sharma d-cache-sets = <128>; 225d548c217SVabhav Sharma i-cache-size = <0xC000>; 226d548c217SVabhav Sharma i-cache-line-size = <64>; 227d548c217SVabhav Sharma i-cache-sets = <192>; 228d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 22907159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2305363eaaeSYuantian Tang #cooling-cells = <2>; 231d548c217SVabhav Sharma }; 232d548c217SVabhav Sharma 2335363eaaeSYuantian Tang cpu600: cpu@600 { 234d548c217SVabhav Sharma device_type = "cpu"; 235d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 236d548c217SVabhav Sharma enable-method = "psci"; 237d548c217SVabhav Sharma reg = <0x600>; 238*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239d548c217SVabhav Sharma d-cache-size = <0x8000>; 240d548c217SVabhav Sharma d-cache-line-size = <64>; 241d548c217SVabhav Sharma d-cache-sets = <128>; 242d548c217SVabhav Sharma i-cache-size = <0xC000>; 243d548c217SVabhav Sharma i-cache-line-size = <64>; 244d548c217SVabhav Sharma i-cache-sets = <192>; 245d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 24607159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2475363eaaeSYuantian Tang #cooling-cells = <2>; 248d548c217SVabhav Sharma }; 249d548c217SVabhav Sharma 2505363eaaeSYuantian Tang cpu601: cpu@601 { 251d548c217SVabhav Sharma device_type = "cpu"; 252d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 253d548c217SVabhav Sharma enable-method = "psci"; 254d548c217SVabhav Sharma reg = <0x601>; 255*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256d548c217SVabhav Sharma d-cache-size = <0x8000>; 257d548c217SVabhav Sharma d-cache-line-size = <64>; 258d548c217SVabhav Sharma d-cache-sets = <128>; 259d548c217SVabhav Sharma i-cache-size = <0xC000>; 260d548c217SVabhav Sharma i-cache-line-size = <64>; 261d548c217SVabhav Sharma i-cache-sets = <192>; 262d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 26307159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2645363eaaeSYuantian Tang #cooling-cells = <2>; 265d548c217SVabhav Sharma }; 266d548c217SVabhav Sharma 2675363eaaeSYuantian Tang cpu700: cpu@700 { 268d548c217SVabhav Sharma device_type = "cpu"; 269d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 270d548c217SVabhav Sharma enable-method = "psci"; 271d548c217SVabhav Sharma reg = <0x700>; 272*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273d548c217SVabhav Sharma d-cache-size = <0x8000>; 274d548c217SVabhav Sharma d-cache-line-size = <64>; 275d548c217SVabhav Sharma d-cache-sets = <128>; 276d548c217SVabhav Sharma i-cache-size = <0xC000>; 277d548c217SVabhav Sharma i-cache-line-size = <64>; 278d548c217SVabhav Sharma i-cache-sets = <192>; 279d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 28007159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2815363eaaeSYuantian Tang #cooling-cells = <2>; 282d548c217SVabhav Sharma }; 283d548c217SVabhav Sharma 2845363eaaeSYuantian Tang cpu701: cpu@701 { 285d548c217SVabhav Sharma device_type = "cpu"; 286d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 287d548c217SVabhav Sharma enable-method = "psci"; 288d548c217SVabhav Sharma reg = <0x701>; 289*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290d548c217SVabhav Sharma d-cache-size = <0x8000>; 291d548c217SVabhav Sharma d-cache-line-size = <64>; 292d548c217SVabhav Sharma d-cache-sets = <128>; 293d548c217SVabhav Sharma i-cache-size = <0xC000>; 294d548c217SVabhav Sharma i-cache-line-size = <64>; 295d548c217SVabhav Sharma i-cache-sets = <192>; 296d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 29707159f67SRan Wang cpu-idle-states = <&cpu_pw15>; 2985363eaaeSYuantian Tang #cooling-cells = <2>; 299d548c217SVabhav Sharma }; 300d548c217SVabhav Sharma 301d548c217SVabhav Sharma cluster0_l2: l2-cache0 { 302d548c217SVabhav Sharma compatible = "cache"; 303d548c217SVabhav Sharma cache-size = <0x100000>; 304d548c217SVabhav Sharma cache-line-size = <64>; 305d548c217SVabhav Sharma cache-sets = <1024>; 306d548c217SVabhav Sharma cache-level = <2>; 307d548c217SVabhav Sharma }; 308d548c217SVabhav Sharma 309d548c217SVabhav Sharma cluster1_l2: l2-cache1 { 310d548c217SVabhav Sharma compatible = "cache"; 311d548c217SVabhav Sharma cache-size = <0x100000>; 312d548c217SVabhav Sharma cache-line-size = <64>; 313d548c217SVabhav Sharma cache-sets = <1024>; 314d548c217SVabhav Sharma cache-level = <2>; 315d548c217SVabhav Sharma }; 316d548c217SVabhav Sharma 317d548c217SVabhav Sharma cluster2_l2: l2-cache2 { 318d548c217SVabhav Sharma compatible = "cache"; 319d548c217SVabhav Sharma cache-size = <0x100000>; 320d548c217SVabhav Sharma cache-line-size = <64>; 321d548c217SVabhav Sharma cache-sets = <1024>; 322d548c217SVabhav Sharma cache-level = <2>; 323d548c217SVabhav Sharma }; 324d548c217SVabhav Sharma 325d548c217SVabhav Sharma cluster3_l2: l2-cache3 { 326d548c217SVabhav Sharma compatible = "cache"; 327d548c217SVabhav Sharma cache-size = <0x100000>; 328d548c217SVabhav Sharma cache-line-size = <64>; 329d548c217SVabhav Sharma cache-sets = <1024>; 330d548c217SVabhav Sharma cache-level = <2>; 331d548c217SVabhav Sharma }; 332d548c217SVabhav Sharma 333d548c217SVabhav Sharma cluster4_l2: l2-cache4 { 334d548c217SVabhav Sharma compatible = "cache"; 335d548c217SVabhav Sharma cache-size = <0x100000>; 336d548c217SVabhav Sharma cache-line-size = <64>; 337d548c217SVabhav Sharma cache-sets = <1024>; 338d548c217SVabhav Sharma cache-level = <2>; 339d548c217SVabhav Sharma }; 340d548c217SVabhav Sharma 341d548c217SVabhav Sharma cluster5_l2: l2-cache5 { 342d548c217SVabhav Sharma compatible = "cache"; 343d548c217SVabhav Sharma cache-size = <0x100000>; 344d548c217SVabhav Sharma cache-line-size = <64>; 345d548c217SVabhav Sharma cache-sets = <1024>; 346d548c217SVabhav Sharma cache-level = <2>; 347d548c217SVabhav Sharma }; 348d548c217SVabhav Sharma 349d548c217SVabhav Sharma cluster6_l2: l2-cache6 { 350d548c217SVabhav Sharma compatible = "cache"; 351d548c217SVabhav Sharma cache-size = <0x100000>; 352d548c217SVabhav Sharma cache-line-size = <64>; 353d548c217SVabhav Sharma cache-sets = <1024>; 354d548c217SVabhav Sharma cache-level = <2>; 355d548c217SVabhav Sharma }; 356d548c217SVabhav Sharma 357d548c217SVabhav Sharma cluster7_l2: l2-cache7 { 358d548c217SVabhav Sharma compatible = "cache"; 359d548c217SVabhav Sharma cache-size = <0x100000>; 360d548c217SVabhav Sharma cache-line-size = <64>; 361d548c217SVabhav Sharma cache-sets = <1024>; 362d548c217SVabhav Sharma cache-level = <2>; 363d548c217SVabhav Sharma }; 36400c5ce8aSRan Wang 36507159f67SRan Wang cpu_pw15: cpu-pw15 { 36600c5ce8aSRan Wang compatible = "arm,idle-state"; 36707159f67SRan Wang idle-state-name = "PW15"; 36800c5ce8aSRan Wang arm,psci-suspend-param = <0x0>; 36900c5ce8aSRan Wang entry-latency-us = <2000>; 37000c5ce8aSRan Wang exit-latency-us = <2000>; 37100c5ce8aSRan Wang min-residency-us = <6000>; 37200c5ce8aSRan Wang }; 373d548c217SVabhav Sharma }; 374d548c217SVabhav Sharma 375d548c217SVabhav Sharma gic: interrupt-controller@6000000 { 376d548c217SVabhav Sharma compatible = "arm,gic-v3"; 377d548c217SVabhav Sharma reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 378d548c217SVabhav Sharma <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 379d548c217SVabhav Sharma // SGI_base) 380d548c217SVabhav Sharma <0x0 0x0c0c0000 0 0x2000>, // GICC 381d548c217SVabhav Sharma <0x0 0x0c0d0000 0 0x1000>, // GICH 382d548c217SVabhav Sharma <0x0 0x0c0e0000 0 0x20000>; // GICV 383d548c217SVabhav Sharma #interrupt-cells = <3>; 384d548c217SVabhav Sharma #address-cells = <2>; 385d548c217SVabhav Sharma #size-cells = <2>; 386d548c217SVabhav Sharma ranges; 387d548c217SVabhav Sharma interrupt-controller; 388d548c217SVabhav Sharma interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 389d548c217SVabhav Sharma 390d548c217SVabhav Sharma its: gic-its@6020000 { 391d548c217SVabhav Sharma compatible = "arm,gic-v3-its"; 392d548c217SVabhav Sharma msi-controller; 393d548c217SVabhav Sharma reg = <0x0 0x6020000 0 0x20000>; 394d548c217SVabhav Sharma }; 395d548c217SVabhav Sharma }; 396d548c217SVabhav Sharma 397d548c217SVabhav Sharma timer { 398d548c217SVabhav Sharma compatible = "arm,armv8-timer"; 399d548c217SVabhav Sharma interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 400d548c217SVabhav Sharma <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 401d548c217SVabhav Sharma <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 402d548c217SVabhav Sharma <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 403d548c217SVabhav Sharma }; 404d548c217SVabhav Sharma 405d548c217SVabhav Sharma pmu { 406d548c217SVabhav Sharma compatible = "arm,cortex-a72-pmu"; 407d548c217SVabhav Sharma interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 408d548c217SVabhav Sharma }; 409d548c217SVabhav Sharma 410d548c217SVabhav Sharma psci { 411d548c217SVabhav Sharma compatible = "arm,psci-0.2"; 412d548c217SVabhav Sharma method = "smc"; 413d548c217SVabhav Sharma }; 414d548c217SVabhav Sharma 415d548c217SVabhav Sharma memory@80000000 { 416d548c217SVabhav Sharma // DRAM space - 1, size : 2 GB DRAM 417d548c217SVabhav Sharma device_type = "memory"; 418d548c217SVabhav Sharma reg = <0x00000000 0x80000000 0 0x80000000>; 419d548c217SVabhav Sharma }; 420d548c217SVabhav Sharma 421d548c217SVabhav Sharma ddr1: memory-controller@1080000 { 422d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 423d548c217SVabhav Sharma reg = <0x0 0x1080000 0x0 0x1000>; 424d548c217SVabhav Sharma interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 425d548c217SVabhav Sharma little-endian; 426d548c217SVabhav Sharma }; 427d548c217SVabhav Sharma 428d548c217SVabhav Sharma ddr2: memory-controller@1090000 { 429d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 430d548c217SVabhav Sharma reg = <0x0 0x1090000 0x0 0x1000>; 431d548c217SVabhav Sharma interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 432d548c217SVabhav Sharma little-endian; 433d548c217SVabhav Sharma }; 434d548c217SVabhav Sharma 435d548c217SVabhav Sharma // One clock unit-sysclk node which bootloader require during DT fix-up 436d548c217SVabhav Sharma sysclk: sysclk { 437d548c217SVabhav Sharma compatible = "fixed-clock"; 438d548c217SVabhav Sharma #clock-cells = <0>; 439d548c217SVabhav Sharma clock-frequency = <100000000>; // fixed up by bootloader 440d548c217SVabhav Sharma clock-output-names = "sysclk"; 441d548c217SVabhav Sharma }; 442d548c217SVabhav Sharma 4435363eaaeSYuantian Tang thermal-zones { 444ac082ea8SYuantian Tang cluster6-7 { 4455363eaaeSYuantian Tang polling-delay-passive = <1000>; 4465363eaaeSYuantian Tang polling-delay = <5000>; 4475363eaaeSYuantian Tang thermal-sensors = <&tmu 0>; 4485363eaaeSYuantian Tang 4495363eaaeSYuantian Tang trips { 450ac082ea8SYuantian Tang cluster6_7_alert: cluster6-7-alert { 4515363eaaeSYuantian Tang temperature = <85000>; 4525363eaaeSYuantian Tang hysteresis = <2000>; 4535363eaaeSYuantian Tang type = "passive"; 4545363eaaeSYuantian Tang }; 4555363eaaeSYuantian Tang 456ac082ea8SYuantian Tang cluster6_7_crit: cluster6-7-crit { 4575363eaaeSYuantian Tang temperature = <95000>; 4585363eaaeSYuantian Tang hysteresis = <2000>; 4595363eaaeSYuantian Tang type = "critical"; 4605363eaaeSYuantian Tang }; 4615363eaaeSYuantian Tang }; 4625363eaaeSYuantian Tang 4635363eaaeSYuantian Tang cooling-maps { 4645363eaaeSYuantian Tang map0 { 465ac082ea8SYuantian Tang trip = <&cluster6_7_alert>; 4665363eaaeSYuantian Tang cooling-device = 4675363eaaeSYuantian Tang <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685363eaaeSYuantian Tang <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4695363eaaeSYuantian Tang <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4705363eaaeSYuantian Tang <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4715363eaaeSYuantian Tang <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4725363eaaeSYuantian Tang <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4735363eaaeSYuantian Tang <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4745363eaaeSYuantian Tang <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4755363eaaeSYuantian Tang <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765363eaaeSYuantian Tang <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775363eaaeSYuantian Tang <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4785363eaaeSYuantian Tang <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4795363eaaeSYuantian Tang <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4805363eaaeSYuantian Tang <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815363eaaeSYuantian Tang <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4825363eaaeSYuantian Tang <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4835363eaaeSYuantian Tang }; 4845363eaaeSYuantian Tang }; 4855363eaaeSYuantian Tang }; 486ac082ea8SYuantian Tang 487ac082ea8SYuantian Tang ddr-cluster5 { 488ac082ea8SYuantian Tang polling-delay-passive = <1000>; 489ac082ea8SYuantian Tang polling-delay = <5000>; 490ac082ea8SYuantian Tang thermal-sensors = <&tmu 1>; 491ac082ea8SYuantian Tang 492ac082ea8SYuantian Tang trips { 493ac082ea8SYuantian Tang ddr-cluster5-alert { 494ac082ea8SYuantian Tang temperature = <85000>; 495ac082ea8SYuantian Tang hysteresis = <2000>; 496ac082ea8SYuantian Tang type = "passive"; 497ac082ea8SYuantian Tang }; 498ac082ea8SYuantian Tang 499ac082ea8SYuantian Tang ddr-cluster5-crit { 500ac082ea8SYuantian Tang temperature = <95000>; 501ac082ea8SYuantian Tang hysteresis = <2000>; 502ac082ea8SYuantian Tang type = "critical"; 503ac082ea8SYuantian Tang }; 504ac082ea8SYuantian Tang }; 505ac082ea8SYuantian Tang }; 506ac082ea8SYuantian Tang 507ac082ea8SYuantian Tang wriop { 508ac082ea8SYuantian Tang polling-delay-passive = <1000>; 509ac082ea8SYuantian Tang polling-delay = <5000>; 510ac082ea8SYuantian Tang thermal-sensors = <&tmu 2>; 511ac082ea8SYuantian Tang 512ac082ea8SYuantian Tang trips { 513ac082ea8SYuantian Tang wriop-alert { 514ac082ea8SYuantian Tang temperature = <85000>; 515ac082ea8SYuantian Tang hysteresis = <2000>; 516ac082ea8SYuantian Tang type = "passive"; 517ac082ea8SYuantian Tang }; 518ac082ea8SYuantian Tang 519ac082ea8SYuantian Tang wriop-crit { 520ac082ea8SYuantian Tang temperature = <95000>; 521ac082ea8SYuantian Tang hysteresis = <2000>; 522ac082ea8SYuantian Tang type = "critical"; 523ac082ea8SYuantian Tang }; 524ac082ea8SYuantian Tang }; 525ac082ea8SYuantian Tang }; 526ac082ea8SYuantian Tang 527ac082ea8SYuantian Tang dce-qbman-hsio2 { 528ac082ea8SYuantian Tang polling-delay-passive = <1000>; 529ac082ea8SYuantian Tang polling-delay = <5000>; 530ac082ea8SYuantian Tang thermal-sensors = <&tmu 3>; 531ac082ea8SYuantian Tang 532ac082ea8SYuantian Tang trips { 533ac082ea8SYuantian Tang dce-qbman-alert { 534ac082ea8SYuantian Tang temperature = <85000>; 535ac082ea8SYuantian Tang hysteresis = <2000>; 536ac082ea8SYuantian Tang type = "passive"; 537ac082ea8SYuantian Tang }; 538ac082ea8SYuantian Tang 539ac082ea8SYuantian Tang dce-qbman-crit { 540ac082ea8SYuantian Tang temperature = <95000>; 541ac082ea8SYuantian Tang hysteresis = <2000>; 542ac082ea8SYuantian Tang type = "critical"; 543ac082ea8SYuantian Tang }; 544ac082ea8SYuantian Tang }; 545ac082ea8SYuantian Tang }; 546ac082ea8SYuantian Tang 547ac082ea8SYuantian Tang ccn-dpaa-tbu { 548ac082ea8SYuantian Tang polling-delay-passive = <1000>; 549ac082ea8SYuantian Tang polling-delay = <5000>; 550ac082ea8SYuantian Tang thermal-sensors = <&tmu 4>; 551ac082ea8SYuantian Tang 552ac082ea8SYuantian Tang trips { 553ac082ea8SYuantian Tang ccn-dpaa-alert { 554ac082ea8SYuantian Tang temperature = <85000>; 555ac082ea8SYuantian Tang hysteresis = <2000>; 556ac082ea8SYuantian Tang type = "passive"; 557ac082ea8SYuantian Tang }; 558ac082ea8SYuantian Tang 559ac082ea8SYuantian Tang ccn-dpaa-crit { 560ac082ea8SYuantian Tang temperature = <95000>; 561ac082ea8SYuantian Tang hysteresis = <2000>; 562ac082ea8SYuantian Tang type = "critical"; 563ac082ea8SYuantian Tang }; 564ac082ea8SYuantian Tang }; 565ac082ea8SYuantian Tang }; 566ac082ea8SYuantian Tang 567ac082ea8SYuantian Tang cluster4-hsio3 { 568ac082ea8SYuantian Tang polling-delay-passive = <1000>; 569ac082ea8SYuantian Tang polling-delay = <5000>; 570ac082ea8SYuantian Tang thermal-sensors = <&tmu 5>; 571ac082ea8SYuantian Tang 572ac082ea8SYuantian Tang trips { 573ac082ea8SYuantian Tang clust4-hsio3-alert { 574ac082ea8SYuantian Tang temperature = <85000>; 575ac082ea8SYuantian Tang hysteresis = <2000>; 576ac082ea8SYuantian Tang type = "passive"; 577ac082ea8SYuantian Tang }; 578ac082ea8SYuantian Tang 579ac082ea8SYuantian Tang clust4-hsio3-crit { 580ac082ea8SYuantian Tang temperature = <95000>; 581ac082ea8SYuantian Tang hysteresis = <2000>; 582ac082ea8SYuantian Tang type = "critical"; 583ac082ea8SYuantian Tang }; 584ac082ea8SYuantian Tang }; 585ac082ea8SYuantian Tang }; 586ac082ea8SYuantian Tang 587ac082ea8SYuantian Tang cluster2-3 { 588ac082ea8SYuantian Tang polling-delay-passive = <1000>; 589ac082ea8SYuantian Tang polling-delay = <5000>; 590ac082ea8SYuantian Tang thermal-sensors = <&tmu 6>; 591ac082ea8SYuantian Tang 592ac082ea8SYuantian Tang trips { 593ac082ea8SYuantian Tang cluster2-3-alert { 594ac082ea8SYuantian Tang temperature = <85000>; 595ac082ea8SYuantian Tang hysteresis = <2000>; 596ac082ea8SYuantian Tang type = "passive"; 597ac082ea8SYuantian Tang }; 598ac082ea8SYuantian Tang 599ac082ea8SYuantian Tang cluster2-3-crit { 600ac082ea8SYuantian Tang temperature = <95000>; 601ac082ea8SYuantian Tang hysteresis = <2000>; 602ac082ea8SYuantian Tang type = "critical"; 603ac082ea8SYuantian Tang }; 604ac082ea8SYuantian Tang }; 605ac082ea8SYuantian Tang }; 6065363eaaeSYuantian Tang }; 6075363eaaeSYuantian Tang 608d548c217SVabhav Sharma soc { 609d548c217SVabhav Sharma compatible = "simple-bus"; 610d548c217SVabhav Sharma #address-cells = <2>; 611d548c217SVabhav Sharma #size-cells = <2>; 612d548c217SVabhav Sharma ranges; 6130154878dSIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 614d548c217SVabhav Sharma 615d548c217SVabhav Sharma crypto: crypto@8000000 { 616d548c217SVabhav Sharma compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 617d548c217SVabhav Sharma fsl,sec-era = <10>; 618d548c217SVabhav Sharma #address-cells = <1>; 619d548c217SVabhav Sharma #size-cells = <1>; 620d548c217SVabhav Sharma ranges = <0x0 0x00 0x8000000 0x100000>; 621d548c217SVabhav Sharma reg = <0x00 0x8000000 0x0 0x100000>; 622d548c217SVabhav Sharma interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 623d548c217SVabhav Sharma dma-coherent; 624d548c217SVabhav Sharma status = "disabled"; 625d548c217SVabhav Sharma 626d548c217SVabhav Sharma sec_jr0: jr@10000 { 627d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 628d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 629d548c217SVabhav Sharma reg = <0x10000 0x10000>; 630d548c217SVabhav Sharma interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 631d548c217SVabhav Sharma }; 632d548c217SVabhav Sharma 633d548c217SVabhav Sharma sec_jr1: jr@20000 { 634d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 635d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 636d548c217SVabhav Sharma reg = <0x20000 0x10000>; 637d548c217SVabhav Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 638d548c217SVabhav Sharma }; 639d548c217SVabhav Sharma 640d548c217SVabhav Sharma sec_jr2: jr@30000 { 641d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 642d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 643d548c217SVabhav Sharma reg = <0x30000 0x10000>; 644d548c217SVabhav Sharma interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 645d548c217SVabhav Sharma }; 646d548c217SVabhav Sharma 647d548c217SVabhav Sharma sec_jr3: jr@40000 { 648d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 649d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 650d548c217SVabhav Sharma reg = <0x40000 0x10000>; 651d548c217SVabhav Sharma interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 652d548c217SVabhav Sharma }; 653d548c217SVabhav Sharma }; 654d548c217SVabhav Sharma 655d548c217SVabhav Sharma clockgen: clock-controller@1300000 { 656d548c217SVabhav Sharma compatible = "fsl,lx2160a-clockgen"; 657d548c217SVabhav Sharma reg = <0 0x1300000 0 0xa0000>; 658d548c217SVabhav Sharma #clock-cells = <2>; 659d548c217SVabhav Sharma clocks = <&sysclk>; 660d548c217SVabhav Sharma }; 661d548c217SVabhav Sharma 662d548c217SVabhav Sharma dcfg: syscon@1e00000 { 663d548c217SVabhav Sharma compatible = "fsl,lx2160a-dcfg", "syscon"; 664d548c217SVabhav Sharma reg = <0x0 0x1e00000 0x0 0x10000>; 665d548c217SVabhav Sharma little-endian; 666d548c217SVabhav Sharma }; 667d548c217SVabhav Sharma 668332b6a79SBiwen Li isc: syscon@1f70000 { 669332b6a79SBiwen Li compatible = "fsl,lx2160a-isc", "syscon"; 670332b6a79SBiwen Li reg = <0x0 0x1f70000 0x0 0x10000>; 671332b6a79SBiwen Li little-endian; 672332b6a79SBiwen Li #address-cells = <1>; 673332b6a79SBiwen Li #size-cells = <1>; 674332b6a79SBiwen Li ranges = <0x0 0x0 0x1f70000 0x10000>; 675332b6a79SBiwen Li 676332b6a79SBiwen Li extirq: interrupt-controller@14 { 677332b6a79SBiwen Li compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 678332b6a79SBiwen Li #interrupt-cells = <2>; 679332b6a79SBiwen Li #address-cells = <0>; 680332b6a79SBiwen Li interrupt-controller; 681332b6a79SBiwen Li reg = <0x14 4>; 682332b6a79SBiwen Li interrupt-map = 683332b6a79SBiwen Li <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 684332b6a79SBiwen Li <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 685332b6a79SBiwen Li <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 686332b6a79SBiwen Li <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 687332b6a79SBiwen Li <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 688332b6a79SBiwen Li <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 689332b6a79SBiwen Li <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 690332b6a79SBiwen Li <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 691332b6a79SBiwen Li <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 692332b6a79SBiwen Li <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 693332b6a79SBiwen Li <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 694332b6a79SBiwen Li <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 695332b6a79SBiwen Li interrupt-map-mask = <0xffffffff 0x0>; 696332b6a79SBiwen Li }; 697332b6a79SBiwen Li }; 698332b6a79SBiwen Li 6995363eaaeSYuantian Tang tmu: tmu@1f80000 { 7005363eaaeSYuantian Tang compatible = "fsl,qoriq-tmu"; 7015363eaaeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 7025363eaaeSYuantian Tang interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 7035363eaaeSYuantian Tang fsl,tmu-range = <0x800000e6 0x8001017d>; 7045363eaaeSYuantian Tang fsl,tmu-calibration = 7055363eaaeSYuantian Tang /* Calibration data group 1 */ 7065363eaaeSYuantian Tang <0x00000000 0x00000035 7075363eaaeSYuantian Tang /* Calibration data group 2 */ 708ac082ea8SYuantian Tang 0x00000001 0x00000154>; 7095363eaaeSYuantian Tang little-endian; 7105363eaaeSYuantian Tang #thermal-sensor-cells = <1>; 7115363eaaeSYuantian Tang }; 7125363eaaeSYuantian Tang 713d548c217SVabhav Sharma i2c0: i2c@2000000 { 714d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 715d548c217SVabhav Sharma #address-cells = <1>; 716d548c217SVabhav Sharma #size-cells = <0>; 717d548c217SVabhav Sharma reg = <0x0 0x2000000 0x0 0x10000>; 718d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 719d548c217SVabhav Sharma clock-names = "i2c"; 720*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 721*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 722d548c217SVabhav Sharma scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; 723d548c217SVabhav Sharma status = "disabled"; 724d548c217SVabhav Sharma }; 725d548c217SVabhav Sharma 726d548c217SVabhav Sharma i2c1: i2c@2010000 { 727d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 728d548c217SVabhav Sharma #address-cells = <1>; 729d548c217SVabhav Sharma #size-cells = <0>; 730d548c217SVabhav Sharma reg = <0x0 0x2010000 0x0 0x10000>; 731d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 732d548c217SVabhav Sharma clock-names = "i2c"; 733*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 734*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 735d548c217SVabhav Sharma status = "disabled"; 736d548c217SVabhav Sharma }; 737d548c217SVabhav Sharma 738d548c217SVabhav Sharma i2c2: i2c@2020000 { 739d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 740d548c217SVabhav Sharma #address-cells = <1>; 741d548c217SVabhav Sharma #size-cells = <0>; 742d548c217SVabhav Sharma reg = <0x0 0x2020000 0x0 0x10000>; 743d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 744d548c217SVabhav Sharma clock-names = "i2c"; 745*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 746*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 747d548c217SVabhav Sharma status = "disabled"; 748d548c217SVabhav Sharma }; 749d548c217SVabhav Sharma 750d548c217SVabhav Sharma i2c3: i2c@2030000 { 751d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 752d548c217SVabhav Sharma #address-cells = <1>; 753d548c217SVabhav Sharma #size-cells = <0>; 754d548c217SVabhav Sharma reg = <0x0 0x2030000 0x0 0x10000>; 755d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 756d548c217SVabhav Sharma clock-names = "i2c"; 757*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 758*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 759d548c217SVabhav Sharma status = "disabled"; 760d548c217SVabhav Sharma }; 761d548c217SVabhav Sharma 762d548c217SVabhav Sharma i2c4: i2c@2040000 { 763d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 764d548c217SVabhav Sharma #address-cells = <1>; 765d548c217SVabhav Sharma #size-cells = <0>; 766d548c217SVabhav Sharma reg = <0x0 0x2040000 0x0 0x10000>; 767d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 768d548c217SVabhav Sharma clock-names = "i2c"; 769*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 770*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 771d548c217SVabhav Sharma scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; 772d548c217SVabhav Sharma status = "disabled"; 773d548c217SVabhav Sharma }; 774d548c217SVabhav Sharma 775d548c217SVabhav Sharma i2c5: i2c@2050000 { 776d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 777d548c217SVabhav Sharma #address-cells = <1>; 778d548c217SVabhav Sharma #size-cells = <0>; 779d548c217SVabhav Sharma reg = <0x0 0x2050000 0x0 0x10000>; 780d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 781d548c217SVabhav Sharma clock-names = "i2c"; 782*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 783*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 784d548c217SVabhav Sharma status = "disabled"; 785d548c217SVabhav Sharma }; 786d548c217SVabhav Sharma 787d548c217SVabhav Sharma i2c6: i2c@2060000 { 788d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 789d548c217SVabhav Sharma #address-cells = <1>; 790d548c217SVabhav Sharma #size-cells = <0>; 791d548c217SVabhav Sharma reg = <0x0 0x2060000 0x0 0x10000>; 792d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 793d548c217SVabhav Sharma clock-names = "i2c"; 794*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 795*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 796d548c217SVabhav Sharma status = "disabled"; 797d548c217SVabhav Sharma }; 798d548c217SVabhav Sharma 799d548c217SVabhav Sharma i2c7: i2c@2070000 { 800d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 801d548c217SVabhav Sharma #address-cells = <1>; 802d548c217SVabhav Sharma #size-cells = <0>; 803d548c217SVabhav Sharma reg = <0x0 0x2070000 0x0 0x10000>; 804d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 805d548c217SVabhav Sharma clock-names = "i2c"; 806*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 807*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 808d548c217SVabhav Sharma status = "disabled"; 809d548c217SVabhav Sharma }; 810d548c217SVabhav Sharma 8111ffeef4eSYogesh Narayan Gaur fspi: spi@20c0000 { 8121ffeef4eSYogesh Narayan Gaur compatible = "nxp,lx2160a-fspi"; 8131ffeef4eSYogesh Narayan Gaur #address-cells = <1>; 8141ffeef4eSYogesh Narayan Gaur #size-cells = <0>; 8151ffeef4eSYogesh Narayan Gaur reg = <0x0 0x20c0000 0x0 0x10000>, 8161ffeef4eSYogesh Narayan Gaur <0x0 0x20000000 0x0 0x10000000>; 8171ffeef4eSYogesh Narayan Gaur reg-names = "fspi_base", "fspi_mmap"; 8181ffeef4eSYogesh Narayan Gaur interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 819*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 820*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>, 821*8e9f7797SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 822*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 8231ffeef4eSYogesh Narayan Gaur clock-names = "fspi_en", "fspi"; 8241ffeef4eSYogesh Narayan Gaur status = "disabled"; 8251ffeef4eSYogesh Narayan Gaur }; 8261ffeef4eSYogesh Narayan Gaur 82783ebd4a5SChuanhua Han dspi0: spi@2100000 { 82883ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 82983ebd4a5SChuanhua Han #address-cells = <1>; 83083ebd4a5SChuanhua Han #size-cells = <0>; 83183ebd4a5SChuanhua Han reg = <0x0 0x2100000 0x0 0x10000>; 83283ebd4a5SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 833*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 834*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 83583ebd4a5SChuanhua Han clock-names = "dspi"; 83683ebd4a5SChuanhua Han spi-num-chipselects = <5>; 83783ebd4a5SChuanhua Han bus-num = <0>; 83883ebd4a5SChuanhua Han status = "disabled"; 83983ebd4a5SChuanhua Han }; 84083ebd4a5SChuanhua Han 84183ebd4a5SChuanhua Han dspi1: spi@2110000 { 84283ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 84383ebd4a5SChuanhua Han #address-cells = <1>; 84483ebd4a5SChuanhua Han #size-cells = <0>; 84583ebd4a5SChuanhua Han reg = <0x0 0x2110000 0x0 0x10000>; 84683ebd4a5SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 847*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 848*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 84983ebd4a5SChuanhua Han clock-names = "dspi"; 85083ebd4a5SChuanhua Han spi-num-chipselects = <5>; 85183ebd4a5SChuanhua Han bus-num = <1>; 85283ebd4a5SChuanhua Han status = "disabled"; 85383ebd4a5SChuanhua Han }; 85483ebd4a5SChuanhua Han 85583ebd4a5SChuanhua Han dspi2: spi@2120000 { 85683ebd4a5SChuanhua Han compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 85783ebd4a5SChuanhua Han #address-cells = <1>; 85883ebd4a5SChuanhua Han #size-cells = <0>; 85983ebd4a5SChuanhua Han reg = <0x0 0x2120000 0x0 0x10000>; 86083ebd4a5SChuanhua Han interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 861*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 862*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(8)>; 86383ebd4a5SChuanhua Han clock-names = "dspi"; 86483ebd4a5SChuanhua Han spi-num-chipselects = <5>; 86583ebd4a5SChuanhua Han bus-num = <2>; 86683ebd4a5SChuanhua Han status = "disabled"; 86783ebd4a5SChuanhua Han }; 86883ebd4a5SChuanhua Han 869d548c217SVabhav Sharma esdhc0: esdhc@2140000 { 870d548c217SVabhav Sharma compatible = "fsl,esdhc"; 871d548c217SVabhav Sharma reg = <0x0 0x2140000 0x0 0x10000>; 872d548c217SVabhav Sharma interrupts = <0 28 0x4>; /* Level high type */ 873*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 874*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 87562b4359cSRussell King dma-coherent; 876d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 877d548c217SVabhav Sharma sdhci,auto-cmd12; 878d548c217SVabhav Sharma little-endian; 879d548c217SVabhav Sharma bus-width = <4>; 880d548c217SVabhav Sharma status = "disabled"; 881d548c217SVabhav Sharma }; 882d548c217SVabhav Sharma 883d548c217SVabhav Sharma esdhc1: esdhc@2150000 { 884d548c217SVabhav Sharma compatible = "fsl,esdhc"; 885d548c217SVabhav Sharma reg = <0x0 0x2150000 0x0 0x10000>; 886d548c217SVabhav Sharma interrupts = <0 63 0x4>; /* Level high type */ 887*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 888*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 88962b4359cSRussell King dma-coherent; 890d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 891d548c217SVabhav Sharma sdhci,auto-cmd12; 892d548c217SVabhav Sharma broken-cd; 893d548c217SVabhav Sharma little-endian; 894d548c217SVabhav Sharma bus-width = <4>; 895d548c217SVabhav Sharma status = "disabled"; 896d548c217SVabhav Sharma }; 897d548c217SVabhav Sharma 898d548c217SVabhav Sharma uart0: serial@21c0000 { 899d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 900d548c217SVabhav Sharma reg = <0x0 0x21c0000 0x0 0x1000>; 901d548c217SVabhav Sharma interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 902d548c217SVabhav Sharma current-speed = <115200>; 903d548c217SVabhav Sharma status = "disabled"; 904d548c217SVabhav Sharma }; 905d548c217SVabhav Sharma 906d548c217SVabhav Sharma uart1: serial@21d0000 { 907d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 908d548c217SVabhav Sharma reg = <0x0 0x21d0000 0x0 0x1000>; 909d548c217SVabhav Sharma interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 910d548c217SVabhav Sharma current-speed = <115200>; 911d548c217SVabhav Sharma status = "disabled"; 912d548c217SVabhav Sharma }; 913d548c217SVabhav Sharma 914d548c217SVabhav Sharma uart2: serial@21e0000 { 915d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 916d548c217SVabhav Sharma reg = <0x0 0x21e0000 0x0 0x1000>; 917d548c217SVabhav Sharma interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 918d548c217SVabhav Sharma current-speed = <115200>; 919d548c217SVabhav Sharma status = "disabled"; 920d548c217SVabhav Sharma }; 921d548c217SVabhav Sharma 922d548c217SVabhav Sharma uart3: serial@21f0000 { 923d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 924d548c217SVabhav Sharma reg = <0x0 0x21f0000 0x0 0x1000>; 925d548c217SVabhav Sharma interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 926d548c217SVabhav Sharma current-speed = <115200>; 927d548c217SVabhav Sharma status = "disabled"; 928d548c217SVabhav Sharma }; 929d548c217SVabhav Sharma 930d548c217SVabhav Sharma gpio0: gpio@2300000 { 931d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 932d548c217SVabhav Sharma reg = <0x0 0x2300000 0x0 0x10000>; 933d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 934d548c217SVabhav Sharma gpio-controller; 935d548c217SVabhav Sharma little-endian; 936d548c217SVabhav Sharma #gpio-cells = <2>; 937d548c217SVabhav Sharma interrupt-controller; 938d548c217SVabhav Sharma #interrupt-cells = <2>; 939d548c217SVabhav Sharma }; 940d548c217SVabhav Sharma 941d548c217SVabhav Sharma gpio1: gpio@2310000 { 942d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 943d548c217SVabhav Sharma reg = <0x0 0x2310000 0x0 0x10000>; 944d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 945d548c217SVabhav Sharma gpio-controller; 946d548c217SVabhav Sharma little-endian; 947d548c217SVabhav Sharma #gpio-cells = <2>; 948d548c217SVabhav Sharma interrupt-controller; 949d548c217SVabhav Sharma #interrupt-cells = <2>; 950d548c217SVabhav Sharma }; 951d548c217SVabhav Sharma 952d548c217SVabhav Sharma gpio2: gpio@2320000 { 953d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 954d548c217SVabhav Sharma reg = <0x0 0x2320000 0x0 0x10000>; 955d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 956d548c217SVabhav Sharma gpio-controller; 957d548c217SVabhav Sharma little-endian; 958d548c217SVabhav Sharma #gpio-cells = <2>; 959d548c217SVabhav Sharma interrupt-controller; 960d548c217SVabhav Sharma #interrupt-cells = <2>; 961d548c217SVabhav Sharma }; 962d548c217SVabhav Sharma 963d548c217SVabhav Sharma gpio3: gpio@2330000 { 964d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 965d548c217SVabhav Sharma reg = <0x0 0x2330000 0x0 0x10000>; 966d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 967d548c217SVabhav Sharma gpio-controller; 968d548c217SVabhav Sharma little-endian; 969d548c217SVabhav Sharma #gpio-cells = <2>; 970d548c217SVabhav Sharma interrupt-controller; 971d548c217SVabhav Sharma #interrupt-cells = <2>; 972d548c217SVabhav Sharma }; 973d548c217SVabhav Sharma 974d548c217SVabhav Sharma watchdog@23a0000 { 975d548c217SVabhav Sharma compatible = "arm,sbsa-gwdt"; 976d548c217SVabhav Sharma reg = <0x0 0x23a0000 0 0x1000>, 977d548c217SVabhav Sharma <0x0 0x2390000 0 0x1000>; 978d548c217SVabhav Sharma interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 979d548c217SVabhav Sharma timeout-sec = <30>; 980d548c217SVabhav Sharma }; 981d548c217SVabhav Sharma 982dca78e32SBiwen Li rcpm: power-controller@1e34040 { 983dca78e32SBiwen Li compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 984dca78e32SBiwen Li reg = <0x0 0x1e34040 0x0 0x1c>; 985dca78e32SBiwen Li #fsl,rcpm-wakeup-cells = <7>; 986dca78e32SBiwen Li little-endian; 987dca78e32SBiwen Li }; 988dca78e32SBiwen Li 989dca78e32SBiwen Li ftm_alarm0: timer@2800000 { 990dca78e32SBiwen Li compatible = "fsl,lx2160a-ftm-alarm"; 991dca78e32SBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 992dca78e32SBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 993dca78e32SBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 994dca78e32SBiwen Li }; 995dca78e32SBiwen Li 996d548c217SVabhav Sharma usb0: usb@3100000 { 997d548c217SVabhav Sharma compatible = "snps,dwc3"; 998d548c217SVabhav Sharma reg = <0x0 0x3100000 0x0 0x10000>; 999d548c217SVabhav Sharma interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1000d548c217SVabhav Sharma dr_mode = "host"; 1001d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 1002d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 10031000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1004d548c217SVabhav Sharma status = "disabled"; 1005d548c217SVabhav Sharma }; 1006d548c217SVabhav Sharma 1007d548c217SVabhav Sharma usb1: usb@3110000 { 1008d548c217SVabhav Sharma compatible = "snps,dwc3"; 1009d548c217SVabhav Sharma reg = <0x0 0x3110000 0x0 0x10000>; 1010d548c217SVabhav Sharma interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1011d548c217SVabhav Sharma dr_mode = "host"; 1012d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 1013d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 10141000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1015d548c217SVabhav Sharma status = "disabled"; 1016d548c217SVabhav Sharma }; 1017d548c217SVabhav Sharma 1018071f7855SPeng Ma sata0: sata@3200000 { 1019071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1020071f7855SPeng Ma reg = <0x0 0x3200000 0x0 0x10000>, 1021071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1022071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1023071f7855SPeng Ma interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1024*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1025*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1026071f7855SPeng Ma dma-coherent; 1027071f7855SPeng Ma status = "disabled"; 1028071f7855SPeng Ma }; 1029071f7855SPeng Ma 1030071f7855SPeng Ma sata1: sata@3210000 { 1031071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1032071f7855SPeng Ma reg = <0x0 0x3210000 0x0 0x10000>, 1033071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1034071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1035071f7855SPeng Ma interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1036*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1037*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1038071f7855SPeng Ma dma-coherent; 1039071f7855SPeng Ma status = "disabled"; 1040071f7855SPeng Ma }; 1041071f7855SPeng Ma 1042071f7855SPeng Ma sata2: sata@3220000 { 1043071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1044071f7855SPeng Ma reg = <0x0 0x3220000 0x0 0x10000>, 1045071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1046071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1047071f7855SPeng Ma interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1048*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1049*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1050071f7855SPeng Ma dma-coherent; 1051071f7855SPeng Ma status = "disabled"; 1052071f7855SPeng Ma }; 1053071f7855SPeng Ma 1054071f7855SPeng Ma sata3: sata@3230000 { 1055071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 1056071f7855SPeng Ma reg = <0x0 0x3230000 0x0 0x10000>, 1057071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 1058071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 1059071f7855SPeng Ma interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1060*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1061*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 1062071f7855SPeng Ma dma-coherent; 1063071f7855SPeng Ma status = "disabled"; 1064071f7855SPeng Ma }; 1065071f7855SPeng Ma 1066f7d48ffcSWasim Khan pcie1: pcie@3400000 { 1067b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1068b1ad0e7dSHou Zhiqiang reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 106966dfd959SWasim Khan 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1070b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1071b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1072b1ad0e7dSHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1073b1ad0e7dSHou Zhiqiang <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1074b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1075b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1076b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1077b1ad0e7dSHou Zhiqiang device_type = "pci"; 1078b1ad0e7dSHou Zhiqiang dma-coherent; 1079b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1080b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1081b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1082b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1083b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1084b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1085b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1086b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1087b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1088b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1089b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1090f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1091b1ad0e7dSHou Zhiqiang status = "disabled"; 1092b1ad0e7dSHou Zhiqiang }; 1093b1ad0e7dSHou Zhiqiang 1094f7d48ffcSWasim Khan pcie2: pcie@3500000 { 1095b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1096b1ad0e7dSHou Zhiqiang reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 109766dfd959SWasim Khan 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1098b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1099b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1100b1ad0e7dSHou Zhiqiang <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1101b1ad0e7dSHou Zhiqiang <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1102b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1103b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1104b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1105b1ad0e7dSHou Zhiqiang device_type = "pci"; 1106b1ad0e7dSHou Zhiqiang dma-coherent; 1107b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1108b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1109b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1110b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1111b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1112b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1113b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1114b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1115b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1116b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1117b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1118f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1119b1ad0e7dSHou Zhiqiang status = "disabled"; 1120b1ad0e7dSHou Zhiqiang }; 1121b1ad0e7dSHou Zhiqiang 1122f7d48ffcSWasim Khan pcie3: pcie@3600000 { 1123b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1124b1ad0e7dSHou Zhiqiang reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 112566dfd959SWasim Khan 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1126b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1127b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1128b1ad0e7dSHou Zhiqiang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1129b1ad0e7dSHou Zhiqiang <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1130b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1131b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1132b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1133b1ad0e7dSHou Zhiqiang device_type = "pci"; 1134b1ad0e7dSHou Zhiqiang dma-coherent; 1135b1ad0e7dSHou Zhiqiang apio-wins = <256>; 1136b1ad0e7dSHou Zhiqiang ppio-wins = <24>; 1137b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1138b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1139b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1140b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1141b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1142b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1143b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1144b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1145b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1146f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1147b1ad0e7dSHou Zhiqiang status = "disabled"; 1148b1ad0e7dSHou Zhiqiang }; 1149b1ad0e7dSHou Zhiqiang 1150f7d48ffcSWasim Khan pcie4: pcie@3700000 { 1151b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1152b1ad0e7dSHou Zhiqiang reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 115366dfd959SWasim Khan 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1154b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1155b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1156b1ad0e7dSHou Zhiqiang <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1157b1ad0e7dSHou Zhiqiang <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1158b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1159b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1160b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1161b1ad0e7dSHou Zhiqiang device_type = "pci"; 1162b1ad0e7dSHou Zhiqiang dma-coherent; 1163b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1164b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1165b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1166b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1167b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1168b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1169b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1170b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1171b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1172b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1173b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1174f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1175b1ad0e7dSHou Zhiqiang status = "disabled"; 1176b1ad0e7dSHou Zhiqiang }; 1177b1ad0e7dSHou Zhiqiang 1178f7d48ffcSWasim Khan pcie5: pcie@3800000 { 1179b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1180b1ad0e7dSHou Zhiqiang reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ 118166dfd959SWasim Khan 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1182b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1183b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1184b1ad0e7dSHou Zhiqiang <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1185b1ad0e7dSHou Zhiqiang <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1186b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1187b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1188b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1189b1ad0e7dSHou Zhiqiang device_type = "pci"; 1190b1ad0e7dSHou Zhiqiang dma-coherent; 1191b1ad0e7dSHou Zhiqiang apio-wins = <256>; 1192b1ad0e7dSHou Zhiqiang ppio-wins = <24>; 1193b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1194b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1195b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1196b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1197b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1198b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1199b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1200b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1201b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1202f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1203b1ad0e7dSHou Zhiqiang status = "disabled"; 1204b1ad0e7dSHou Zhiqiang }; 1205b1ad0e7dSHou Zhiqiang 1206f7d48ffcSWasim Khan pcie6: pcie@3900000 { 1207b1ad0e7dSHou Zhiqiang compatible = "fsl,lx2160a-pcie"; 1208b1ad0e7dSHou Zhiqiang reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ 120966dfd959SWasim Khan 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1210b1ad0e7dSHou Zhiqiang reg-names = "csr_axi_slave", "config_axi_slave"; 1211b1ad0e7dSHou Zhiqiang interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1212b1ad0e7dSHou Zhiqiang <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1213b1ad0e7dSHou Zhiqiang <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1214b1ad0e7dSHou Zhiqiang interrupt-names = "aer", "pme", "intr"; 1215b1ad0e7dSHou Zhiqiang #address-cells = <3>; 1216b1ad0e7dSHou Zhiqiang #size-cells = <2>; 1217b1ad0e7dSHou Zhiqiang device_type = "pci"; 1218b1ad0e7dSHou Zhiqiang dma-coherent; 1219b1ad0e7dSHou Zhiqiang apio-wins = <8>; 1220b1ad0e7dSHou Zhiqiang ppio-wins = <8>; 1221b1ad0e7dSHou Zhiqiang bus-range = <0x0 0xff>; 1222b1ad0e7dSHou Zhiqiang ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1223b1ad0e7dSHou Zhiqiang msi-parent = <&its>; 1224b1ad0e7dSHou Zhiqiang #interrupt-cells = <1>; 1225b1ad0e7dSHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 1226b1ad0e7dSHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1227b1ad0e7dSHou Zhiqiang <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1228b1ad0e7dSHou Zhiqiang <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1229b1ad0e7dSHou Zhiqiang <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1230f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1231b1ad0e7dSHou Zhiqiang status = "disabled"; 1232b1ad0e7dSHou Zhiqiang }; 1233b1ad0e7dSHou Zhiqiang 1234d548c217SVabhav Sharma smmu: iommu@5000000 { 1235d548c217SVabhav Sharma compatible = "arm,mmu-500"; 1236d548c217SVabhav Sharma reg = <0 0x5000000 0 0x800000>; 1237d548c217SVabhav Sharma #iommu-cells = <1>; 1238d548c217SVabhav Sharma #global-interrupts = <14>; 1239d548c217SVabhav Sharma // global secure fault 1240d548c217SVabhav Sharma interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1241d548c217SVabhav Sharma // combined secure 1242d548c217SVabhav Sharma <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1243d548c217SVabhav Sharma // global non-secure fault 1244d548c217SVabhav Sharma <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1245d548c217SVabhav Sharma // combined non-secure 1246d548c217SVabhav Sharma <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1247d548c217SVabhav Sharma // performance counter interrupts 0-9 1248d548c217SVabhav Sharma <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1249d548c217SVabhav Sharma <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1250d548c217SVabhav Sharma <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1251d548c217SVabhav Sharma <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1252d548c217SVabhav Sharma <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1253d548c217SVabhav Sharma <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1254d548c217SVabhav Sharma <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1255d548c217SVabhav Sharma <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1256d548c217SVabhav Sharma <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1257d548c217SVabhav Sharma <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1258d548c217SVabhav Sharma // per context interrupt, 64 interrupts 1259d548c217SVabhav Sharma <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1260d548c217SVabhav Sharma <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1261d548c217SVabhav Sharma <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1262d548c217SVabhav Sharma <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1263d548c217SVabhav Sharma <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1264d548c217SVabhav Sharma <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1265d548c217SVabhav Sharma <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1266d548c217SVabhav Sharma <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1267d548c217SVabhav Sharma <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1268d548c217SVabhav Sharma <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1269d548c217SVabhav Sharma <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1270d548c217SVabhav Sharma <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1271d548c217SVabhav Sharma <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1272d548c217SVabhav Sharma <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1273d548c217SVabhav Sharma <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1274d548c217SVabhav Sharma <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1275d548c217SVabhav Sharma <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1276d548c217SVabhav Sharma <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1277d548c217SVabhav Sharma <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1278d548c217SVabhav Sharma <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1279d548c217SVabhav Sharma <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1280d548c217SVabhav Sharma <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1281d548c217SVabhav Sharma <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1282d548c217SVabhav Sharma <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1283d548c217SVabhav Sharma <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1284d548c217SVabhav Sharma <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1285d548c217SVabhav Sharma <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1286d548c217SVabhav Sharma <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1287d548c217SVabhav Sharma <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1288d548c217SVabhav Sharma <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1289d548c217SVabhav Sharma <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1290d548c217SVabhav Sharma <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1291d548c217SVabhav Sharma <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1292d548c217SVabhav Sharma <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1293d548c217SVabhav Sharma <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1294d548c217SVabhav Sharma <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1295d548c217SVabhav Sharma <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1296d548c217SVabhav Sharma <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1297d548c217SVabhav Sharma <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1298d548c217SVabhav Sharma <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1299d548c217SVabhav Sharma <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1300d548c217SVabhav Sharma <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1301d548c217SVabhav Sharma <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1302d548c217SVabhav Sharma <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1303d548c217SVabhav Sharma <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1304d548c217SVabhav Sharma <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1305d548c217SVabhav Sharma <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1306d548c217SVabhav Sharma <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1307d548c217SVabhav Sharma <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1308d548c217SVabhav Sharma <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1309d548c217SVabhav Sharma <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1310d548c217SVabhav Sharma <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1311d548c217SVabhav Sharma <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1312d548c217SVabhav Sharma <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1313d548c217SVabhav Sharma <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1314d548c217SVabhav Sharma <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1315d548c217SVabhav Sharma <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1316d548c217SVabhav Sharma <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1317d548c217SVabhav Sharma <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1318d548c217SVabhav Sharma <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1319d548c217SVabhav Sharma <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1320d548c217SVabhav Sharma <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1321d548c217SVabhav Sharma <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1322d548c217SVabhav Sharma <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1323d548c217SVabhav Sharma dma-coherent; 1324d548c217SVabhav Sharma }; 1325703c5e40SIoana Ciocoi Radulescu 1326546d92d3SIoana Ciornei console@8340020 { 1327546d92d3SIoana Ciornei compatible = "fsl,dpaa2-console"; 1328546d92d3SIoana Ciornei reg = <0x00000000 0x08340020 0 0x2>; 1329546d92d3SIoana Ciornei }; 1330546d92d3SIoana Ciornei 1331fe844f19SYangbo Lu ptp-timer@8b95000 { 1332fe844f19SYangbo Lu compatible = "fsl,dpaa2-ptp"; 1333fe844f19SYangbo Lu reg = <0x0 0x8b95000 0x0 0x100>; 1334*8e9f7797SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1335*8e9f7797SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 1336fe844f19SYangbo Lu little-endian; 1337fe844f19SYangbo Lu fsl,extts-fifo; 1338fe844f19SYangbo Lu }; 1339fe844f19SYangbo Lu 13406e1b8faeSIoana Ciornei /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 13416e1b8faeSIoana Ciornei emdio1: mdio@8b96000 { 13426e1b8faeSIoana Ciornei compatible = "fsl,fman-memac-mdio"; 13436e1b8faeSIoana Ciornei reg = <0x0 0x8b96000 0x0 0x1000>; 13446e1b8faeSIoana Ciornei interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 13456e1b8faeSIoana Ciornei #address-cells = <1>; 13466e1b8faeSIoana Ciornei #size-cells = <0>; 13476e1b8faeSIoana Ciornei little-endian; 13486e1b8faeSIoana Ciornei status = "disabled"; 13496e1b8faeSIoana Ciornei }; 13506e1b8faeSIoana Ciornei 13515705b9dcSRussell King emdio2: mdio@8b97000 { 13525705b9dcSRussell King compatible = "fsl,fman-memac-mdio"; 13535705b9dcSRussell King reg = <0x0 0x8b97000 0x0 0x1000>; 13545705b9dcSRussell King interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 13555705b9dcSRussell King little-endian; 13565705b9dcSRussell King #address-cells = <1>; 13575705b9dcSRussell King #size-cells = <0>; 13585705b9dcSRussell King status = "disabled"; 13595705b9dcSRussell King }; 13605705b9dcSRussell King 1361f94cfe32SIoana Ciornei pcs_mdio1: mdio@8c07000 { 1362f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1363f94cfe32SIoana Ciornei reg = <0x0 0x8c07000 0x0 0x1000>; 1364f94cfe32SIoana Ciornei little-endian; 1365f94cfe32SIoana Ciornei #address-cells = <1>; 1366f94cfe32SIoana Ciornei #size-cells = <0>; 1367f94cfe32SIoana Ciornei status = "disabled"; 1368f94cfe32SIoana Ciornei 1369f94cfe32SIoana Ciornei pcs1: ethernet-phy@0 { 1370f94cfe32SIoana Ciornei reg = <0>; 1371f94cfe32SIoana Ciornei }; 1372f94cfe32SIoana Ciornei }; 1373f94cfe32SIoana Ciornei 1374f94cfe32SIoana Ciornei pcs_mdio2: mdio@8c0b000 { 1375f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1376f94cfe32SIoana Ciornei reg = <0x0 0x8c0b000 0x0 0x1000>; 1377f94cfe32SIoana Ciornei little-endian; 1378f94cfe32SIoana Ciornei #address-cells = <1>; 1379f94cfe32SIoana Ciornei #size-cells = <0>; 1380f94cfe32SIoana Ciornei status = "disabled"; 1381f94cfe32SIoana Ciornei 1382f94cfe32SIoana Ciornei pcs2: ethernet-phy@0 { 1383f94cfe32SIoana Ciornei reg = <0>; 1384f94cfe32SIoana Ciornei }; 1385f94cfe32SIoana Ciornei }; 1386f94cfe32SIoana Ciornei 1387f94cfe32SIoana Ciornei pcs_mdio3: mdio@8c0f000 { 1388f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1389f94cfe32SIoana Ciornei reg = <0x0 0x8c0f000 0x0 0x1000>; 1390f94cfe32SIoana Ciornei little-endian; 1391f94cfe32SIoana Ciornei #address-cells = <1>; 1392f94cfe32SIoana Ciornei #size-cells = <0>; 1393f94cfe32SIoana Ciornei status = "disabled"; 1394f94cfe32SIoana Ciornei 1395f94cfe32SIoana Ciornei pcs3: ethernet-phy@0 { 1396f94cfe32SIoana Ciornei reg = <0>; 1397f94cfe32SIoana Ciornei }; 1398f94cfe32SIoana Ciornei }; 1399f94cfe32SIoana Ciornei 1400f94cfe32SIoana Ciornei pcs_mdio4: mdio@8c13000 { 1401f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1402f94cfe32SIoana Ciornei reg = <0x0 0x8c13000 0x0 0x1000>; 1403f94cfe32SIoana Ciornei little-endian; 1404f94cfe32SIoana Ciornei #address-cells = <1>; 1405f94cfe32SIoana Ciornei #size-cells = <0>; 1406f94cfe32SIoana Ciornei status = "disabled"; 1407f94cfe32SIoana Ciornei 1408f94cfe32SIoana Ciornei pcs4: ethernet-phy@0 { 1409f94cfe32SIoana Ciornei reg = <0>; 1410f94cfe32SIoana Ciornei }; 1411f94cfe32SIoana Ciornei }; 1412f94cfe32SIoana Ciornei 1413f94cfe32SIoana Ciornei pcs_mdio5: mdio@8c17000 { 1414f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1415f94cfe32SIoana Ciornei reg = <0x0 0x8c17000 0x0 0x1000>; 1416f94cfe32SIoana Ciornei little-endian; 1417f94cfe32SIoana Ciornei #address-cells = <1>; 1418f94cfe32SIoana Ciornei #size-cells = <0>; 1419f94cfe32SIoana Ciornei status = "disabled"; 1420f94cfe32SIoana Ciornei 1421f94cfe32SIoana Ciornei pcs5: ethernet-phy@0 { 1422f94cfe32SIoana Ciornei reg = <0>; 1423f94cfe32SIoana Ciornei }; 1424f94cfe32SIoana Ciornei }; 1425f94cfe32SIoana Ciornei 1426f94cfe32SIoana Ciornei pcs_mdio6: mdio@8c1b000 { 1427f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1428f94cfe32SIoana Ciornei reg = <0x0 0x8c1b000 0x0 0x1000>; 1429f94cfe32SIoana Ciornei little-endian; 1430f94cfe32SIoana Ciornei #address-cells = <1>; 1431f94cfe32SIoana Ciornei #size-cells = <0>; 1432f94cfe32SIoana Ciornei status = "disabled"; 1433f94cfe32SIoana Ciornei 1434f94cfe32SIoana Ciornei pcs6: ethernet-phy@0 { 1435f94cfe32SIoana Ciornei reg = <0>; 1436f94cfe32SIoana Ciornei }; 1437f94cfe32SIoana Ciornei }; 1438f94cfe32SIoana Ciornei 1439f94cfe32SIoana Ciornei pcs_mdio7: mdio@8c1f000 { 1440f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1441f94cfe32SIoana Ciornei reg = <0x0 0x8c1f000 0x0 0x1000>; 1442f94cfe32SIoana Ciornei little-endian; 1443f94cfe32SIoana Ciornei #address-cells = <1>; 1444f94cfe32SIoana Ciornei #size-cells = <0>; 1445f94cfe32SIoana Ciornei status = "disabled"; 1446f94cfe32SIoana Ciornei 1447f94cfe32SIoana Ciornei pcs7: ethernet-phy@0 { 1448f94cfe32SIoana Ciornei reg = <0>; 1449f94cfe32SIoana Ciornei }; 1450f94cfe32SIoana Ciornei }; 1451f94cfe32SIoana Ciornei 1452f94cfe32SIoana Ciornei pcs_mdio8: mdio@8c23000 { 1453f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1454f94cfe32SIoana Ciornei reg = <0x0 0x8c23000 0x0 0x1000>; 1455f94cfe32SIoana Ciornei little-endian; 1456f94cfe32SIoana Ciornei #address-cells = <1>; 1457f94cfe32SIoana Ciornei #size-cells = <0>; 1458f94cfe32SIoana Ciornei status = "disabled"; 1459f94cfe32SIoana Ciornei 1460f94cfe32SIoana Ciornei pcs8: ethernet-phy@0 { 1461f94cfe32SIoana Ciornei reg = <0>; 1462f94cfe32SIoana Ciornei }; 1463f94cfe32SIoana Ciornei }; 1464f94cfe32SIoana Ciornei 1465f94cfe32SIoana Ciornei pcs_mdio9: mdio@8c27000 { 1466f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1467f94cfe32SIoana Ciornei reg = <0x0 0x8c27000 0x0 0x1000>; 1468f94cfe32SIoana Ciornei little-endian; 1469f94cfe32SIoana Ciornei #address-cells = <1>; 1470f94cfe32SIoana Ciornei #size-cells = <0>; 1471f94cfe32SIoana Ciornei status = "disabled"; 1472f94cfe32SIoana Ciornei 1473f94cfe32SIoana Ciornei pcs9: ethernet-phy@0 { 1474f94cfe32SIoana Ciornei reg = <0>; 1475f94cfe32SIoana Ciornei }; 1476f94cfe32SIoana Ciornei }; 1477f94cfe32SIoana Ciornei 1478f94cfe32SIoana Ciornei pcs_mdio10: mdio@8c2b000 { 1479f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1480f94cfe32SIoana Ciornei reg = <0x0 0x8c2b000 0x0 0x1000>; 1481f94cfe32SIoana Ciornei little-endian; 1482f94cfe32SIoana Ciornei #address-cells = <1>; 1483f94cfe32SIoana Ciornei #size-cells = <0>; 1484f94cfe32SIoana Ciornei status = "disabled"; 1485f94cfe32SIoana Ciornei 1486f94cfe32SIoana Ciornei pcs10: ethernet-phy@0 { 1487f94cfe32SIoana Ciornei reg = <0>; 1488f94cfe32SIoana Ciornei }; 1489f94cfe32SIoana Ciornei }; 1490f94cfe32SIoana Ciornei 1491f94cfe32SIoana Ciornei pcs_mdio11: mdio@8c2f000 { 1492f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1493f94cfe32SIoana Ciornei reg = <0x0 0x8c2f000 0x0 0x1000>; 1494f94cfe32SIoana Ciornei little-endian; 1495f94cfe32SIoana Ciornei #address-cells = <1>; 1496f94cfe32SIoana Ciornei #size-cells = <0>; 1497f94cfe32SIoana Ciornei status = "disabled"; 1498f94cfe32SIoana Ciornei 1499f94cfe32SIoana Ciornei pcs11: ethernet-phy@0 { 1500f94cfe32SIoana Ciornei reg = <0>; 1501f94cfe32SIoana Ciornei }; 1502f94cfe32SIoana Ciornei }; 1503f94cfe32SIoana Ciornei 1504f94cfe32SIoana Ciornei pcs_mdio12: mdio@8c33000 { 1505f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1506f94cfe32SIoana Ciornei reg = <0x0 0x8c33000 0x0 0x1000>; 1507f94cfe32SIoana Ciornei little-endian; 1508f94cfe32SIoana Ciornei #address-cells = <1>; 1509f94cfe32SIoana Ciornei #size-cells = <0>; 1510f94cfe32SIoana Ciornei status = "disabled"; 1511f94cfe32SIoana Ciornei 1512f94cfe32SIoana Ciornei pcs12: ethernet-phy@0 { 1513f94cfe32SIoana Ciornei reg = <0>; 1514f94cfe32SIoana Ciornei }; 1515f94cfe32SIoana Ciornei }; 1516f94cfe32SIoana Ciornei 1517f94cfe32SIoana Ciornei pcs_mdio13: mdio@8c37000 { 1518f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1519f94cfe32SIoana Ciornei reg = <0x0 0x8c37000 0x0 0x1000>; 1520f94cfe32SIoana Ciornei little-endian; 1521f94cfe32SIoana Ciornei #address-cells = <1>; 1522f94cfe32SIoana Ciornei #size-cells = <0>; 1523f94cfe32SIoana Ciornei status = "disabled"; 1524f94cfe32SIoana Ciornei 1525f94cfe32SIoana Ciornei pcs13: ethernet-phy@0 { 1526f94cfe32SIoana Ciornei reg = <0>; 1527f94cfe32SIoana Ciornei }; 1528f94cfe32SIoana Ciornei }; 1529f94cfe32SIoana Ciornei 1530f94cfe32SIoana Ciornei pcs_mdio14: mdio@8c3b000 { 1531f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1532f94cfe32SIoana Ciornei reg = <0x0 0x8c3b000 0x0 0x1000>; 1533f94cfe32SIoana Ciornei little-endian; 1534f94cfe32SIoana Ciornei #address-cells = <1>; 1535f94cfe32SIoana Ciornei #size-cells = <0>; 1536f94cfe32SIoana Ciornei status = "disabled"; 1537f94cfe32SIoana Ciornei 1538f94cfe32SIoana Ciornei pcs14: ethernet-phy@0 { 1539f94cfe32SIoana Ciornei reg = <0>; 1540f94cfe32SIoana Ciornei }; 1541f94cfe32SIoana Ciornei }; 1542f94cfe32SIoana Ciornei 1543f94cfe32SIoana Ciornei pcs_mdio15: mdio@8c3f000 { 1544f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1545f94cfe32SIoana Ciornei reg = <0x0 0x8c3f000 0x0 0x1000>; 1546f94cfe32SIoana Ciornei little-endian; 1547f94cfe32SIoana Ciornei #address-cells = <1>; 1548f94cfe32SIoana Ciornei #size-cells = <0>; 1549f94cfe32SIoana Ciornei status = "disabled"; 1550f94cfe32SIoana Ciornei 1551f94cfe32SIoana Ciornei pcs15: ethernet-phy@0 { 1552f94cfe32SIoana Ciornei reg = <0>; 1553f94cfe32SIoana Ciornei }; 1554f94cfe32SIoana Ciornei }; 1555f94cfe32SIoana Ciornei 1556f94cfe32SIoana Ciornei pcs_mdio16: mdio@8c43000 { 1557f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1558f94cfe32SIoana Ciornei reg = <0x0 0x8c43000 0x0 0x1000>; 1559f94cfe32SIoana Ciornei little-endian; 1560f94cfe32SIoana Ciornei #address-cells = <1>; 1561f94cfe32SIoana Ciornei #size-cells = <0>; 1562f94cfe32SIoana Ciornei status = "disabled"; 1563f94cfe32SIoana Ciornei 1564f94cfe32SIoana Ciornei pcs16: ethernet-phy@0 { 1565f94cfe32SIoana Ciornei reg = <0>; 1566f94cfe32SIoana Ciornei }; 1567f94cfe32SIoana Ciornei }; 1568f94cfe32SIoana Ciornei 1569f94cfe32SIoana Ciornei pcs_mdio17: mdio@8c47000 { 1570f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1571f94cfe32SIoana Ciornei reg = <0x0 0x8c47000 0x0 0x1000>; 1572f94cfe32SIoana Ciornei little-endian; 1573f94cfe32SIoana Ciornei #address-cells = <1>; 1574f94cfe32SIoana Ciornei #size-cells = <0>; 1575f94cfe32SIoana Ciornei status = "disabled"; 1576f94cfe32SIoana Ciornei 1577f94cfe32SIoana Ciornei pcs17: ethernet-phy@0 { 1578f94cfe32SIoana Ciornei reg = <0>; 1579f94cfe32SIoana Ciornei }; 1580f94cfe32SIoana Ciornei }; 1581f94cfe32SIoana Ciornei 1582f94cfe32SIoana Ciornei pcs_mdio18: mdio@8c4b000 { 1583f94cfe32SIoana Ciornei compatible = "fsl,fman-memac-mdio"; 1584f94cfe32SIoana Ciornei reg = <0x0 0x8c4b000 0x0 0x1000>; 1585f94cfe32SIoana Ciornei little-endian; 1586f94cfe32SIoana Ciornei #address-cells = <1>; 1587f94cfe32SIoana Ciornei #size-cells = <0>; 1588f94cfe32SIoana Ciornei status = "disabled"; 1589f94cfe32SIoana Ciornei 1590f94cfe32SIoana Ciornei pcs18: ethernet-phy@0 { 1591f94cfe32SIoana Ciornei reg = <0>; 1592f94cfe32SIoana Ciornei }; 1593f94cfe32SIoana Ciornei }; 1594f94cfe32SIoana Ciornei 1595703c5e40SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 1596703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 1597703c5e40SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, 1598703c5e40SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; 1599703c5e40SIoana Ciocoi Radulescu msi-parent = <&its>; 1600703c5e40SIoana Ciocoi Radulescu /* iommu-map property is fixed up by u-boot */ 1601703c5e40SIoana Ciocoi Radulescu iommu-map = <0 &smmu 0 0>; 1602703c5e40SIoana Ciocoi Radulescu dma-coherent; 1603703c5e40SIoana Ciocoi Radulescu #address-cells = <3>; 1604703c5e40SIoana Ciocoi Radulescu #size-cells = <1>; 1605703c5e40SIoana Ciocoi Radulescu 1606703c5e40SIoana Ciocoi Radulescu /* 1607703c5e40SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 1608703c5e40SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 1609703c5e40SIoana Ciocoi Radulescu */ 1610703c5e40SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1611703c5e40SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1612703c5e40SIoana Ciocoi Radulescu 1613703c5e40SIoana Ciocoi Radulescu /* 1614703c5e40SIoana Ciocoi Radulescu * Define the maximum number of MACs present on the SoC. 1615703c5e40SIoana Ciocoi Radulescu */ 1616703c5e40SIoana Ciocoi Radulescu dpmacs { 1617703c5e40SIoana Ciocoi Radulescu #address-cells = <1>; 1618703c5e40SIoana Ciocoi Radulescu #size-cells = <0>; 1619703c5e40SIoana Ciocoi Radulescu 1620f94cfe32SIoana Ciornei dpmac1: ethernet@1 { 1621703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1622703c5e40SIoana Ciocoi Radulescu reg = <0x1>; 1623f94cfe32SIoana Ciornei pcs-handle = <&pcs1>; 1624703c5e40SIoana Ciocoi Radulescu }; 1625703c5e40SIoana Ciocoi Radulescu 1626f94cfe32SIoana Ciornei dpmac2: ethernet@2 { 1627703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1628703c5e40SIoana Ciocoi Radulescu reg = <0x2>; 1629f94cfe32SIoana Ciornei pcs-handle = <&pcs2>; 1630703c5e40SIoana Ciocoi Radulescu }; 1631703c5e40SIoana Ciocoi Radulescu 1632f94cfe32SIoana Ciornei dpmac3: ethernet@3 { 1633703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1634703c5e40SIoana Ciocoi Radulescu reg = <0x3>; 1635f94cfe32SIoana Ciornei pcs-handle = <&pcs3>; 1636703c5e40SIoana Ciocoi Radulescu }; 1637703c5e40SIoana Ciocoi Radulescu 1638f94cfe32SIoana Ciornei dpmac4: ethernet@4 { 1639703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1640703c5e40SIoana Ciocoi Radulescu reg = <0x4>; 1641f94cfe32SIoana Ciornei pcs-handle = <&pcs4>; 1642703c5e40SIoana Ciocoi Radulescu }; 1643703c5e40SIoana Ciocoi Radulescu 1644f94cfe32SIoana Ciornei dpmac5: ethernet@5 { 1645703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1646703c5e40SIoana Ciocoi Radulescu reg = <0x5>; 1647f94cfe32SIoana Ciornei pcs-handle = <&pcs5>; 1648703c5e40SIoana Ciocoi Radulescu }; 1649703c5e40SIoana Ciocoi Radulescu 1650f94cfe32SIoana Ciornei dpmac6: ethernet@6 { 1651703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1652703c5e40SIoana Ciocoi Radulescu reg = <0x6>; 1653f94cfe32SIoana Ciornei pcs-handle = <&pcs6>; 1654703c5e40SIoana Ciocoi Radulescu }; 1655703c5e40SIoana Ciocoi Radulescu 1656f94cfe32SIoana Ciornei dpmac7: ethernet@7 { 1657703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1658703c5e40SIoana Ciocoi Radulescu reg = <0x7>; 1659f94cfe32SIoana Ciornei pcs-handle = <&pcs7>; 1660703c5e40SIoana Ciocoi Radulescu }; 1661703c5e40SIoana Ciocoi Radulescu 1662f94cfe32SIoana Ciornei dpmac8: ethernet@8 { 1663703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1664703c5e40SIoana Ciocoi Radulescu reg = <0x8>; 1665f94cfe32SIoana Ciornei pcs-handle = <&pcs8>; 1666703c5e40SIoana Ciocoi Radulescu }; 1667703c5e40SIoana Ciocoi Radulescu 1668f94cfe32SIoana Ciornei dpmac9: ethernet@9 { 1669703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1670703c5e40SIoana Ciocoi Radulescu reg = <0x9>; 1671f94cfe32SIoana Ciornei pcs-handle = <&pcs9>; 1672703c5e40SIoana Ciocoi Radulescu }; 1673703c5e40SIoana Ciocoi Radulescu 1674f94cfe32SIoana Ciornei dpmac10: ethernet@a { 1675703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1676703c5e40SIoana Ciocoi Radulescu reg = <0xa>; 1677f94cfe32SIoana Ciornei pcs-handle = <&pcs10>; 1678703c5e40SIoana Ciocoi Radulescu }; 1679703c5e40SIoana Ciocoi Radulescu 1680f94cfe32SIoana Ciornei dpmac11: ethernet@b { 1681703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1682703c5e40SIoana Ciocoi Radulescu reg = <0xb>; 1683f94cfe32SIoana Ciornei pcs-handle = <&pcs11>; 1684703c5e40SIoana Ciocoi Radulescu }; 1685703c5e40SIoana Ciocoi Radulescu 1686f94cfe32SIoana Ciornei dpmac12: ethernet@c { 1687703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1688703c5e40SIoana Ciocoi Radulescu reg = <0xc>; 1689f94cfe32SIoana Ciornei pcs-handle = <&pcs12>; 1690703c5e40SIoana Ciocoi Radulescu }; 1691703c5e40SIoana Ciocoi Radulescu 1692f94cfe32SIoana Ciornei dpmac13: ethernet@d { 1693703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1694703c5e40SIoana Ciocoi Radulescu reg = <0xd>; 1695f94cfe32SIoana Ciornei pcs-handle = <&pcs13>; 1696703c5e40SIoana Ciocoi Radulescu }; 1697703c5e40SIoana Ciocoi Radulescu 1698f94cfe32SIoana Ciornei dpmac14: ethernet@e { 1699703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1700703c5e40SIoana Ciocoi Radulescu reg = <0xe>; 1701f94cfe32SIoana Ciornei pcs-handle = <&pcs14>; 1702703c5e40SIoana Ciocoi Radulescu }; 1703703c5e40SIoana Ciocoi Radulescu 1704f94cfe32SIoana Ciornei dpmac15: ethernet@f { 1705703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1706703c5e40SIoana Ciocoi Radulescu reg = <0xf>; 1707f94cfe32SIoana Ciornei pcs-handle = <&pcs15>; 1708703c5e40SIoana Ciocoi Radulescu }; 1709703c5e40SIoana Ciocoi Radulescu 1710f94cfe32SIoana Ciornei dpmac16: ethernet@10 { 1711703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1712703c5e40SIoana Ciocoi Radulescu reg = <0x10>; 1713f94cfe32SIoana Ciornei pcs-handle = <&pcs16>; 1714703c5e40SIoana Ciocoi Radulescu }; 1715703c5e40SIoana Ciocoi Radulescu 1716f94cfe32SIoana Ciornei dpmac17: ethernet@11 { 1717703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1718703c5e40SIoana Ciocoi Radulescu reg = <0x11>; 1719f94cfe32SIoana Ciornei pcs-handle = <&pcs17>; 1720703c5e40SIoana Ciocoi Radulescu }; 1721703c5e40SIoana Ciocoi Radulescu 1722f94cfe32SIoana Ciornei dpmac18: ethernet@12 { 1723703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 1724703c5e40SIoana Ciocoi Radulescu reg = <0x12>; 1725f94cfe32SIoana Ciornei pcs-handle = <&pcs18>; 1726703c5e40SIoana Ciocoi Radulescu }; 1727703c5e40SIoana Ciocoi Radulescu }; 1728703c5e40SIoana Ciocoi Radulescu }; 1729d548c217SVabhav Sharma }; 1730d548c217SVabhav Sharma}; 1731