1d548c217SVabhav Sharma// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2d548c217SVabhav Sharma// 3d548c217SVabhav Sharma// Device Tree Include file for Layerscape-LX2160A family SoC. 4d548c217SVabhav Sharma// 5d548c217SVabhav Sharma// Copyright 2018 NXP 6d548c217SVabhav Sharma 7d548c217SVabhav Sharma#include <dt-bindings/gpio/gpio.h> 8d548c217SVabhav Sharma#include <dt-bindings/interrupt-controller/arm-gic.h> 9d548c217SVabhav Sharma 10d548c217SVabhav Sharma/memreserve/ 0x80000000 0x00010000; 11d548c217SVabhav Sharma 12d548c217SVabhav Sharma/ { 13d548c217SVabhav Sharma compatible = "fsl,lx2160a"; 14d548c217SVabhav Sharma interrupt-parent = <&gic>; 15d548c217SVabhav Sharma #address-cells = <2>; 16d548c217SVabhav Sharma #size-cells = <2>; 17d548c217SVabhav Sharma 18d548c217SVabhav Sharma cpus { 19d548c217SVabhav Sharma #address-cells = <1>; 20d548c217SVabhav Sharma #size-cells = <0>; 21d548c217SVabhav Sharma 22d548c217SVabhav Sharma // 8 clusters having 2 Cortex-A72 cores each 23d548c217SVabhav Sharma cpu@0 { 24d548c217SVabhav Sharma device_type = "cpu"; 25d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 26d548c217SVabhav Sharma enable-method = "psci"; 27d548c217SVabhav Sharma reg = <0x0>; 28d548c217SVabhav Sharma clocks = <&clockgen 1 0>; 29d548c217SVabhav Sharma d-cache-size = <0x8000>; 30d548c217SVabhav Sharma d-cache-line-size = <64>; 31d548c217SVabhav Sharma d-cache-sets = <128>; 32d548c217SVabhav Sharma i-cache-size = <0xC000>; 33d548c217SVabhav Sharma i-cache-line-size = <64>; 34d548c217SVabhav Sharma i-cache-sets = <192>; 35d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 36d548c217SVabhav Sharma }; 37d548c217SVabhav Sharma 38d548c217SVabhav Sharma cpu@1 { 39d548c217SVabhav Sharma device_type = "cpu"; 40d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 41d548c217SVabhav Sharma enable-method = "psci"; 42d548c217SVabhav Sharma reg = <0x1>; 43d548c217SVabhav Sharma clocks = <&clockgen 1 0>; 44d548c217SVabhav Sharma d-cache-size = <0x8000>; 45d548c217SVabhav Sharma d-cache-line-size = <64>; 46d548c217SVabhav Sharma d-cache-sets = <128>; 47d548c217SVabhav Sharma i-cache-size = <0xC000>; 48d548c217SVabhav Sharma i-cache-line-size = <64>; 49d548c217SVabhav Sharma i-cache-sets = <192>; 50d548c217SVabhav Sharma next-level-cache = <&cluster0_l2>; 51d548c217SVabhav Sharma }; 52d548c217SVabhav Sharma 53d548c217SVabhav Sharma cpu@100 { 54d548c217SVabhav Sharma device_type = "cpu"; 55d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 56d548c217SVabhav Sharma enable-method = "psci"; 57d548c217SVabhav Sharma reg = <0x100>; 58d548c217SVabhav Sharma clocks = <&clockgen 1 1>; 59d548c217SVabhav Sharma d-cache-size = <0x8000>; 60d548c217SVabhav Sharma d-cache-line-size = <64>; 61d548c217SVabhav Sharma d-cache-sets = <128>; 62d548c217SVabhav Sharma i-cache-size = <0xC000>; 63d548c217SVabhav Sharma i-cache-line-size = <64>; 64d548c217SVabhav Sharma i-cache-sets = <192>; 65d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 66d548c217SVabhav Sharma }; 67d548c217SVabhav Sharma 68d548c217SVabhav Sharma cpu@101 { 69d548c217SVabhav Sharma device_type = "cpu"; 70d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 71d548c217SVabhav Sharma enable-method = "psci"; 72d548c217SVabhav Sharma reg = <0x101>; 73d548c217SVabhav Sharma clocks = <&clockgen 1 1>; 74d548c217SVabhav Sharma d-cache-size = <0x8000>; 75d548c217SVabhav Sharma d-cache-line-size = <64>; 76d548c217SVabhav Sharma d-cache-sets = <128>; 77d548c217SVabhav Sharma i-cache-size = <0xC000>; 78d548c217SVabhav Sharma i-cache-line-size = <64>; 79d548c217SVabhav Sharma i-cache-sets = <192>; 80d548c217SVabhav Sharma next-level-cache = <&cluster1_l2>; 81d548c217SVabhav Sharma }; 82d548c217SVabhav Sharma 83d548c217SVabhav Sharma cpu@200 { 84d548c217SVabhav Sharma device_type = "cpu"; 85d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 86d548c217SVabhav Sharma enable-method = "psci"; 87d548c217SVabhav Sharma reg = <0x200>; 88d548c217SVabhav Sharma clocks = <&clockgen 1 2>; 89d548c217SVabhav Sharma d-cache-size = <0x8000>; 90d548c217SVabhav Sharma d-cache-line-size = <64>; 91d548c217SVabhav Sharma d-cache-sets = <128>; 92d548c217SVabhav Sharma i-cache-size = <0xC000>; 93d548c217SVabhav Sharma i-cache-line-size = <64>; 94d548c217SVabhav Sharma i-cache-sets = <192>; 95d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 96d548c217SVabhav Sharma }; 97d548c217SVabhav Sharma 98d548c217SVabhav Sharma cpu@201 { 99d548c217SVabhav Sharma device_type = "cpu"; 100d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 101d548c217SVabhav Sharma enable-method = "psci"; 102d548c217SVabhav Sharma reg = <0x201>; 103d548c217SVabhav Sharma clocks = <&clockgen 1 2>; 104d548c217SVabhav Sharma d-cache-size = <0x8000>; 105d548c217SVabhav Sharma d-cache-line-size = <64>; 106d548c217SVabhav Sharma d-cache-sets = <128>; 107d548c217SVabhav Sharma i-cache-size = <0xC000>; 108d548c217SVabhav Sharma i-cache-line-size = <64>; 109d548c217SVabhav Sharma i-cache-sets = <192>; 110d548c217SVabhav Sharma next-level-cache = <&cluster2_l2>; 111d548c217SVabhav Sharma }; 112d548c217SVabhav Sharma 113d548c217SVabhav Sharma cpu@300 { 114d548c217SVabhav Sharma device_type = "cpu"; 115d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 116d548c217SVabhav Sharma enable-method = "psci"; 117d548c217SVabhav Sharma reg = <0x300>; 118d548c217SVabhav Sharma clocks = <&clockgen 1 3>; 119d548c217SVabhav Sharma d-cache-size = <0x8000>; 120d548c217SVabhav Sharma d-cache-line-size = <64>; 121d548c217SVabhav Sharma d-cache-sets = <128>; 122d548c217SVabhav Sharma i-cache-size = <0xC000>; 123d548c217SVabhav Sharma i-cache-line-size = <64>; 124d548c217SVabhav Sharma i-cache-sets = <192>; 125d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 126d548c217SVabhav Sharma }; 127d548c217SVabhav Sharma 128d548c217SVabhav Sharma cpu@301 { 129d548c217SVabhav Sharma device_type = "cpu"; 130d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 131d548c217SVabhav Sharma enable-method = "psci"; 132d548c217SVabhav Sharma reg = <0x301>; 133d548c217SVabhav Sharma clocks = <&clockgen 1 3>; 134d548c217SVabhav Sharma d-cache-size = <0x8000>; 135d548c217SVabhav Sharma d-cache-line-size = <64>; 136d548c217SVabhav Sharma d-cache-sets = <128>; 137d548c217SVabhav Sharma i-cache-size = <0xC000>; 138d548c217SVabhav Sharma i-cache-line-size = <64>; 139d548c217SVabhav Sharma i-cache-sets = <192>; 140d548c217SVabhav Sharma next-level-cache = <&cluster3_l2>; 141d548c217SVabhav Sharma }; 142d548c217SVabhav Sharma 143d548c217SVabhav Sharma cpu@400 { 144d548c217SVabhav Sharma device_type = "cpu"; 145d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 146d548c217SVabhav Sharma enable-method = "psci"; 147d548c217SVabhav Sharma reg = <0x400>; 148d548c217SVabhav Sharma clocks = <&clockgen 1 4>; 149d548c217SVabhav Sharma d-cache-size = <0x8000>; 150d548c217SVabhav Sharma d-cache-line-size = <64>; 151d548c217SVabhav Sharma d-cache-sets = <128>; 152d548c217SVabhav Sharma i-cache-size = <0xC000>; 153d548c217SVabhav Sharma i-cache-line-size = <64>; 154d548c217SVabhav Sharma i-cache-sets = <192>; 155d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 156d548c217SVabhav Sharma }; 157d548c217SVabhav Sharma 158d548c217SVabhav Sharma cpu@401 { 159d548c217SVabhav Sharma device_type = "cpu"; 160d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 161d548c217SVabhav Sharma enable-method = "psci"; 162d548c217SVabhav Sharma reg = <0x401>; 163d548c217SVabhav Sharma clocks = <&clockgen 1 4>; 164d548c217SVabhav Sharma d-cache-size = <0x8000>; 165d548c217SVabhav Sharma d-cache-line-size = <64>; 166d548c217SVabhav Sharma d-cache-sets = <128>; 167d548c217SVabhav Sharma i-cache-size = <0xC000>; 168d548c217SVabhav Sharma i-cache-line-size = <64>; 169d548c217SVabhav Sharma i-cache-sets = <192>; 170d548c217SVabhav Sharma next-level-cache = <&cluster4_l2>; 171d548c217SVabhav Sharma }; 172d548c217SVabhav Sharma 173d548c217SVabhav Sharma cpu@500 { 174d548c217SVabhav Sharma device_type = "cpu"; 175d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 176d548c217SVabhav Sharma enable-method = "psci"; 177d548c217SVabhav Sharma reg = <0x500>; 178d548c217SVabhav Sharma clocks = <&clockgen 1 5>; 179d548c217SVabhav Sharma d-cache-size = <0x8000>; 180d548c217SVabhav Sharma d-cache-line-size = <64>; 181d548c217SVabhav Sharma d-cache-sets = <128>; 182d548c217SVabhav Sharma i-cache-size = <0xC000>; 183d548c217SVabhav Sharma i-cache-line-size = <64>; 184d548c217SVabhav Sharma i-cache-sets = <192>; 185d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 186d548c217SVabhav Sharma }; 187d548c217SVabhav Sharma 188d548c217SVabhav Sharma cpu@501 { 189d548c217SVabhav Sharma device_type = "cpu"; 190d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 191d548c217SVabhav Sharma enable-method = "psci"; 192d548c217SVabhav Sharma reg = <0x501>; 193d548c217SVabhav Sharma clocks = <&clockgen 1 5>; 194d548c217SVabhav Sharma d-cache-size = <0x8000>; 195d548c217SVabhav Sharma d-cache-line-size = <64>; 196d548c217SVabhav Sharma d-cache-sets = <128>; 197d548c217SVabhav Sharma i-cache-size = <0xC000>; 198d548c217SVabhav Sharma i-cache-line-size = <64>; 199d548c217SVabhav Sharma i-cache-sets = <192>; 200d548c217SVabhav Sharma next-level-cache = <&cluster5_l2>; 201d548c217SVabhav Sharma }; 202d548c217SVabhav Sharma 203d548c217SVabhav Sharma cpu@600 { 204d548c217SVabhav Sharma device_type = "cpu"; 205d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 206d548c217SVabhav Sharma enable-method = "psci"; 207d548c217SVabhav Sharma reg = <0x600>; 208d548c217SVabhav Sharma clocks = <&clockgen 1 6>; 209d548c217SVabhav Sharma d-cache-size = <0x8000>; 210d548c217SVabhav Sharma d-cache-line-size = <64>; 211d548c217SVabhav Sharma d-cache-sets = <128>; 212d548c217SVabhav Sharma i-cache-size = <0xC000>; 213d548c217SVabhav Sharma i-cache-line-size = <64>; 214d548c217SVabhav Sharma i-cache-sets = <192>; 215d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 216d548c217SVabhav Sharma }; 217d548c217SVabhav Sharma 218d548c217SVabhav Sharma cpu@601 { 219d548c217SVabhav Sharma device_type = "cpu"; 220d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 221d548c217SVabhav Sharma enable-method = "psci"; 222d548c217SVabhav Sharma reg = <0x601>; 223d548c217SVabhav Sharma clocks = <&clockgen 1 6>; 224d548c217SVabhav Sharma d-cache-size = <0x8000>; 225d548c217SVabhav Sharma d-cache-line-size = <64>; 226d548c217SVabhav Sharma d-cache-sets = <128>; 227d548c217SVabhav Sharma i-cache-size = <0xC000>; 228d548c217SVabhav Sharma i-cache-line-size = <64>; 229d548c217SVabhav Sharma i-cache-sets = <192>; 230d548c217SVabhav Sharma next-level-cache = <&cluster6_l2>; 231d548c217SVabhav Sharma }; 232d548c217SVabhav Sharma 233d548c217SVabhav Sharma cpu@700 { 234d548c217SVabhav Sharma device_type = "cpu"; 235d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 236d548c217SVabhav Sharma enable-method = "psci"; 237d548c217SVabhav Sharma reg = <0x700>; 238d548c217SVabhav Sharma clocks = <&clockgen 1 7>; 239d548c217SVabhav Sharma d-cache-size = <0x8000>; 240d548c217SVabhav Sharma d-cache-line-size = <64>; 241d548c217SVabhav Sharma d-cache-sets = <128>; 242d548c217SVabhav Sharma i-cache-size = <0xC000>; 243d548c217SVabhav Sharma i-cache-line-size = <64>; 244d548c217SVabhav Sharma i-cache-sets = <192>; 245d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 246d548c217SVabhav Sharma }; 247d548c217SVabhav Sharma 248d548c217SVabhav Sharma cpu@701 { 249d548c217SVabhav Sharma device_type = "cpu"; 250d548c217SVabhav Sharma compatible = "arm,cortex-a72"; 251d548c217SVabhav Sharma enable-method = "psci"; 252d548c217SVabhav Sharma reg = <0x701>; 253d548c217SVabhav Sharma clocks = <&clockgen 1 7>; 254d548c217SVabhav Sharma d-cache-size = <0x8000>; 255d548c217SVabhav Sharma d-cache-line-size = <64>; 256d548c217SVabhav Sharma d-cache-sets = <128>; 257d548c217SVabhav Sharma i-cache-size = <0xC000>; 258d548c217SVabhav Sharma i-cache-line-size = <64>; 259d548c217SVabhav Sharma i-cache-sets = <192>; 260d548c217SVabhav Sharma next-level-cache = <&cluster7_l2>; 261d548c217SVabhav Sharma }; 262d548c217SVabhav Sharma 263d548c217SVabhav Sharma cluster0_l2: l2-cache0 { 264d548c217SVabhav Sharma compatible = "cache"; 265d548c217SVabhav Sharma cache-size = <0x100000>; 266d548c217SVabhav Sharma cache-line-size = <64>; 267d548c217SVabhav Sharma cache-sets = <1024>; 268d548c217SVabhav Sharma cache-level = <2>; 269d548c217SVabhav Sharma }; 270d548c217SVabhav Sharma 271d548c217SVabhav Sharma cluster1_l2: l2-cache1 { 272d548c217SVabhav Sharma compatible = "cache"; 273d548c217SVabhav Sharma cache-size = <0x100000>; 274d548c217SVabhav Sharma cache-line-size = <64>; 275d548c217SVabhav Sharma cache-sets = <1024>; 276d548c217SVabhav Sharma cache-level = <2>; 277d548c217SVabhav Sharma }; 278d548c217SVabhav Sharma 279d548c217SVabhav Sharma cluster2_l2: l2-cache2 { 280d548c217SVabhav Sharma compatible = "cache"; 281d548c217SVabhav Sharma cache-size = <0x100000>; 282d548c217SVabhav Sharma cache-line-size = <64>; 283d548c217SVabhav Sharma cache-sets = <1024>; 284d548c217SVabhav Sharma cache-level = <2>; 285d548c217SVabhav Sharma }; 286d548c217SVabhav Sharma 287d548c217SVabhav Sharma cluster3_l2: l2-cache3 { 288d548c217SVabhav Sharma compatible = "cache"; 289d548c217SVabhav Sharma cache-size = <0x100000>; 290d548c217SVabhav Sharma cache-line-size = <64>; 291d548c217SVabhav Sharma cache-sets = <1024>; 292d548c217SVabhav Sharma cache-level = <2>; 293d548c217SVabhav Sharma }; 294d548c217SVabhav Sharma 295d548c217SVabhav Sharma cluster4_l2: l2-cache4 { 296d548c217SVabhav Sharma compatible = "cache"; 297d548c217SVabhav Sharma cache-size = <0x100000>; 298d548c217SVabhav Sharma cache-line-size = <64>; 299d548c217SVabhav Sharma cache-sets = <1024>; 300d548c217SVabhav Sharma cache-level = <2>; 301d548c217SVabhav Sharma }; 302d548c217SVabhav Sharma 303d548c217SVabhav Sharma cluster5_l2: l2-cache5 { 304d548c217SVabhav Sharma compatible = "cache"; 305d548c217SVabhav Sharma cache-size = <0x100000>; 306d548c217SVabhav Sharma cache-line-size = <64>; 307d548c217SVabhav Sharma cache-sets = <1024>; 308d548c217SVabhav Sharma cache-level = <2>; 309d548c217SVabhav Sharma }; 310d548c217SVabhav Sharma 311d548c217SVabhav Sharma cluster6_l2: l2-cache6 { 312d548c217SVabhav Sharma compatible = "cache"; 313d548c217SVabhav Sharma cache-size = <0x100000>; 314d548c217SVabhav Sharma cache-line-size = <64>; 315d548c217SVabhav Sharma cache-sets = <1024>; 316d548c217SVabhav Sharma cache-level = <2>; 317d548c217SVabhav Sharma }; 318d548c217SVabhav Sharma 319d548c217SVabhav Sharma cluster7_l2: l2-cache7 { 320d548c217SVabhav Sharma compatible = "cache"; 321d548c217SVabhav Sharma cache-size = <0x100000>; 322d548c217SVabhav Sharma cache-line-size = <64>; 323d548c217SVabhav Sharma cache-sets = <1024>; 324d548c217SVabhav Sharma cache-level = <2>; 325d548c217SVabhav Sharma }; 326d548c217SVabhav Sharma }; 327d548c217SVabhav Sharma 328d548c217SVabhav Sharma gic: interrupt-controller@6000000 { 329d548c217SVabhav Sharma compatible = "arm,gic-v3"; 330d548c217SVabhav Sharma reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 331d548c217SVabhav Sharma <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 332d548c217SVabhav Sharma // SGI_base) 333d548c217SVabhav Sharma <0x0 0x0c0c0000 0 0x2000>, // GICC 334d548c217SVabhav Sharma <0x0 0x0c0d0000 0 0x1000>, // GICH 335d548c217SVabhav Sharma <0x0 0x0c0e0000 0 0x20000>; // GICV 336d548c217SVabhav Sharma #interrupt-cells = <3>; 337d548c217SVabhav Sharma #address-cells = <2>; 338d548c217SVabhav Sharma #size-cells = <2>; 339d548c217SVabhav Sharma ranges; 340d548c217SVabhav Sharma interrupt-controller; 341d548c217SVabhav Sharma interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 342d548c217SVabhav Sharma 343d548c217SVabhav Sharma its: gic-its@6020000 { 344d548c217SVabhav Sharma compatible = "arm,gic-v3-its"; 345d548c217SVabhav Sharma msi-controller; 346d548c217SVabhav Sharma reg = <0x0 0x6020000 0 0x20000>; 347d548c217SVabhav Sharma }; 348d548c217SVabhav Sharma }; 349d548c217SVabhav Sharma 350d548c217SVabhav Sharma timer { 351d548c217SVabhav Sharma compatible = "arm,armv8-timer"; 352d548c217SVabhav Sharma interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 353d548c217SVabhav Sharma <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 354d548c217SVabhav Sharma <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 355d548c217SVabhav Sharma <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 356d548c217SVabhav Sharma }; 357d548c217SVabhav Sharma 358d548c217SVabhav Sharma pmu { 359d548c217SVabhav Sharma compatible = "arm,cortex-a72-pmu"; 360d548c217SVabhav Sharma interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 361d548c217SVabhav Sharma }; 362d548c217SVabhav Sharma 363d548c217SVabhav Sharma psci { 364d548c217SVabhav Sharma compatible = "arm,psci-0.2"; 365d548c217SVabhav Sharma method = "smc"; 366d548c217SVabhav Sharma }; 367d548c217SVabhav Sharma 368d548c217SVabhav Sharma memory@80000000 { 369d548c217SVabhav Sharma // DRAM space - 1, size : 2 GB DRAM 370d548c217SVabhav Sharma device_type = "memory"; 371d548c217SVabhav Sharma reg = <0x00000000 0x80000000 0 0x80000000>; 372d548c217SVabhav Sharma }; 373d548c217SVabhav Sharma 374d548c217SVabhav Sharma ddr1: memory-controller@1080000 { 375d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 376d548c217SVabhav Sharma reg = <0x0 0x1080000 0x0 0x1000>; 377d548c217SVabhav Sharma interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 378d548c217SVabhav Sharma little-endian; 379d548c217SVabhav Sharma }; 380d548c217SVabhav Sharma 381d548c217SVabhav Sharma ddr2: memory-controller@1090000 { 382d548c217SVabhav Sharma compatible = "fsl,qoriq-memory-controller"; 383d548c217SVabhav Sharma reg = <0x0 0x1090000 0x0 0x1000>; 384d548c217SVabhav Sharma interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 385d548c217SVabhav Sharma little-endian; 386d548c217SVabhav Sharma }; 387d548c217SVabhav Sharma 388d548c217SVabhav Sharma // One clock unit-sysclk node which bootloader require during DT fix-up 389d548c217SVabhav Sharma sysclk: sysclk { 390d548c217SVabhav Sharma compatible = "fixed-clock"; 391d548c217SVabhav Sharma #clock-cells = <0>; 392d548c217SVabhav Sharma clock-frequency = <100000000>; // fixed up by bootloader 393d548c217SVabhav Sharma clock-output-names = "sysclk"; 394d548c217SVabhav Sharma }; 395d548c217SVabhav Sharma 396d548c217SVabhav Sharma soc { 397d548c217SVabhav Sharma compatible = "simple-bus"; 398d548c217SVabhav Sharma #address-cells = <2>; 399d548c217SVabhav Sharma #size-cells = <2>; 400d548c217SVabhav Sharma ranges; 4010154878dSIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 402d548c217SVabhav Sharma 403d548c217SVabhav Sharma crypto: crypto@8000000 { 404d548c217SVabhav Sharma compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 405d548c217SVabhav Sharma fsl,sec-era = <10>; 406d548c217SVabhav Sharma #address-cells = <1>; 407d548c217SVabhav Sharma #size-cells = <1>; 408d548c217SVabhav Sharma ranges = <0x0 0x00 0x8000000 0x100000>; 409d548c217SVabhav Sharma reg = <0x00 0x8000000 0x0 0x100000>; 410d548c217SVabhav Sharma interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 411d548c217SVabhav Sharma dma-coherent; 412d548c217SVabhav Sharma status = "disabled"; 413d548c217SVabhav Sharma 414d548c217SVabhav Sharma sec_jr0: jr@10000 { 415d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 416d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 417d548c217SVabhav Sharma reg = <0x10000 0x10000>; 418d548c217SVabhav Sharma interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 419d548c217SVabhav Sharma }; 420d548c217SVabhav Sharma 421d548c217SVabhav Sharma sec_jr1: jr@20000 { 422d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 423d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 424d548c217SVabhav Sharma reg = <0x20000 0x10000>; 425d548c217SVabhav Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 426d548c217SVabhav Sharma }; 427d548c217SVabhav Sharma 428d548c217SVabhav Sharma sec_jr2: jr@30000 { 429d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 430d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 431d548c217SVabhav Sharma reg = <0x30000 0x10000>; 432d548c217SVabhav Sharma interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 433d548c217SVabhav Sharma }; 434d548c217SVabhav Sharma 435d548c217SVabhav Sharma sec_jr3: jr@40000 { 436d548c217SVabhav Sharma compatible = "fsl,sec-v5.0-job-ring", 437d548c217SVabhav Sharma "fsl,sec-v4.0-job-ring"; 438d548c217SVabhav Sharma reg = <0x40000 0x10000>; 439d548c217SVabhav Sharma interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 440d548c217SVabhav Sharma }; 441d548c217SVabhav Sharma }; 442d548c217SVabhav Sharma 443d548c217SVabhav Sharma clockgen: clock-controller@1300000 { 444d548c217SVabhav Sharma compatible = "fsl,lx2160a-clockgen"; 445d548c217SVabhav Sharma reg = <0 0x1300000 0 0xa0000>; 446d548c217SVabhav Sharma #clock-cells = <2>; 447d548c217SVabhav Sharma clocks = <&sysclk>; 448d548c217SVabhav Sharma }; 449d548c217SVabhav Sharma 450d548c217SVabhav Sharma dcfg: syscon@1e00000 { 451d548c217SVabhav Sharma compatible = "fsl,lx2160a-dcfg", "syscon"; 452d548c217SVabhav Sharma reg = <0x0 0x1e00000 0x0 0x10000>; 453d548c217SVabhav Sharma little-endian; 454d548c217SVabhav Sharma }; 455d548c217SVabhav Sharma 456d548c217SVabhav Sharma i2c0: i2c@2000000 { 457d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 458d548c217SVabhav Sharma #address-cells = <1>; 459d548c217SVabhav Sharma #size-cells = <0>; 460d548c217SVabhav Sharma reg = <0x0 0x2000000 0x0 0x10000>; 461d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 462d548c217SVabhav Sharma clock-names = "i2c"; 463d548c217SVabhav Sharma clocks = <&clockgen 4 7>; 464d548c217SVabhav Sharma scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; 465d548c217SVabhav Sharma status = "disabled"; 466d548c217SVabhav Sharma }; 467d548c217SVabhav Sharma 468d548c217SVabhav Sharma i2c1: i2c@2010000 { 469d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 470d548c217SVabhav Sharma #address-cells = <1>; 471d548c217SVabhav Sharma #size-cells = <0>; 472d548c217SVabhav Sharma reg = <0x0 0x2010000 0x0 0x10000>; 473d548c217SVabhav Sharma interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 474d548c217SVabhav Sharma clock-names = "i2c"; 475d548c217SVabhav Sharma clocks = <&clockgen 4 7>; 476d548c217SVabhav Sharma status = "disabled"; 477d548c217SVabhav Sharma }; 478d548c217SVabhav Sharma 479d548c217SVabhav Sharma i2c2: i2c@2020000 { 480d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 481d548c217SVabhav Sharma #address-cells = <1>; 482d548c217SVabhav Sharma #size-cells = <0>; 483d548c217SVabhav Sharma reg = <0x0 0x2020000 0x0 0x10000>; 484d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 485d548c217SVabhav Sharma clock-names = "i2c"; 486d548c217SVabhav Sharma clocks = <&clockgen 4 7>; 487d548c217SVabhav Sharma status = "disabled"; 488d548c217SVabhav Sharma }; 489d548c217SVabhav Sharma 490d548c217SVabhav Sharma i2c3: i2c@2030000 { 491d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 492d548c217SVabhav Sharma #address-cells = <1>; 493d548c217SVabhav Sharma #size-cells = <0>; 494d548c217SVabhav Sharma reg = <0x0 0x2030000 0x0 0x10000>; 495d548c217SVabhav Sharma interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 496d548c217SVabhav Sharma clock-names = "i2c"; 497d548c217SVabhav Sharma clocks = <&clockgen 4 7>; 498d548c217SVabhav Sharma status = "disabled"; 499d548c217SVabhav Sharma }; 500d548c217SVabhav Sharma 501d548c217SVabhav Sharma i2c4: i2c@2040000 { 502d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 503d548c217SVabhav Sharma #address-cells = <1>; 504d548c217SVabhav Sharma #size-cells = <0>; 505d548c217SVabhav Sharma reg = <0x0 0x2040000 0x0 0x10000>; 506d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 507d548c217SVabhav Sharma clock-names = "i2c"; 508d548c217SVabhav Sharma clocks = <&clockgen 4 7>; 509d548c217SVabhav Sharma scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; 510d548c217SVabhav Sharma status = "disabled"; 511d548c217SVabhav Sharma }; 512d548c217SVabhav Sharma 513d548c217SVabhav Sharma i2c5: i2c@2050000 { 514d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 515d548c217SVabhav Sharma #address-cells = <1>; 516d548c217SVabhav Sharma #size-cells = <0>; 517d548c217SVabhav Sharma reg = <0x0 0x2050000 0x0 0x10000>; 518d548c217SVabhav Sharma interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 519d548c217SVabhav Sharma clock-names = "i2c"; 520d548c217SVabhav Sharma clocks = <&clockgen 4 7>; 521d548c217SVabhav Sharma status = "disabled"; 522d548c217SVabhav Sharma }; 523d548c217SVabhav Sharma 524d548c217SVabhav Sharma i2c6: i2c@2060000 { 525d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 526d548c217SVabhav Sharma #address-cells = <1>; 527d548c217SVabhav Sharma #size-cells = <0>; 528d548c217SVabhav Sharma reg = <0x0 0x2060000 0x0 0x10000>; 529d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 530d548c217SVabhav Sharma clock-names = "i2c"; 531d548c217SVabhav Sharma clocks = <&clockgen 4 7>; 532d548c217SVabhav Sharma status = "disabled"; 533d548c217SVabhav Sharma }; 534d548c217SVabhav Sharma 535d548c217SVabhav Sharma i2c7: i2c@2070000 { 536d548c217SVabhav Sharma compatible = "fsl,vf610-i2c"; 537d548c217SVabhav Sharma #address-cells = <1>; 538d548c217SVabhav Sharma #size-cells = <0>; 539d548c217SVabhav Sharma reg = <0x0 0x2070000 0x0 0x10000>; 540d548c217SVabhav Sharma interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 541d548c217SVabhav Sharma clock-names = "i2c"; 542d548c217SVabhav Sharma clocks = <&clockgen 4 7>; 543d548c217SVabhav Sharma status = "disabled"; 544d548c217SVabhav Sharma }; 545d548c217SVabhav Sharma 5461ffeef4eSYogesh Narayan Gaur fspi: spi@20c0000 { 5471ffeef4eSYogesh Narayan Gaur compatible = "nxp,lx2160a-fspi"; 5481ffeef4eSYogesh Narayan Gaur #address-cells = <1>; 5491ffeef4eSYogesh Narayan Gaur #size-cells = <0>; 5501ffeef4eSYogesh Narayan Gaur reg = <0x0 0x20c0000 0x0 0x10000>, 5511ffeef4eSYogesh Narayan Gaur <0x0 0x20000000 0x0 0x10000000>; 5521ffeef4eSYogesh Narayan Gaur reg-names = "fspi_base", "fspi_mmap"; 5531ffeef4eSYogesh Narayan Gaur interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 5541ffeef4eSYogesh Narayan Gaur clocks = <&clockgen 4 3>, <&clockgen 4 3>; 5551ffeef4eSYogesh Narayan Gaur clock-names = "fspi_en", "fspi"; 5561ffeef4eSYogesh Narayan Gaur status = "disabled"; 5571ffeef4eSYogesh Narayan Gaur }; 5581ffeef4eSYogesh Narayan Gaur 559d548c217SVabhav Sharma esdhc0: esdhc@2140000 { 560d548c217SVabhav Sharma compatible = "fsl,esdhc"; 561d548c217SVabhav Sharma reg = <0x0 0x2140000 0x0 0x10000>; 562d548c217SVabhav Sharma interrupts = <0 28 0x4>; /* Level high type */ 563d548c217SVabhav Sharma clocks = <&clockgen 4 1>; 564d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 565d548c217SVabhav Sharma sdhci,auto-cmd12; 566d548c217SVabhav Sharma little-endian; 567d548c217SVabhav Sharma bus-width = <4>; 568d548c217SVabhav Sharma status = "disabled"; 569d548c217SVabhav Sharma }; 570d548c217SVabhav Sharma 571d548c217SVabhav Sharma esdhc1: esdhc@2150000 { 572d548c217SVabhav Sharma compatible = "fsl,esdhc"; 573d548c217SVabhav Sharma reg = <0x0 0x2150000 0x0 0x10000>; 574d548c217SVabhav Sharma interrupts = <0 63 0x4>; /* Level high type */ 575d548c217SVabhav Sharma clocks = <&clockgen 4 1>; 576d548c217SVabhav Sharma voltage-ranges = <1800 1800 3300 3300>; 577d548c217SVabhav Sharma sdhci,auto-cmd12; 578d548c217SVabhav Sharma broken-cd; 579d548c217SVabhav Sharma little-endian; 580d548c217SVabhav Sharma bus-width = <4>; 581d548c217SVabhav Sharma status = "disabled"; 582d548c217SVabhav Sharma }; 583d548c217SVabhav Sharma 584d548c217SVabhav Sharma uart0: serial@21c0000 { 585d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 586d548c217SVabhav Sharma reg = <0x0 0x21c0000 0x0 0x1000>; 587d548c217SVabhav Sharma interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 588d548c217SVabhav Sharma current-speed = <115200>; 589d548c217SVabhav Sharma status = "disabled"; 590d548c217SVabhav Sharma }; 591d548c217SVabhav Sharma 592d548c217SVabhav Sharma uart1: serial@21d0000 { 593d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 594d548c217SVabhav Sharma reg = <0x0 0x21d0000 0x0 0x1000>; 595d548c217SVabhav Sharma interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 596d548c217SVabhav Sharma current-speed = <115200>; 597d548c217SVabhav Sharma status = "disabled"; 598d548c217SVabhav Sharma }; 599d548c217SVabhav Sharma 600d548c217SVabhav Sharma uart2: serial@21e0000 { 601d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 602d548c217SVabhav Sharma reg = <0x0 0x21e0000 0x0 0x1000>; 603d548c217SVabhav Sharma interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 604d548c217SVabhav Sharma current-speed = <115200>; 605d548c217SVabhav Sharma status = "disabled"; 606d548c217SVabhav Sharma }; 607d548c217SVabhav Sharma 608d548c217SVabhav Sharma uart3: serial@21f0000 { 609d548c217SVabhav Sharma compatible = "arm,sbsa-uart","arm,pl011"; 610d548c217SVabhav Sharma reg = <0x0 0x21f0000 0x0 0x1000>; 611d548c217SVabhav Sharma interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 612d548c217SVabhav Sharma current-speed = <115200>; 613d548c217SVabhav Sharma status = "disabled"; 614d548c217SVabhav Sharma }; 615d548c217SVabhav Sharma 616d548c217SVabhav Sharma gpio0: gpio@2300000 { 617d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 618d548c217SVabhav Sharma reg = <0x0 0x2300000 0x0 0x10000>; 619d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 620d548c217SVabhav Sharma gpio-controller; 621d548c217SVabhav Sharma little-endian; 622d548c217SVabhav Sharma #gpio-cells = <2>; 623d548c217SVabhav Sharma interrupt-controller; 624d548c217SVabhav Sharma #interrupt-cells = <2>; 625d548c217SVabhav Sharma }; 626d548c217SVabhav Sharma 627d548c217SVabhav Sharma gpio1: gpio@2310000 { 628d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 629d548c217SVabhav Sharma reg = <0x0 0x2310000 0x0 0x10000>; 630d548c217SVabhav Sharma interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 631d548c217SVabhav Sharma gpio-controller; 632d548c217SVabhav Sharma little-endian; 633d548c217SVabhav Sharma #gpio-cells = <2>; 634d548c217SVabhav Sharma interrupt-controller; 635d548c217SVabhav Sharma #interrupt-cells = <2>; 636d548c217SVabhav Sharma }; 637d548c217SVabhav Sharma 638d548c217SVabhav Sharma gpio2: gpio@2320000 { 639d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 640d548c217SVabhav Sharma reg = <0x0 0x2320000 0x0 0x10000>; 641d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 642d548c217SVabhav Sharma gpio-controller; 643d548c217SVabhav Sharma little-endian; 644d548c217SVabhav Sharma #gpio-cells = <2>; 645d548c217SVabhav Sharma interrupt-controller; 646d548c217SVabhav Sharma #interrupt-cells = <2>; 647d548c217SVabhav Sharma }; 648d548c217SVabhav Sharma 649d548c217SVabhav Sharma gpio3: gpio@2330000 { 650d548c217SVabhav Sharma compatible = "fsl,qoriq-gpio"; 651d548c217SVabhav Sharma reg = <0x0 0x2330000 0x0 0x10000>; 652d548c217SVabhav Sharma interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 653d548c217SVabhav Sharma gpio-controller; 654d548c217SVabhav Sharma little-endian; 655d548c217SVabhav Sharma #gpio-cells = <2>; 656d548c217SVabhav Sharma interrupt-controller; 657d548c217SVabhav Sharma #interrupt-cells = <2>; 658d548c217SVabhav Sharma }; 659d548c217SVabhav Sharma 660d548c217SVabhav Sharma watchdog@23a0000 { 661d548c217SVabhav Sharma compatible = "arm,sbsa-gwdt"; 662d548c217SVabhav Sharma reg = <0x0 0x23a0000 0 0x1000>, 663d548c217SVabhav Sharma <0x0 0x2390000 0 0x1000>; 664d548c217SVabhav Sharma interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 665d548c217SVabhav Sharma timeout-sec = <30>; 666d548c217SVabhav Sharma }; 667d548c217SVabhav Sharma 668d548c217SVabhav Sharma usb0: usb@3100000 { 669d548c217SVabhav Sharma compatible = "snps,dwc3"; 670d548c217SVabhav Sharma reg = <0x0 0x3100000 0x0 0x10000>; 671d548c217SVabhav Sharma interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 672d548c217SVabhav Sharma dr_mode = "host"; 673d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 674d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 6751000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 676d548c217SVabhav Sharma status = "disabled"; 677d548c217SVabhav Sharma }; 678d548c217SVabhav Sharma 679d548c217SVabhav Sharma usb1: usb@3110000 { 680d548c217SVabhav Sharma compatible = "snps,dwc3"; 681d548c217SVabhav Sharma reg = <0x0 0x3110000 0x0 0x10000>; 682d548c217SVabhav Sharma interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 683d548c217SVabhav Sharma dr_mode = "host"; 684d548c217SVabhav Sharma snps,quirk-frame-length-adjustment = <0x20>; 685d548c217SVabhav Sharma snps,dis_rxdet_inp3_quirk; 6861000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 687d548c217SVabhav Sharma status = "disabled"; 688d548c217SVabhav Sharma }; 689d548c217SVabhav Sharma 690071f7855SPeng Ma sata0: sata@3200000 { 691071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 692071f7855SPeng Ma reg = <0x0 0x3200000 0x0 0x10000>, 693071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 694071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 695071f7855SPeng Ma interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 696071f7855SPeng Ma clocks = <&clockgen 4 3>; 697071f7855SPeng Ma dma-coherent; 698071f7855SPeng Ma status = "disabled"; 699071f7855SPeng Ma }; 700071f7855SPeng Ma 701071f7855SPeng Ma sata1: sata@3210000 { 702071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 703071f7855SPeng Ma reg = <0x0 0x3210000 0x0 0x10000>, 704071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 705071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 706071f7855SPeng Ma interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 707071f7855SPeng Ma clocks = <&clockgen 4 3>; 708071f7855SPeng Ma dma-coherent; 709071f7855SPeng Ma status = "disabled"; 710071f7855SPeng Ma }; 711071f7855SPeng Ma 712071f7855SPeng Ma sata2: sata@3220000 { 713071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 714071f7855SPeng Ma reg = <0x0 0x3220000 0x0 0x10000>, 715071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 716071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 717071f7855SPeng Ma interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 718071f7855SPeng Ma clocks = <&clockgen 4 3>; 719071f7855SPeng Ma dma-coherent; 720071f7855SPeng Ma status = "disabled"; 721071f7855SPeng Ma }; 722071f7855SPeng Ma 723071f7855SPeng Ma sata3: sata@3230000 { 724071f7855SPeng Ma compatible = "fsl,lx2160a-ahci"; 725071f7855SPeng Ma reg = <0x0 0x3230000 0x0 0x10000>, 726071f7855SPeng Ma <0x7 0x100520 0x0 0x4>; 727071f7855SPeng Ma reg-names = "ahci", "sata-ecc"; 728071f7855SPeng Ma interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 729071f7855SPeng Ma clocks = <&clockgen 4 3>; 730071f7855SPeng Ma dma-coherent; 731071f7855SPeng Ma status = "disabled"; 732071f7855SPeng Ma }; 733071f7855SPeng Ma 734d548c217SVabhav Sharma smmu: iommu@5000000 { 735d548c217SVabhav Sharma compatible = "arm,mmu-500"; 736d548c217SVabhav Sharma reg = <0 0x5000000 0 0x800000>; 737d548c217SVabhav Sharma #iommu-cells = <1>; 738d548c217SVabhav Sharma #global-interrupts = <14>; 739d548c217SVabhav Sharma // global secure fault 740d548c217SVabhav Sharma interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 741d548c217SVabhav Sharma // combined secure 742d548c217SVabhav Sharma <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 743d548c217SVabhav Sharma // global non-secure fault 744d548c217SVabhav Sharma <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 745d548c217SVabhav Sharma // combined non-secure 746d548c217SVabhav Sharma <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 747d548c217SVabhav Sharma // performance counter interrupts 0-9 748d548c217SVabhav Sharma <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 749d548c217SVabhav Sharma <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 750d548c217SVabhav Sharma <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 751d548c217SVabhav Sharma <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 752d548c217SVabhav Sharma <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 753d548c217SVabhav Sharma <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 754d548c217SVabhav Sharma <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 755d548c217SVabhav Sharma <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 756d548c217SVabhav Sharma <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 757d548c217SVabhav Sharma <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 758d548c217SVabhav Sharma // per context interrupt, 64 interrupts 759d548c217SVabhav Sharma <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 760d548c217SVabhav Sharma <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 761d548c217SVabhav Sharma <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 762d548c217SVabhav Sharma <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 763d548c217SVabhav Sharma <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 764d548c217SVabhav Sharma <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 765d548c217SVabhav Sharma <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 766d548c217SVabhav Sharma <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 767d548c217SVabhav Sharma <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 768d548c217SVabhav Sharma <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 769d548c217SVabhav Sharma <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 770d548c217SVabhav Sharma <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 771d548c217SVabhav Sharma <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 772d548c217SVabhav Sharma <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 773d548c217SVabhav Sharma <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 774d548c217SVabhav Sharma <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 775d548c217SVabhav Sharma <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 776d548c217SVabhav Sharma <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 777d548c217SVabhav Sharma <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 778d548c217SVabhav Sharma <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 779d548c217SVabhav Sharma <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 780d548c217SVabhav Sharma <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 781d548c217SVabhav Sharma <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 782d548c217SVabhav Sharma <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 783d548c217SVabhav Sharma <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 784d548c217SVabhav Sharma <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 785d548c217SVabhav Sharma <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 786d548c217SVabhav Sharma <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 787d548c217SVabhav Sharma <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 788d548c217SVabhav Sharma <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 789d548c217SVabhav Sharma <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 790d548c217SVabhav Sharma <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 791d548c217SVabhav Sharma <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 792d548c217SVabhav Sharma <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 793d548c217SVabhav Sharma <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 794d548c217SVabhav Sharma <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 795d548c217SVabhav Sharma <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 796d548c217SVabhav Sharma <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 797d548c217SVabhav Sharma <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 798d548c217SVabhav Sharma <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 799d548c217SVabhav Sharma <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 800d548c217SVabhav Sharma <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 801d548c217SVabhav Sharma <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 802d548c217SVabhav Sharma <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 803d548c217SVabhav Sharma <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 804d548c217SVabhav Sharma <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 805d548c217SVabhav Sharma <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 806d548c217SVabhav Sharma <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 807d548c217SVabhav Sharma <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 808d548c217SVabhav Sharma <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 809d548c217SVabhav Sharma <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 810d548c217SVabhav Sharma <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 811d548c217SVabhav Sharma <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 812d548c217SVabhav Sharma <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 813d548c217SVabhav Sharma <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 814d548c217SVabhav Sharma <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 815d548c217SVabhav Sharma <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 816d548c217SVabhav Sharma <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 817d548c217SVabhav Sharma <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 818d548c217SVabhav Sharma <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 819d548c217SVabhav Sharma <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 820d548c217SVabhav Sharma <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 821d548c217SVabhav Sharma <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 822d548c217SVabhav Sharma <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 823d548c217SVabhav Sharma dma-coherent; 824d548c217SVabhav Sharma }; 825703c5e40SIoana Ciocoi Radulescu 826703c5e40SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 827703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 828703c5e40SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, 829703c5e40SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; 830703c5e40SIoana Ciocoi Radulescu msi-parent = <&its>; 831703c5e40SIoana Ciocoi Radulescu /* iommu-map property is fixed up by u-boot */ 832703c5e40SIoana Ciocoi Radulescu iommu-map = <0 &smmu 0 0>; 833703c5e40SIoana Ciocoi Radulescu dma-coherent; 834703c5e40SIoana Ciocoi Radulescu #address-cells = <3>; 835703c5e40SIoana Ciocoi Radulescu #size-cells = <1>; 836703c5e40SIoana Ciocoi Radulescu 837703c5e40SIoana Ciocoi Radulescu /* 838703c5e40SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 839703c5e40SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 840703c5e40SIoana Ciocoi Radulescu */ 841703c5e40SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 842703c5e40SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 843703c5e40SIoana Ciocoi Radulescu 844703c5e40SIoana Ciocoi Radulescu /* 845703c5e40SIoana Ciocoi Radulescu * Define the maximum number of MACs present on the SoC. 846703c5e40SIoana Ciocoi Radulescu */ 847703c5e40SIoana Ciocoi Radulescu dpmacs { 848703c5e40SIoana Ciocoi Radulescu #address-cells = <1>; 849703c5e40SIoana Ciocoi Radulescu #size-cells = <0>; 850703c5e40SIoana Ciocoi Radulescu 851703c5e40SIoana Ciocoi Radulescu dpmac1: dpmac@1 { 852703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 853703c5e40SIoana Ciocoi Radulescu reg = <0x1>; 854703c5e40SIoana Ciocoi Radulescu }; 855703c5e40SIoana Ciocoi Radulescu 856703c5e40SIoana Ciocoi Radulescu dpmac2: dpmac@2 { 857703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 858703c5e40SIoana Ciocoi Radulescu reg = <0x2>; 859703c5e40SIoana Ciocoi Radulescu }; 860703c5e40SIoana Ciocoi Radulescu 861703c5e40SIoana Ciocoi Radulescu dpmac3: dpmac@3 { 862703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 863703c5e40SIoana Ciocoi Radulescu reg = <0x3>; 864703c5e40SIoana Ciocoi Radulescu }; 865703c5e40SIoana Ciocoi Radulescu 866703c5e40SIoana Ciocoi Radulescu dpmac4: dpmac@4 { 867703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 868703c5e40SIoana Ciocoi Radulescu reg = <0x4>; 869703c5e40SIoana Ciocoi Radulescu }; 870703c5e40SIoana Ciocoi Radulescu 871703c5e40SIoana Ciocoi Radulescu dpmac5: dpmac@5 { 872703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 873703c5e40SIoana Ciocoi Radulescu reg = <0x5>; 874703c5e40SIoana Ciocoi Radulescu }; 875703c5e40SIoana Ciocoi Radulescu 876703c5e40SIoana Ciocoi Radulescu dpmac6: dpmac@6 { 877703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 878703c5e40SIoana Ciocoi Radulescu reg = <0x6>; 879703c5e40SIoana Ciocoi Radulescu }; 880703c5e40SIoana Ciocoi Radulescu 881703c5e40SIoana Ciocoi Radulescu dpmac7: dpmac@7 { 882703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 883703c5e40SIoana Ciocoi Radulescu reg = <0x7>; 884703c5e40SIoana Ciocoi Radulescu }; 885703c5e40SIoana Ciocoi Radulescu 886703c5e40SIoana Ciocoi Radulescu dpmac8: dpmac@8 { 887703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 888703c5e40SIoana Ciocoi Radulescu reg = <0x8>; 889703c5e40SIoana Ciocoi Radulescu }; 890703c5e40SIoana Ciocoi Radulescu 891703c5e40SIoana Ciocoi Radulescu dpmac9: dpmac@9 { 892703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 893703c5e40SIoana Ciocoi Radulescu reg = <0x9>; 894703c5e40SIoana Ciocoi Radulescu }; 895703c5e40SIoana Ciocoi Radulescu 896703c5e40SIoana Ciocoi Radulescu dpmac10: dpmac@a { 897703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 898703c5e40SIoana Ciocoi Radulescu reg = <0xa>; 899703c5e40SIoana Ciocoi Radulescu }; 900703c5e40SIoana Ciocoi Radulescu 901703c5e40SIoana Ciocoi Radulescu dpmac11: dpmac@b { 902703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 903703c5e40SIoana Ciocoi Radulescu reg = <0xb>; 904703c5e40SIoana Ciocoi Radulescu }; 905703c5e40SIoana Ciocoi Radulescu 906703c5e40SIoana Ciocoi Radulescu dpmac12: dpmac@c { 907703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 908703c5e40SIoana Ciocoi Radulescu reg = <0xc>; 909703c5e40SIoana Ciocoi Radulescu }; 910703c5e40SIoana Ciocoi Radulescu 911703c5e40SIoana Ciocoi Radulescu dpmac13: dpmac@d { 912703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 913703c5e40SIoana Ciocoi Radulescu reg = <0xd>; 914703c5e40SIoana Ciocoi Radulescu }; 915703c5e40SIoana Ciocoi Radulescu 916703c5e40SIoana Ciocoi Radulescu dpmac14: dpmac@e { 917703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 918703c5e40SIoana Ciocoi Radulescu reg = <0xe>; 919703c5e40SIoana Ciocoi Radulescu }; 920703c5e40SIoana Ciocoi Radulescu 921703c5e40SIoana Ciocoi Radulescu dpmac15: dpmac@f { 922703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 923703c5e40SIoana Ciocoi Radulescu reg = <0xf>; 924703c5e40SIoana Ciocoi Radulescu }; 925703c5e40SIoana Ciocoi Radulescu 926703c5e40SIoana Ciocoi Radulescu dpmac16: dpmac@10 { 927703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 928703c5e40SIoana Ciocoi Radulescu reg = <0x10>; 929703c5e40SIoana Ciocoi Radulescu }; 930703c5e40SIoana Ciocoi Radulescu 931703c5e40SIoana Ciocoi Radulescu dpmac17: dpmac@11 { 932703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 933703c5e40SIoana Ciocoi Radulescu reg = <0x11>; 934703c5e40SIoana Ciocoi Radulescu }; 935703c5e40SIoana Ciocoi Radulescu 936703c5e40SIoana Ciocoi Radulescu dpmac18: dpmac@12 { 937703c5e40SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 938703c5e40SIoana Ciocoi Radulescu reg = <0x12>; 939703c5e40SIoana Ciocoi Radulescu }; 940703c5e40SIoana Ciocoi Radulescu }; 941703c5e40SIoana Ciocoi Radulescu }; 942d548c217SVabhav Sharma }; 943d548c217SVabhav Sharma}; 944