1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Device Tree file for LX2160ARDB
4//
5// Copyright 2018 NXP
6
7/dts-v1/;
8
9#include "fsl-lx2160a.dtsi"
10
11/ {
12	model = "NXP Layerscape LX2160ARDB";
13	compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
14
15	aliases {
16		crypto = &crypto;
17		serial0 = &uart0;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	sb_3v3: regulator-sb3v3 {
25		compatible = "regulator-fixed";
26		regulator-name = "MC34717-3.3VSB";
27		regulator-min-microvolt = <3300000>;
28		regulator-max-microvolt = <3300000>;
29		regulator-boot-on;
30		regulator-always-on;
31	};
32};
33
34&crypto {
35	status = "okay";
36};
37
38&dpmac3 {
39	phy-handle = <&aquantia_phy1>;
40	phy-connection-type = "usxgmii";
41	managed = "in-band-status";
42};
43
44&dpmac4 {
45	phy-handle = <&aquantia_phy2>;
46	phy-connection-type = "usxgmii";
47	managed = "in-band-status";
48};
49
50&dpmac17 {
51	phy-handle = <&rgmii_phy1>;
52	phy-connection-type = "rgmii-id";
53};
54
55&dpmac18 {
56	phy-handle = <&rgmii_phy2>;
57	phy-connection-type = "rgmii-id";
58};
59
60&emdio1 {
61	status = "okay";
62
63	rgmii_phy1: ethernet-phy@1 {
64		/* AR8035 PHY */
65		compatible = "ethernet-phy-id004d.d072";
66		reg = <0x1>;
67		eee-broken-1000t;
68	};
69
70	rgmii_phy2: ethernet-phy@2 {
71		/* AR8035 PHY */
72		compatible = "ethernet-phy-id004d.d072";
73		reg = <0x2>;
74		eee-broken-1000t;
75	};
76
77	aquantia_phy1: ethernet-phy@4 {
78		/* AQR107 PHY */
79		compatible = "ethernet-phy-ieee802.3-c45";
80		reg = <0x4>;
81	};
82
83	aquantia_phy2: ethernet-phy@5 {
84		/* AQR107 PHY */
85		compatible = "ethernet-phy-ieee802.3-c45";
86		reg = <0x5>;
87	};
88};
89
90&esdhc0 {
91	sd-uhs-sdr104;
92	sd-uhs-sdr50;
93	sd-uhs-sdr25;
94	sd-uhs-sdr12;
95	status = "okay";
96};
97
98&esdhc1 {
99	mmc-hs200-1_8v;
100	mmc-hs400-1_8v;
101	bus-width = <8>;
102	status = "okay";
103};
104
105&fspi {
106	status = "okay";
107
108	mt35xu512aba0: flash@0 {
109		#address-cells = <1>;
110		#size-cells = <1>;
111		compatible = "jedec,spi-nor";
112		m25p,fast-read;
113		spi-max-frequency = <50000000>;
114		reg = <0>;
115		spi-rx-bus-width = <8>;
116		spi-tx-bus-width = <8>;
117	};
118
119	mt35xu512aba1: flash@1 {
120		#address-cells = <1>;
121		#size-cells = <1>;
122		compatible = "jedec,spi-nor";
123		m25p,fast-read;
124		spi-max-frequency = <50000000>;
125		reg = <1>;
126		spi-rx-bus-width = <8>;
127		spi-tx-bus-width = <8>;
128	};
129};
130
131&i2c0 {
132	status = "okay";
133
134	i2c-mux@77 {
135		compatible = "nxp,pca9547";
136		reg = <0x77>;
137		#address-cells = <1>;
138		#size-cells = <0>;
139
140		i2c@2 {
141			#address-cells = <1>;
142			#size-cells = <0>;
143			reg = <0x2>;
144
145			power-monitor@40 {
146				compatible = "ti,ina220";
147				reg = <0x40>;
148				shunt-resistor = <500>;
149			};
150		};
151
152		i2c@3 {
153			#address-cells = <1>;
154			#size-cells = <0>;
155			reg = <0x3>;
156
157			temperature-sensor@4c {
158				compatible = "nxp,sa56004";
159				reg = <0x4c>;
160				vcc-supply = <&sb_3v3>;
161			};
162
163			temperature-sensor@4d {
164				compatible = "nxp,sa56004";
165				reg = <0x4d>;
166				vcc-supply = <&sb_3v3>;
167			};
168		};
169	};
170};
171
172&i2c4 {
173	status = "okay";
174
175	rtc@51 {
176		compatible = "nxp,pcf2129";
177		reg = <0x51>;
178		// IRQ10_B
179		interrupts = <0 150 0x4>;
180	};
181};
182
183&pcs_mdio3 {
184	status = "okay";
185};
186
187&pcs_mdio4 {
188	status = "okay";
189};
190
191&sata0 {
192	status = "okay";
193};
194
195&sata1 {
196	status = "okay";
197};
198
199&sata2 {
200	status = "okay";
201};
202
203&sata3 {
204	status = "okay";
205};
206
207&uart0 {
208	status = "okay";
209};
210
211&uart1 {
212	status = "okay";
213};
214
215&usb0 {
216	status = "okay";
217};
218
219&usb1 {
220	status = "okay";
221};
222