1/* 2 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 3 * 4 * Copyright (C) 2016-2017, Freescale Semiconductor 5 * 6 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPLv2 or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This library is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This library is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/thermal/thermal.h> 48 49/ { 50 compatible = "fsl,ls2080a"; 51 interrupt-parent = <&gic>; 52 #address-cells = <2>; 53 #size-cells = <2>; 54 55 cpu: cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 }; 59 60 memory@80000000 { 61 device_type = "memory"; 62 reg = <0x00000000 0x80000000 0 0x80000000>; 63 /* DRAM space - 1, size : 2 GB DRAM */ 64 }; 65 66 sysclk: sysclk { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <100000000>; 70 clock-output-names = "sysclk"; 71 }; 72 73 gic: interrupt-controller@6000000 { 74 compatible = "arm,gic-v3"; 75 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 76 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 77 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 78 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 79 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 80 #interrupt-cells = <3>; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 interrupt-controller; 85 interrupts = <1 9 0x4>; 86 87 its: gic-its@6020000 { 88 compatible = "arm,gic-v3-its"; 89 msi-controller; 90 reg = <0x0 0x6020000 0 0x20000>; 91 }; 92 }; 93 94 rstcr: syscon@1e60000 { 95 compatible = "fsl,ls2080a-rstcr", "syscon"; 96 reg = <0x0 0x1e60000 0x0 0x4>; 97 }; 98 99 reboot { 100 compatible ="syscon-reboot"; 101 regmap = <&rstcr>; 102 offset = <0x0>; 103 mask = <0x2>; 104 }; 105 106 timer { 107 compatible = "arm,armv8-timer"; 108 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ 109 <1 14 4>, /* Physical Non-Secure PPI, active-low */ 110 <1 11 4>, /* Virtual PPI, active-low */ 111 <1 10 4>; /* Hypervisor PPI, active-low */ 112 fsl,erratum-a008585; 113 }; 114 115 pmu { 116 compatible = "arm,armv8-pmuv3"; 117 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 118 }; 119 120 soc { 121 compatible = "simple-bus"; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 clockgen: clocking@1300000 { 127 compatible = "fsl,ls2080a-clockgen"; 128 reg = <0 0x1300000 0 0xa0000>; 129 #clock-cells = <2>; 130 clocks = <&sysclk>; 131 }; 132 133 dcfg: dcfg@1e00000 { 134 compatible = "fsl,ls2080a-dcfg", "syscon"; 135 reg = <0x0 0x1e00000 0x0 0x10000>; 136 little-endian; 137 }; 138 139 tmu: tmu@1f80000 { 140 compatible = "fsl,qoriq-tmu"; 141 reg = <0x0 0x1f80000 0x0 0x10000>; 142 interrupts = <0 23 0x4>; 143 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 144 fsl,tmu-calibration = <0x00000000 0x00000026 145 0x00000001 0x0000002d 146 0x00000002 0x00000032 147 0x00000003 0x00000039 148 0x00000004 0x0000003f 149 0x00000005 0x00000046 150 0x00000006 0x0000004d 151 0x00000007 0x00000054 152 0x00000008 0x0000005a 153 0x00000009 0x00000061 154 0x0000000a 0x0000006a 155 0x0000000b 0x00000071 156 157 0x00010000 0x00000025 158 0x00010001 0x0000002c 159 0x00010002 0x00000035 160 0x00010003 0x0000003d 161 0x00010004 0x00000045 162 0x00010005 0x0000004e 163 0x00010006 0x00000057 164 0x00010007 0x00000061 165 0x00010008 0x0000006b 166 0x00010009 0x00000076 167 168 0x00020000 0x00000029 169 0x00020001 0x00000033 170 0x00020002 0x0000003d 171 0x00020003 0x00000049 172 0x00020004 0x00000056 173 0x00020005 0x00000061 174 0x00020006 0x0000006d 175 176 0x00030000 0x00000021 177 0x00030001 0x0000002a 178 0x00030002 0x0000003c 179 0x00030003 0x0000004e>; 180 little-endian; 181 #thermal-sensor-cells = <1>; 182 }; 183 184 thermal-zones { 185 cpu_thermal: cpu-thermal { 186 polling-delay-passive = <1000>; 187 polling-delay = <5000>; 188 189 thermal-sensors = <&tmu 4>; 190 191 trips { 192 cpu_alert: cpu-alert { 193 temperature = <75000>; 194 hysteresis = <2000>; 195 type = "passive"; 196 }; 197 cpu_crit: cpu-crit { 198 temperature = <85000>; 199 hysteresis = <2000>; 200 type = "critical"; 201 }; 202 }; 203 204 cooling-maps { 205 map0 { 206 trip = <&cpu_alert>; 207 cooling-device = 208 <&cpu0 THERMAL_NO_LIMIT 209 THERMAL_NO_LIMIT>; 210 }; 211 map1 { 212 trip = <&cpu_alert>; 213 cooling-device = 214 <&cpu2 THERMAL_NO_LIMIT 215 THERMAL_NO_LIMIT>; 216 }; 217 map2 { 218 trip = <&cpu_alert>; 219 cooling-device = 220 <&cpu4 THERMAL_NO_LIMIT 221 THERMAL_NO_LIMIT>; 222 }; 223 map3 { 224 trip = <&cpu_alert>; 225 cooling-device = 226 <&cpu6 THERMAL_NO_LIMIT 227 THERMAL_NO_LIMIT>; 228 }; 229 }; 230 }; 231 }; 232 233 serial0: serial@21c0500 { 234 compatible = "fsl,ns16550", "ns16550a"; 235 reg = <0x0 0x21c0500 0x0 0x100>; 236 clocks = <&clockgen 4 3>; 237 interrupts = <0 32 0x4>; /* Level high type */ 238 }; 239 240 serial1: serial@21c0600 { 241 compatible = "fsl,ns16550", "ns16550a"; 242 reg = <0x0 0x21c0600 0x0 0x100>; 243 clocks = <&clockgen 4 3>; 244 interrupts = <0 32 0x4>; /* Level high type */ 245 }; 246 247 cluster1_core0_watchdog: wdt@c000000 { 248 compatible = "arm,sp805-wdt", "arm,primecell"; 249 reg = <0x0 0xc000000 0x0 0x1000>; 250 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 251 clock-names = "apb_pclk", "wdog_clk"; 252 }; 253 254 cluster1_core1_watchdog: wdt@c010000 { 255 compatible = "arm,sp805-wdt", "arm,primecell"; 256 reg = <0x0 0xc010000 0x0 0x1000>; 257 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 258 clock-names = "apb_pclk", "wdog_clk"; 259 }; 260 261 cluster2_core0_watchdog: wdt@c100000 { 262 compatible = "arm,sp805-wdt", "arm,primecell"; 263 reg = <0x0 0xc100000 0x0 0x1000>; 264 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 265 clock-names = "apb_pclk", "wdog_clk"; 266 }; 267 268 cluster2_core1_watchdog: wdt@c110000 { 269 compatible = "arm,sp805-wdt", "arm,primecell"; 270 reg = <0x0 0xc110000 0x0 0x1000>; 271 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 272 clock-names = "apb_pclk", "wdog_clk"; 273 }; 274 275 cluster3_core0_watchdog: wdt@c200000 { 276 compatible = "arm,sp805-wdt", "arm,primecell"; 277 reg = <0x0 0xc200000 0x0 0x1000>; 278 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 279 clock-names = "apb_pclk", "wdog_clk"; 280 }; 281 282 cluster3_core1_watchdog: wdt@c210000 { 283 compatible = "arm,sp805-wdt", "arm,primecell"; 284 reg = <0x0 0xc210000 0x0 0x1000>; 285 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 286 clock-names = "apb_pclk", "wdog_clk"; 287 }; 288 289 cluster4_core0_watchdog: wdt@c300000 { 290 compatible = "arm,sp805-wdt", "arm,primecell"; 291 reg = <0x0 0xc300000 0x0 0x1000>; 292 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 293 clock-names = "apb_pclk", "wdog_clk"; 294 }; 295 296 cluster4_core1_watchdog: wdt@c310000 { 297 compatible = "arm,sp805-wdt", "arm,primecell"; 298 reg = <0x0 0xc310000 0x0 0x1000>; 299 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 300 clock-names = "apb_pclk", "wdog_clk"; 301 }; 302 303 fsl_mc: fsl-mc@80c000000 { 304 compatible = "fsl,qoriq-mc"; 305 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 306 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 307 msi-parent = <&its>; 308 #address-cells = <3>; 309 #size-cells = <1>; 310 311 /* 312 * Region type 0x0 - MC portals 313 * Region type 0x1 - QBMAN portals 314 */ 315 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 316 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 317 318 /* 319 * Define the maximum number of MACs present on the SoC. 320 */ 321 dpmacs { 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 dpmac1: dpmac@1 { 326 compatible = "fsl,qoriq-mc-dpmac"; 327 reg = <0x1>; 328 }; 329 330 dpmac2: dpmac@2 { 331 compatible = "fsl,qoriq-mc-dpmac"; 332 reg = <0x2>; 333 }; 334 335 dpmac3: dpmac@3 { 336 compatible = "fsl,qoriq-mc-dpmac"; 337 reg = <0x3>; 338 }; 339 340 dpmac4: dpmac@4 { 341 compatible = "fsl,qoriq-mc-dpmac"; 342 reg = <0x4>; 343 }; 344 345 dpmac5: dpmac@5 { 346 compatible = "fsl,qoriq-mc-dpmac"; 347 reg = <0x5>; 348 }; 349 350 dpmac6: dpmac@6 { 351 compatible = "fsl,qoriq-mc-dpmac"; 352 reg = <0x6>; 353 }; 354 355 dpmac7: dpmac@7 { 356 compatible = "fsl,qoriq-mc-dpmac"; 357 reg = <0x7>; 358 }; 359 360 dpmac8: dpmac@8 { 361 compatible = "fsl,qoriq-mc-dpmac"; 362 reg = <0x8>; 363 }; 364 365 dpmac9: dpmac@9 { 366 compatible = "fsl,qoriq-mc-dpmac"; 367 reg = <0x9>; 368 }; 369 370 dpmac10: dpmac@a { 371 compatible = "fsl,qoriq-mc-dpmac"; 372 reg = <0xa>; 373 }; 374 375 dpmac11: dpmac@b { 376 compatible = "fsl,qoriq-mc-dpmac"; 377 reg = <0xb>; 378 }; 379 380 dpmac12: dpmac@c { 381 compatible = "fsl,qoriq-mc-dpmac"; 382 reg = <0xc>; 383 }; 384 385 dpmac13: dpmac@d { 386 compatible = "fsl,qoriq-mc-dpmac"; 387 reg = <0xd>; 388 }; 389 390 dpmac14: dpmac@e { 391 compatible = "fsl,qoriq-mc-dpmac"; 392 reg = <0xe>; 393 }; 394 395 dpmac15: dpmac@f { 396 compatible = "fsl,qoriq-mc-dpmac"; 397 reg = <0xf>; 398 }; 399 400 dpmac16: dpmac@10 { 401 compatible = "fsl,qoriq-mc-dpmac"; 402 reg = <0x10>; 403 }; 404 }; 405 }; 406 407 smmu: iommu@5000000 { 408 compatible = "arm,mmu-500"; 409 reg = <0 0x5000000 0 0x800000>; 410 #global-interrupts = <12>; 411 interrupts = <0 13 4>, /* global secure fault */ 412 <0 14 4>, /* combined secure interrupt */ 413 <0 15 4>, /* global non-secure fault */ 414 <0 16 4>, /* combined non-secure interrupt */ 415 /* performance counter interrupts 0-7 */ 416 <0 211 4>, <0 212 4>, 417 <0 213 4>, <0 214 4>, 418 <0 215 4>, <0 216 4>, 419 <0 217 4>, <0 218 4>, 420 /* per context interrupt, 64 interrupts */ 421 <0 146 4>, <0 147 4>, 422 <0 148 4>, <0 149 4>, 423 <0 150 4>, <0 151 4>, 424 <0 152 4>, <0 153 4>, 425 <0 154 4>, <0 155 4>, 426 <0 156 4>, <0 157 4>, 427 <0 158 4>, <0 159 4>, 428 <0 160 4>, <0 161 4>, 429 <0 162 4>, <0 163 4>, 430 <0 164 4>, <0 165 4>, 431 <0 166 4>, <0 167 4>, 432 <0 168 4>, <0 169 4>, 433 <0 170 4>, <0 171 4>, 434 <0 172 4>, <0 173 4>, 435 <0 174 4>, <0 175 4>, 436 <0 176 4>, <0 177 4>, 437 <0 178 4>, <0 179 4>, 438 <0 180 4>, <0 181 4>, 439 <0 182 4>, <0 183 4>, 440 <0 184 4>, <0 185 4>, 441 <0 186 4>, <0 187 4>, 442 <0 188 4>, <0 189 4>, 443 <0 190 4>, <0 191 4>, 444 <0 192 4>, <0 193 4>, 445 <0 194 4>, <0 195 4>, 446 <0 196 4>, <0 197 4>, 447 <0 198 4>, <0 199 4>, 448 <0 200 4>, <0 201 4>, 449 <0 202 4>, <0 203 4>, 450 <0 204 4>, <0 205 4>, 451 <0 206 4>, <0 207 4>, 452 <0 208 4>, <0 209 4>; 453 mmu-masters = <&fsl_mc 0x300 0>; 454 }; 455 456 dspi: dspi@2100000 { 457 status = "disabled"; 458 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 reg = <0x0 0x2100000 0x0 0x10000>; 462 interrupts = <0 26 0x4>; /* Level high type */ 463 clocks = <&clockgen 4 3>; 464 clock-names = "dspi"; 465 spi-num-chipselects = <5>; 466 bus-num = <0>; 467 }; 468 469 esdhc: esdhc@2140000 { 470 status = "disabled"; 471 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 472 reg = <0x0 0x2140000 0x0 0x10000>; 473 interrupts = <0 28 0x4>; /* Level high type */ 474 clock-frequency = <0>; /* Updated by bootloader */ 475 voltage-ranges = <1800 1800 3300 3300>; 476 sdhci,auto-cmd12; 477 little-endian; 478 bus-width = <4>; 479 }; 480 481 gpio0: gpio@2300000 { 482 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 483 reg = <0x0 0x2300000 0x0 0x10000>; 484 interrupts = <0 36 0x4>; /* Level high type */ 485 gpio-controller; 486 little-endian; 487 #gpio-cells = <2>; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 }; 491 492 gpio1: gpio@2310000 { 493 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 494 reg = <0x0 0x2310000 0x0 0x10000>; 495 interrupts = <0 36 0x4>; /* Level high type */ 496 gpio-controller; 497 little-endian; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 }; 502 503 gpio2: gpio@2320000 { 504 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 505 reg = <0x0 0x2320000 0x0 0x10000>; 506 interrupts = <0 37 0x4>; /* Level high type */ 507 gpio-controller; 508 little-endian; 509 #gpio-cells = <2>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 }; 513 514 gpio3: gpio@2330000 { 515 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 516 reg = <0x0 0x2330000 0x0 0x10000>; 517 interrupts = <0 37 0x4>; /* Level high type */ 518 gpio-controller; 519 little-endian; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 }; 524 525 i2c0: i2c@2000000 { 526 status = "disabled"; 527 compatible = "fsl,vf610-i2c"; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 reg = <0x0 0x2000000 0x0 0x10000>; 531 interrupts = <0 34 0x4>; /* Level high type */ 532 clock-names = "i2c"; 533 clocks = <&clockgen 4 3>; 534 }; 535 536 i2c1: i2c@2010000 { 537 status = "disabled"; 538 compatible = "fsl,vf610-i2c"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <0x0 0x2010000 0x0 0x10000>; 542 interrupts = <0 34 0x4>; /* Level high type */ 543 clock-names = "i2c"; 544 clocks = <&clockgen 4 3>; 545 }; 546 547 i2c2: i2c@2020000 { 548 status = "disabled"; 549 compatible = "fsl,vf610-i2c"; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 reg = <0x0 0x2020000 0x0 0x10000>; 553 interrupts = <0 35 0x4>; /* Level high type */ 554 clock-names = "i2c"; 555 clocks = <&clockgen 4 3>; 556 }; 557 558 i2c3: i2c@2030000 { 559 status = "disabled"; 560 compatible = "fsl,vf610-i2c"; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 reg = <0x0 0x2030000 0x0 0x10000>; 564 interrupts = <0 35 0x4>; /* Level high type */ 565 clock-names = "i2c"; 566 clocks = <&clockgen 4 3>; 567 }; 568 569 ifc: ifc@2240000 { 570 compatible = "fsl,ifc", "simple-bus"; 571 reg = <0x0 0x2240000 0x0 0x20000>; 572 interrupts = <0 21 0x4>; /* Level high type */ 573 little-endian; 574 #address-cells = <2>; 575 #size-cells = <1>; 576 577 ranges = <0 0 0x5 0x80000000 0x08000000 578 2 0 0x5 0x30000000 0x00010000 579 3 0 0x5 0x20000000 0x00010000>; 580 }; 581 582 qspi: quadspi@20c0000 { 583 status = "disabled"; 584 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 reg = <0x0 0x20c0000 0x0 0x10000>, 588 <0x0 0x20000000 0x0 0x10000000>; 589 reg-names = "QuadSPI", "QuadSPI-memory"; 590 interrupts = <0 25 0x4>; /* Level high type */ 591 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 592 clock-names = "qspi_en", "qspi"; 593 }; 594 595 pcie1: pcie@3400000 { 596 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 597 "snps,dw-pcie"; 598 reg-names = "regs", "config"; 599 interrupts = <0 108 0x4>; /* Level high type */ 600 interrupt-names = "intr"; 601 #address-cells = <3>; 602 #size-cells = <2>; 603 device_type = "pci"; 604 dma-coherent; 605 num-lanes = <4>; 606 bus-range = <0x0 0xff>; 607 msi-parent = <&its>; 608 #interrupt-cells = <1>; 609 interrupt-map-mask = <0 0 0 7>; 610 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, 611 <0000 0 0 2 &gic 0 0 0 110 4>, 612 <0000 0 0 3 &gic 0 0 0 111 4>, 613 <0000 0 0 4 &gic 0 0 0 112 4>; 614 }; 615 616 pcie2: pcie@3500000 { 617 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 618 "snps,dw-pcie"; 619 reg-names = "regs", "config"; 620 interrupts = <0 113 0x4>; /* Level high type */ 621 interrupt-names = "intr"; 622 #address-cells = <3>; 623 #size-cells = <2>; 624 device_type = "pci"; 625 dma-coherent; 626 num-lanes = <4>; 627 bus-range = <0x0 0xff>; 628 msi-parent = <&its>; 629 #interrupt-cells = <1>; 630 interrupt-map-mask = <0 0 0 7>; 631 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, 632 <0000 0 0 2 &gic 0 0 0 115 4>, 633 <0000 0 0 3 &gic 0 0 0 116 4>, 634 <0000 0 0 4 &gic 0 0 0 117 4>; 635 }; 636 637 pcie3: pcie@3600000 { 638 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 639 "snps,dw-pcie"; 640 reg-names = "regs", "config"; 641 interrupts = <0 118 0x4>; /* Level high type */ 642 interrupt-names = "intr"; 643 #address-cells = <3>; 644 #size-cells = <2>; 645 device_type = "pci"; 646 dma-coherent; 647 num-lanes = <8>; 648 bus-range = <0x0 0xff>; 649 msi-parent = <&its>; 650 #interrupt-cells = <1>; 651 interrupt-map-mask = <0 0 0 7>; 652 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, 653 <0000 0 0 2 &gic 0 0 0 120 4>, 654 <0000 0 0 3 &gic 0 0 0 121 4>, 655 <0000 0 0 4 &gic 0 0 0 122 4>; 656 }; 657 658 pcie4: pcie@3700000 { 659 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 660 "snps,dw-pcie"; 661 reg-names = "regs", "config"; 662 interrupts = <0 123 0x4>; /* Level high type */ 663 interrupt-names = "intr"; 664 #address-cells = <3>; 665 #size-cells = <2>; 666 device_type = "pci"; 667 dma-coherent; 668 num-lanes = <4>; 669 bus-range = <0x0 0xff>; 670 msi-parent = <&its>; 671 #interrupt-cells = <1>; 672 interrupt-map-mask = <0 0 0 7>; 673 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, 674 <0000 0 0 2 &gic 0 0 0 125 4>, 675 <0000 0 0 3 &gic 0 0 0 126 4>, 676 <0000 0 0 4 &gic 0 0 0 127 4>; 677 }; 678 679 sata0: sata@3200000 { 680 status = "disabled"; 681 compatible = "fsl,ls2080a-ahci"; 682 reg = <0x0 0x3200000 0x0 0x10000>; 683 interrupts = <0 133 0x4>; /* Level high type */ 684 clocks = <&clockgen 4 3>; 685 dma-coherent; 686 }; 687 688 sata1: sata@3210000 { 689 status = "disabled"; 690 compatible = "fsl,ls2080a-ahci"; 691 reg = <0x0 0x3210000 0x0 0x10000>; 692 interrupts = <0 136 0x4>; /* Level high type */ 693 clocks = <&clockgen 4 3>; 694 dma-coherent; 695 }; 696 697 usb0: usb3@3100000 { 698 status = "disabled"; 699 compatible = "snps,dwc3"; 700 reg = <0x0 0x3100000 0x0 0x10000>; 701 interrupts = <0 80 0x4>; /* Level high type */ 702 dr_mode = "host"; 703 snps,quirk-frame-length-adjustment = <0x20>; 704 snps,dis_rxdet_inp3_quirk; 705 }; 706 707 usb1: usb3@3110000 { 708 status = "disabled"; 709 compatible = "snps,dwc3"; 710 reg = <0x0 0x3110000 0x0 0x10000>; 711 interrupts = <0 81 0x4>; /* Level high type */ 712 dr_mode = "host"; 713 snps,quirk-frame-length-adjustment = <0x20>; 714 snps,dis_rxdet_inp3_quirk; 715 }; 716 717 ccn@4000000 { 718 compatible = "arm,ccn-504"; 719 reg = <0x0 0x04000000 0x0 0x01000000>; 720 interrupts = <0 12 4>; 721 }; 722 }; 723 724 ddr1: memory-controller@1080000 { 725 compatible = "fsl,qoriq-memory-controller"; 726 reg = <0x0 0x1080000 0x0 0x1000>; 727 interrupts = <0 17 0x4>; 728 little-endian; 729 }; 730 731 ddr2: memory-controller@1090000 { 732 compatible = "fsl,qoriq-memory-controller"; 733 reg = <0x0 0x1090000 0x0 0x1000>; 734 interrupts = <0 18 0x4>; 735 little-endian; 736 }; 737}; 738