1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017-2020 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/thermal/thermal.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/ {
16	compatible = "fsl,ls2080a";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		crypto = &crypto;
23		rtc1 = &ftm_alarm0;
24		serial0 = &serial0;
25		serial1 = &serial1;
26		serial2 = &serial2;
27		serial3 = &serial3;
28	};
29
30	cpu: cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33	};
34
35	memory@80000000 {
36		device_type = "memory";
37		reg = <0x00000000 0x80000000 0 0x80000000>;
38		      /* DRAM space - 1, size : 2 GB DRAM */
39	};
40
41	sysclk: sysclk {
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <100000000>;
45		clock-output-names = "sysclk";
46	};
47
48	gic: interrupt-controller@6000000 {
49		compatible = "arm,gic-v3";
50		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
51			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
52			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
53			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
54			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
55		#interrupt-cells = <3>;
56		#address-cells = <2>;
57		#size-cells = <2>;
58		ranges;
59		interrupt-controller;
60		interrupts = <1 9 0x4>;
61
62		its: gic-its@6020000 {
63			compatible = "arm,gic-v3-its";
64			msi-controller;
65			reg = <0x0 0x6020000 0 0x20000>;
66		};
67	};
68
69	rstcr: syscon@1e60000 {
70		compatible = "fsl,ls2080a-rstcr", "syscon";
71		reg = <0x0 0x1e60000 0x0 0x4>;
72	};
73
74	reboot {
75		compatible ="syscon-reboot";
76		regmap = <&rstcr>;
77		offset = <0x0>;
78		mask = <0x2>;
79	};
80
81	thermal-zones {
82		ddr-controller1 {
83			polling-delay-passive = <1000>;
84			polling-delay = <5000>;
85			thermal-sensors = <&tmu 1>;
86
87			trips {
88				ddr-ctrler1-crit {
89					temperature = <95000>;
90					hysteresis = <2000>;
91					type = "critical";
92				};
93			};
94		};
95
96		ddr-controller2 {
97			polling-delay-passive = <1000>;
98			polling-delay = <5000>;
99			thermal-sensors = <&tmu 2>;
100
101			trips {
102				ddr-ctrler2-crit {
103					temperature = <95000>;
104					hysteresis = <2000>;
105					type = "critical";
106				};
107			};
108		};
109
110		ddr-controller3 {
111			polling-delay-passive = <1000>;
112			polling-delay = <5000>;
113			thermal-sensors = <&tmu 3>;
114
115			trips {
116				ddr-ctrler3-crit {
117					temperature = <95000>;
118					hysteresis = <2000>;
119					type = "critical";
120				};
121			};
122		};
123
124		core-cluster1 {
125			polling-delay-passive = <1000>;
126			polling-delay = <5000>;
127			thermal-sensors = <&tmu 4>;
128
129			trips {
130				core_cluster1_alert: core-cluster1-alert {
131					temperature = <85000>;
132					hysteresis = <2000>;
133					type = "passive";
134				};
135
136				core-cluster1-crit {
137					temperature = <95000>;
138					hysteresis = <2000>;
139					type = "critical";
140				};
141			};
142
143			cooling-maps {
144				map0 {
145					trip = <&core_cluster1_alert>;
146					cooling-device =
147						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
148						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149				};
150			};
151		};
152
153		core-cluster2 {
154			polling-delay-passive = <1000>;
155			polling-delay = <5000>;
156			thermal-sensors = <&tmu 5>;
157
158			trips {
159				core_cluster2_alert: core-cluster2-alert {
160					temperature = <85000>;
161					hysteresis = <2000>;
162					type = "passive";
163				};
164
165				core-cluster2-crit {
166					temperature = <95000>;
167					hysteresis = <2000>;
168					type = "critical";
169				};
170			};
171
172			cooling-maps {
173				map0 {
174					trip = <&core_cluster2_alert>;
175					cooling-device =
176						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
177						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
178				};
179			};
180		};
181
182		core-cluster3 {
183			polling-delay-passive = <1000>;
184			polling-delay = <5000>;
185			thermal-sensors = <&tmu 6>;
186
187			trips {
188				core_cluster3_alert: core-cluster3-alert {
189					temperature = <85000>;
190					hysteresis = <2000>;
191					type = "passive";
192				};
193
194				core-cluster3-crit {
195					temperature = <95000>;
196					hysteresis = <2000>;
197					type = "critical";
198				};
199			};
200
201			cooling-maps {
202				map0 {
203					trip = <&core_cluster3_alert>;
204					cooling-device =
205						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
207				};
208			};
209		};
210
211		core-cluster4 {
212			polling-delay-passive = <1000>;
213			polling-delay = <5000>;
214			thermal-sensors = <&tmu 7>;
215
216			trips {
217				core_cluster4_alert: core-cluster4-alert {
218					temperature = <85000>;
219					hysteresis = <2000>;
220					type = "passive";
221				};
222
223				core-cluster4-crit {
224					temperature = <95000>;
225					hysteresis = <2000>;
226					type = "critical";
227				};
228			};
229
230			cooling-maps {
231				map0 {
232					trip = <&core_cluster4_alert>;
233					cooling-device =
234						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
235						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
236				};
237			};
238		};
239	};
240
241	timer {
242		compatible = "arm,armv8-timer";
243		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
244			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
245			     <1 11 4>, /* Virtual PPI, active-low */
246			     <1 10 4>; /* Hypervisor PPI, active-low */
247		fsl,erratum-a008585;
248	};
249
250	pmu {
251		compatible = "arm,armv8-pmuv3";
252		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
253	};
254
255	psci {
256		compatible = "arm,psci-0.2";
257		method = "smc";
258	};
259
260	soc {
261		compatible = "simple-bus";
262		#address-cells = <2>;
263		#size-cells = <2>;
264		ranges;
265		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
266
267		clockgen: clocking@1300000 {
268			compatible = "fsl,ls2080a-clockgen";
269			reg = <0 0x1300000 0 0xa0000>;
270			#clock-cells = <2>;
271			clocks = <&sysclk>;
272		};
273
274		dcfg: dcfg@1e00000 {
275			compatible = "fsl,ls2080a-dcfg", "syscon";
276			reg = <0x0 0x1e00000 0x0 0x10000>;
277			little-endian;
278		};
279
280		isc: syscon@1f70000 {
281			compatible = "fsl,ls2080a-isc", "syscon";
282			reg = <0x0 0x1f70000 0x0 0x10000>;
283			little-endian;
284			#address-cells = <1>;
285			#size-cells = <1>;
286			ranges = <0x0 0x0 0x1f70000 0x10000>;
287
288			extirq: interrupt-controller@14 {
289				compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
290				#interrupt-cells = <2>;
291				#address-cells = <0>;
292				interrupt-controller;
293				reg = <0x14 4>;
294				interrupt-map =
295					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
296					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
297					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
298					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
299					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
300					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
301					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
302					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
303					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
304					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
305					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
306					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
307				interrupt-map-mask = <0xffffffff 0x0>;
308			};
309		};
310
311		tmu: tmu@1f80000 {
312			compatible = "fsl,qoriq-tmu";
313			reg = <0x0 0x1f80000 0x0 0x10000>;
314			interrupts = <0 23 0x4>;
315			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
316			fsl,tmu-calibration = <0x00000000 0x00000026
317					       0x00000001 0x0000002d
318					       0x00000002 0x00000032
319					       0x00000003 0x00000039
320					       0x00000004 0x0000003f
321					       0x00000005 0x00000046
322					       0x00000006 0x0000004d
323					       0x00000007 0x00000054
324					       0x00000008 0x0000005a
325					       0x00000009 0x00000061
326					       0x0000000a 0x0000006a
327					       0x0000000b 0x00000071
328
329					       0x00010000 0x00000025
330					       0x00010001 0x0000002c
331					       0x00010002 0x00000035
332					       0x00010003 0x0000003d
333					       0x00010004 0x00000045
334					       0x00010005 0x0000004e
335					       0x00010006 0x00000057
336					       0x00010007 0x00000061
337					       0x00010008 0x0000006b
338					       0x00010009 0x00000076
339
340					       0x00020000 0x00000029
341					       0x00020001 0x00000033
342					       0x00020002 0x0000003d
343					       0x00020003 0x00000049
344					       0x00020004 0x00000056
345					       0x00020005 0x00000061
346					       0x00020006 0x0000006d
347
348					       0x00030000 0x00000021
349					       0x00030001 0x0000002a
350					       0x00030002 0x0000003c
351					       0x00030003 0x0000004e>;
352			little-endian;
353			#thermal-sensor-cells = <1>;
354		};
355
356		serial0: serial@21c0500 {
357			compatible = "fsl,ns16550", "ns16550a";
358			reg = <0x0 0x21c0500 0x0 0x100>;
359			clocks = <&clockgen 4 3>;
360			interrupts = <0 32 0x4>; /* Level high type */
361		};
362
363		serial1: serial@21c0600 {
364			compatible = "fsl,ns16550", "ns16550a";
365			reg = <0x0 0x21c0600 0x0 0x100>;
366			clocks = <&clockgen 4 3>;
367			interrupts = <0 32 0x4>; /* Level high type */
368		};
369
370		serial2: serial@21d0500 {
371			compatible = "fsl,ns16550", "ns16550a";
372			reg = <0x0 0x21d0500 0x0 0x100>;
373			clocks = <&clockgen 4 3>;
374			interrupts = <0 33 0x4>; /* Level high type */
375		};
376
377		serial3: serial@21d0600 {
378			compatible = "fsl,ns16550", "ns16550a";
379			reg = <0x0 0x21d0600 0x0 0x100>;
380			clocks = <&clockgen 4 3>;
381			interrupts = <0 33 0x4>; /* Level high type */
382		};
383
384		cluster1_core0_watchdog: wdt@c000000 {
385			compatible = "arm,sp805-wdt", "arm,primecell";
386			reg = <0x0 0xc000000 0x0 0x1000>;
387			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
388			clock-names = "wdog_clk", "apb_pclk";
389		};
390
391		cluster1_core1_watchdog: wdt@c010000 {
392			compatible = "arm,sp805-wdt", "arm,primecell";
393			reg = <0x0 0xc010000 0x0 0x1000>;
394			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
395			clock-names = "wdog_clk", "apb_pclk";
396		};
397
398		cluster2_core0_watchdog: wdt@c100000 {
399			compatible = "arm,sp805-wdt", "arm,primecell";
400			reg = <0x0 0xc100000 0x0 0x1000>;
401			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
402			clock-names = "wdog_clk", "apb_pclk";
403		};
404
405		cluster2_core1_watchdog: wdt@c110000 {
406			compatible = "arm,sp805-wdt", "arm,primecell";
407			reg = <0x0 0xc110000 0x0 0x1000>;
408			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
409			clock-names = "wdog_clk", "apb_pclk";
410		};
411
412		cluster3_core0_watchdog: wdt@c200000 {
413			compatible = "arm,sp805-wdt", "arm,primecell";
414			reg = <0x0 0xc200000 0x0 0x1000>;
415			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
416			clock-names = "wdog_clk", "apb_pclk";
417		};
418
419		cluster3_core1_watchdog: wdt@c210000 {
420			compatible = "arm,sp805-wdt", "arm,primecell";
421			reg = <0x0 0xc210000 0x0 0x1000>;
422			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
423			clock-names = "wdog_clk", "apb_pclk";
424		};
425
426		cluster4_core0_watchdog: wdt@c300000 {
427			compatible = "arm,sp805-wdt", "arm,primecell";
428			reg = <0x0 0xc300000 0x0 0x1000>;
429			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
430			clock-names = "wdog_clk", "apb_pclk";
431		};
432
433		cluster4_core1_watchdog: wdt@c310000 {
434			compatible = "arm,sp805-wdt", "arm,primecell";
435			reg = <0x0 0xc310000 0x0 0x1000>;
436			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
437			clock-names = "wdog_clk", "apb_pclk";
438		};
439
440		crypto: crypto@8000000 {
441			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
442			fsl,sec-era = <8>;
443			#address-cells = <1>;
444			#size-cells = <1>;
445			ranges = <0x0 0x00 0x8000000 0x100000>;
446			reg = <0x00 0x8000000 0x0 0x100000>;
447			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
448			dma-coherent;
449
450			sec_jr0: jr@10000 {
451				compatible = "fsl,sec-v5.0-job-ring",
452					     "fsl,sec-v4.0-job-ring";
453				reg	   = <0x10000 0x10000>;
454				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
455			};
456
457			sec_jr1: jr@20000 {
458				compatible = "fsl,sec-v5.0-job-ring",
459					     "fsl,sec-v4.0-job-ring";
460				reg	   = <0x20000 0x10000>;
461				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
462			};
463
464			sec_jr2: jr@30000 {
465				compatible = "fsl,sec-v5.0-job-ring",
466					     "fsl,sec-v4.0-job-ring";
467				reg	   = <0x30000 0x10000>;
468				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
469			};
470
471			sec_jr3: jr@40000 {
472				compatible = "fsl,sec-v5.0-job-ring",
473					     "fsl,sec-v4.0-job-ring";
474				reg	   = <0x40000 0x10000>;
475				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
476			};
477		};
478
479		console@8340020 {
480			compatible = "fsl,dpaa2-console";
481			reg = <0x00000000 0x08340020 0 0x2>;
482		};
483
484		ptp-timer@8b95000 {
485			compatible = "fsl,dpaa2-ptp";
486			reg = <0x0 0x8b95000 0x0 0x100>;
487			clocks = <&clockgen 4 1>;
488			little-endian;
489			fsl,extts-fifo;
490		};
491
492		emdio1: mdio@8b96000 {
493			compatible = "fsl,fman-memac-mdio";
494			reg = <0x0 0x8b96000 0x0 0x1000>;
495			little-endian;
496			#address-cells = <1>;
497			#size-cells = <0>;
498			status = "disabled";
499		};
500
501		emdio2: mdio@8b97000 {
502			compatible = "fsl,fman-memac-mdio";
503			reg = <0x0 0x8b97000 0x0 0x1000>;
504			little-endian;
505			#address-cells = <1>;
506			#size-cells = <0>;
507			status = "disabled";
508		};
509
510		pcs_mdio1: mdio@8c07000 {
511			compatible = "fsl,fman-memac-mdio";
512			reg = <0x0 0x8c07000 0x0 0x1000>;
513			little-endian;
514			#address-cells = <1>;
515			#size-cells = <0>;
516			status = "disabled";
517
518			pcs1: ethernet-phy@0 {
519				reg = <0>;
520			};
521		};
522
523		pcs_mdio2: mdio@8c0b000 {
524			compatible = "fsl,fman-memac-mdio";
525			reg = <0x0 0x8c0b000 0x0 0x1000>;
526			little-endian;
527			#address-cells = <1>;
528			#size-cells = <0>;
529			status = "disabled";
530
531			pcs2: ethernet-phy@0 {
532				reg = <0>;
533			};
534		};
535
536		pcs_mdio3: mdio@8c0f000 {
537			compatible = "fsl,fman-memac-mdio";
538			reg = <0x0 0x8c0f000 0x0 0x1000>;
539			little-endian;
540			#address-cells = <1>;
541			#size-cells = <0>;
542			status = "disabled";
543
544			pcs3: ethernet-phy@0 {
545				reg = <0>;
546			};
547		};
548
549		pcs_mdio4: mdio@8c13000 {
550			compatible = "fsl,fman-memac-mdio";
551			reg = <0x0 0x8c13000 0x0 0x1000>;
552			little-endian;
553			#address-cells = <1>;
554			#size-cells = <0>;
555			status = "disabled";
556
557			pcs4: ethernet-phy@0 {
558				reg = <0>;
559			};
560		};
561
562		pcs_mdio5: mdio@8c17000 {
563			compatible = "fsl,fman-memac-mdio";
564			reg = <0x0 0x8c17000 0x0 0x1000>;
565			little-endian;
566			#address-cells = <1>;
567			#size-cells = <0>;
568			status = "disabled";
569
570			pcs5: ethernet-phy@0 {
571				reg = <0>;
572			};
573		};
574
575		pcs_mdio6: mdio@8c1b000 {
576			compatible = "fsl,fman-memac-mdio";
577			reg = <0x0 0x8c1b000 0x0 0x1000>;
578			little-endian;
579			#address-cells = <1>;
580			#size-cells = <0>;
581			status = "disabled";
582
583			pcs6: ethernet-phy@0 {
584				reg = <0>;
585			};
586		};
587
588		pcs_mdio7: mdio@8c1f000 {
589			compatible = "fsl,fman-memac-mdio";
590			reg = <0x0 0x8c1f000 0x0 0x1000>;
591			little-endian;
592			#address-cells = <1>;
593			#size-cells = <0>;
594			status = "disabled";
595
596			pcs7: ethernet-phy@0 {
597				reg = <0>;
598			};
599		};
600
601		pcs_mdio8: mdio@8c23000 {
602			compatible = "fsl,fman-memac-mdio";
603			reg = <0x0 0x8c23000 0x0 0x1000>;
604			little-endian;
605			#address-cells = <1>;
606			#size-cells = <0>;
607			status = "disabled";
608
609			pcs8: ethernet-phy@0 {
610				reg = <0>;
611			};
612		};
613
614		pcs_mdio9: mdio@8c27000 {
615			compatible = "fsl,fman-memac-mdio";
616			reg = <0x0 0x8c27000 0x0 0x1000>;
617			little-endian;
618			#address-cells = <1>;
619			#size-cells = <0>;
620			status = "disabled";
621
622			pcs9: ethernet-phy@0 {
623				reg = <0>;
624			};
625		};
626
627		pcs_mdio10: mdio@8c2b000 {
628			compatible = "fsl,fman-memac-mdio";
629			reg = <0x0 0x8c2b000 0x0 0x1000>;
630			little-endian;
631			#address-cells = <1>;
632			#size-cells = <0>;
633			status = "disabled";
634
635			pcs10: ethernet-phy@0 {
636				reg = <0>;
637			};
638		};
639
640		pcs_mdio11: mdio@8c2f000 {
641			compatible = "fsl,fman-memac-mdio";
642			reg = <0x0 0x8c2f000 0x0 0x1000>;
643			little-endian;
644			#address-cells = <1>;
645			#size-cells = <0>;
646			status = "disabled";
647
648			pcs11: ethernet-phy@0 {
649				reg = <0>;
650			};
651		};
652
653		pcs_mdio12: mdio@8c33000 {
654			compatible = "fsl,fman-memac-mdio";
655			reg = <0x0 0x8c33000 0x0 0x1000>;
656			little-endian;
657			#address-cells = <1>;
658			#size-cells = <0>;
659			status = "disabled";
660
661			pcs12: ethernet-phy@0 {
662				reg = <0>;
663			};
664		};
665
666		pcs_mdio13: mdio@8c37000 {
667			compatible = "fsl,fman-memac-mdio";
668			reg = <0x0 0x8c37000 0x0 0x1000>;
669			little-endian;
670			#address-cells = <1>;
671			#size-cells = <0>;
672			status = "disabled";
673
674			pcs13: ethernet-phy@0 {
675				reg = <0>;
676			};
677		};
678
679		pcs_mdio14: mdio@8c3b000 {
680			compatible = "fsl,fman-memac-mdio";
681			reg = <0x0 0x8c3b000 0x0 0x1000>;
682			little-endian;
683			#address-cells = <1>;
684			#size-cells = <0>;
685			status = "disabled";
686
687			pcs14: ethernet-phy@0 {
688				reg = <0>;
689			};
690		};
691
692		pcs_mdio15: mdio@8c3f000 {
693			compatible = "fsl,fman-memac-mdio";
694			reg = <0x0 0x8c3f000 0x0 0x1000>;
695			little-endian;
696			#address-cells = <1>;
697			#size-cells = <0>;
698			status = "disabled";
699
700			pcs15: ethernet-phy@0 {
701				reg = <0>;
702			};
703		};
704
705		pcs_mdio16: mdio@8c43000 {
706			compatible = "fsl,fman-memac-mdio";
707			reg = <0x0 0x8c43000 0x0 0x1000>;
708			little-endian;
709			#address-cells = <1>;
710			#size-cells = <0>;
711			status = "disabled";
712
713			pcs16: ethernet-phy@0 {
714				reg = <0>;
715			};
716		};
717
718		fsl_mc: fsl-mc@80c000000 {
719			compatible = "fsl,qoriq-mc";
720			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
721			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
722			msi-parent = <&its>;
723			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
724			dma-coherent;
725			#address-cells = <3>;
726			#size-cells = <1>;
727
728			/*
729			 * Region type 0x0 - MC portals
730			 * Region type 0x1 - QBMAN portals
731			 */
732			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
733				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
734
735			/*
736			 * Define the maximum number of MACs present on the SoC.
737			 */
738			dpmacs {
739				#address-cells = <1>;
740				#size-cells = <0>;
741
742				dpmac1: ethernet@1 {
743					compatible = "fsl,qoriq-mc-dpmac";
744					reg = <0x1>;
745					pcs-handle = <&pcs1>;
746				};
747
748				dpmac2: ethernet@2 {
749					compatible = "fsl,qoriq-mc-dpmac";
750					reg = <0x2>;
751					pcs-handle = <&pcs2>;
752				};
753
754				dpmac3: ethernet@3 {
755					compatible = "fsl,qoriq-mc-dpmac";
756					reg = <0x3>;
757					pcs-handle = <&pcs3>;
758				};
759
760				dpmac4: ethernet@4 {
761					compatible = "fsl,qoriq-mc-dpmac";
762					reg = <0x4>;
763					pcs-handle = <&pcs4>;
764				};
765
766				dpmac5: ethernet@5 {
767					compatible = "fsl,qoriq-mc-dpmac";
768					reg = <0x5>;
769					pcs-handle = <&pcs5>;
770				};
771
772				dpmac6: ethernet@6 {
773					compatible = "fsl,qoriq-mc-dpmac";
774					reg = <0x6>;
775					pcs-handle = <&pcs6>;
776				};
777
778				dpmac7: ethernet@7 {
779					compatible = "fsl,qoriq-mc-dpmac";
780					reg = <0x7>;
781					pcs-handle = <&pcs7>;
782				};
783
784				dpmac8: ethernet@8 {
785					compatible = "fsl,qoriq-mc-dpmac";
786					reg = <0x8>;
787					pcs-handle = <&pcs8>;
788				};
789
790				dpmac9: ethernet@9 {
791					compatible = "fsl,qoriq-mc-dpmac";
792					reg = <0x9>;
793					pcs-handle = <&pcs9>;
794				};
795
796				dpmac10: ethernet@a {
797					compatible = "fsl,qoriq-mc-dpmac";
798					reg = <0xa>;
799					pcs-handle = <&pcs10>;
800				};
801
802				dpmac11: ethernet@b {
803					compatible = "fsl,qoriq-mc-dpmac";
804					reg = <0xb>;
805					pcs-handle = <&pcs11>;
806				};
807
808				dpmac12: ethernet@c {
809					compatible = "fsl,qoriq-mc-dpmac";
810					reg = <0xc>;
811					pcs-handle = <&pcs12>;
812				};
813
814				dpmac13: ethernet@d {
815					compatible = "fsl,qoriq-mc-dpmac";
816					reg = <0xd>;
817					pcs-handle = <&pcs13>;
818				};
819
820				dpmac14: ethernet@e {
821					compatible = "fsl,qoriq-mc-dpmac";
822					reg = <0xe>;
823					pcs-handle = <&pcs14>;
824				};
825
826				dpmac15: ethernet@f {
827					compatible = "fsl,qoriq-mc-dpmac";
828					reg = <0xf>;
829					pcs-handle = <&pcs15>;
830				};
831
832				dpmac16: ethernet@10 {
833					compatible = "fsl,qoriq-mc-dpmac";
834					reg = <0x10>;
835					pcs-handle = <&pcs16>;
836				};
837			};
838		};
839
840		smmu: iommu@5000000 {
841			compatible = "arm,mmu-500";
842			reg = <0 0x5000000 0 0x800000>;
843			#global-interrupts = <12>;
844			#iommu-cells = <1>;
845			stream-match-mask = <0x7C00>;
846			dma-coherent;
847			interrupts = <0 13 4>, /* global secure fault */
848				     <0 14 4>, /* combined secure interrupt */
849				     <0 15 4>, /* global non-secure fault */
850				     <0 16 4>, /* combined non-secure interrupt */
851				/* performance counter interrupts 0-7 */
852				     <0 211 4>, <0 212 4>,
853				     <0 213 4>, <0 214 4>,
854				     <0 215 4>, <0 216 4>,
855				     <0 217 4>, <0 218 4>,
856				/* per context interrupt, 64 interrupts */
857				     <0 146 4>, <0 147 4>,
858				     <0 148 4>, <0 149 4>,
859				     <0 150 4>, <0 151 4>,
860				     <0 152 4>, <0 153 4>,
861				     <0 154 4>, <0 155 4>,
862				     <0 156 4>, <0 157 4>,
863				     <0 158 4>, <0 159 4>,
864				     <0 160 4>, <0 161 4>,
865				     <0 162 4>, <0 163 4>,
866				     <0 164 4>, <0 165 4>,
867				     <0 166 4>, <0 167 4>,
868				     <0 168 4>, <0 169 4>,
869				     <0 170 4>, <0 171 4>,
870				     <0 172 4>, <0 173 4>,
871				     <0 174 4>, <0 175 4>,
872				     <0 176 4>, <0 177 4>,
873				     <0 178 4>, <0 179 4>,
874				     <0 180 4>, <0 181 4>,
875				     <0 182 4>, <0 183 4>,
876				     <0 184 4>, <0 185 4>,
877				     <0 186 4>, <0 187 4>,
878				     <0 188 4>, <0 189 4>,
879				     <0 190 4>, <0 191 4>,
880				     <0 192 4>, <0 193 4>,
881				     <0 194 4>, <0 195 4>,
882				     <0 196 4>, <0 197 4>,
883				     <0 198 4>, <0 199 4>,
884				     <0 200 4>, <0 201 4>,
885				     <0 202 4>, <0 203 4>,
886				     <0 204 4>, <0 205 4>,
887				     <0 206 4>, <0 207 4>,
888				     <0 208 4>, <0 209 4>;
889		};
890
891		dspi: spi@2100000 {
892			status = "disabled";
893			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
894			#address-cells = <1>;
895			#size-cells = <0>;
896			reg = <0x0 0x2100000 0x0 0x10000>;
897			interrupts = <0 26 0x4>; /* Level high type */
898			clocks = <&clockgen 4 3>;
899			clock-names = "dspi";
900			spi-num-chipselects = <5>;
901			bus-num = <0>;
902		};
903
904		esdhc: esdhc@2140000 {
905			status = "disabled";
906			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
907			reg = <0x0 0x2140000 0x0 0x10000>;
908			interrupts = <0 28 0x4>; /* Level high type */
909			clocks = <&clockgen 4 1>;
910			voltage-ranges = <1800 1800 3300 3300>;
911			sdhci,auto-cmd12;
912			little-endian;
913			bus-width = <4>;
914		};
915
916		gpio0: gpio@2300000 {
917			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
918			reg = <0x0 0x2300000 0x0 0x10000>;
919			interrupts = <0 36 0x4>; /* Level high type */
920			gpio-controller;
921			little-endian;
922			#gpio-cells = <2>;
923			interrupt-controller;
924			#interrupt-cells = <2>;
925		};
926
927		gpio1: gpio@2310000 {
928			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
929			reg = <0x0 0x2310000 0x0 0x10000>;
930			interrupts = <0 36 0x4>; /* Level high type */
931			gpio-controller;
932			little-endian;
933			#gpio-cells = <2>;
934			interrupt-controller;
935			#interrupt-cells = <2>;
936		};
937
938		gpio2: gpio@2320000 {
939			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
940			reg = <0x0 0x2320000 0x0 0x10000>;
941			interrupts = <0 37 0x4>; /* Level high type */
942			gpio-controller;
943			little-endian;
944			#gpio-cells = <2>;
945			interrupt-controller;
946			#interrupt-cells = <2>;
947		};
948
949		gpio3: gpio@2330000 {
950			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
951			reg = <0x0 0x2330000 0x0 0x10000>;
952			interrupts = <0 37 0x4>; /* Level high type */
953			gpio-controller;
954			little-endian;
955			#gpio-cells = <2>;
956			interrupt-controller;
957			#interrupt-cells = <2>;
958		};
959
960		i2c0: i2c@2000000 {
961			status = "disabled";
962			compatible = "fsl,vf610-i2c";
963			#address-cells = <1>;
964			#size-cells = <0>;
965			reg = <0x0 0x2000000 0x0 0x10000>;
966			interrupts = <0 34 0x4>; /* Level high type */
967			clock-names = "i2c";
968			clocks = <&clockgen 4 3>;
969		};
970
971		i2c1: i2c@2010000 {
972			status = "disabled";
973			compatible = "fsl,vf610-i2c";
974			#address-cells = <1>;
975			#size-cells = <0>;
976			reg = <0x0 0x2010000 0x0 0x10000>;
977			interrupts = <0 34 0x4>; /* Level high type */
978			clock-names = "i2c";
979			clocks = <&clockgen 4 3>;
980		};
981
982		i2c2: i2c@2020000 {
983			status = "disabled";
984			compatible = "fsl,vf610-i2c";
985			#address-cells = <1>;
986			#size-cells = <0>;
987			reg = <0x0 0x2020000 0x0 0x10000>;
988			interrupts = <0 35 0x4>; /* Level high type */
989			clock-names = "i2c";
990			clocks = <&clockgen 4 3>;
991		};
992
993		i2c3: i2c@2030000 {
994			status = "disabled";
995			compatible = "fsl,vf610-i2c";
996			#address-cells = <1>;
997			#size-cells = <0>;
998			reg = <0x0 0x2030000 0x0 0x10000>;
999			interrupts = <0 35 0x4>; /* Level high type */
1000			clock-names = "i2c";
1001			clocks = <&clockgen 4 3>;
1002		};
1003
1004		ifc: ifc@2240000 {
1005			compatible = "fsl,ifc", "simple-bus";
1006			reg = <0x0 0x2240000 0x0 0x20000>;
1007			interrupts = <0 21 0x4>; /* Level high type */
1008			little-endian;
1009			#address-cells = <2>;
1010			#size-cells = <1>;
1011
1012			ranges = <0 0 0x5 0x80000000 0x08000000
1013				  2 0 0x5 0x30000000 0x00010000
1014				  3 0 0x5 0x20000000 0x00010000>;
1015		};
1016
1017		qspi: spi@20c0000 {
1018			compatible = "fsl,ls2080a-qspi";
1019			#address-cells = <1>;
1020			#size-cells = <0>;
1021			reg = <0x0 0x20c0000 0x0 0x10000>,
1022			      <0x0 0x20000000 0x0 0x10000000>;
1023			reg-names = "QuadSPI", "QuadSPI-memory";
1024			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1025			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
1026			clock-names = "qspi_en", "qspi";
1027			status = "disabled";
1028		};
1029
1030		pcie1: pcie@3400000 {
1031			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1032			reg-names = "regs", "config";
1033			interrupts = <0 108 0x4>; /* Level high type */
1034			interrupt-names = "intr";
1035			#address-cells = <3>;
1036			#size-cells = <2>;
1037			device_type = "pci";
1038			dma-coherent;
1039			num-viewport = <6>;
1040			bus-range = <0x0 0xff>;
1041			msi-parent = <&its>;
1042			#interrupt-cells = <1>;
1043			interrupt-map-mask = <0 0 0 7>;
1044			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1045					<0000 0 0 2 &gic 0 0 0 110 4>,
1046					<0000 0 0 3 &gic 0 0 0 111 4>,
1047					<0000 0 0 4 &gic 0 0 0 112 4>;
1048			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1049			status = "disabled";
1050		};
1051
1052		pcie2: pcie@3500000 {
1053			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1054			reg-names = "regs", "config";
1055			interrupts = <0 113 0x4>; /* Level high type */
1056			interrupt-names = "intr";
1057			#address-cells = <3>;
1058			#size-cells = <2>;
1059			device_type = "pci";
1060			dma-coherent;
1061			num-viewport = <6>;
1062			bus-range = <0x0 0xff>;
1063			msi-parent = <&its>;
1064			#interrupt-cells = <1>;
1065			interrupt-map-mask = <0 0 0 7>;
1066			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1067					<0000 0 0 2 &gic 0 0 0 115 4>,
1068					<0000 0 0 3 &gic 0 0 0 116 4>,
1069					<0000 0 0 4 &gic 0 0 0 117 4>;
1070			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1071			status = "disabled";
1072		};
1073
1074		pcie3: pcie@3600000 {
1075			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1076			reg-names = "regs", "config";
1077			interrupts = <0 118 0x4>; /* Level high type */
1078			interrupt-names = "intr";
1079			#address-cells = <3>;
1080			#size-cells = <2>;
1081			device_type = "pci";
1082			dma-coherent;
1083			num-viewport = <256>;
1084			bus-range = <0x0 0xff>;
1085			msi-parent = <&its>;
1086			#interrupt-cells = <1>;
1087			interrupt-map-mask = <0 0 0 7>;
1088			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1089					<0000 0 0 2 &gic 0 0 0 120 4>,
1090					<0000 0 0 3 &gic 0 0 0 121 4>,
1091					<0000 0 0 4 &gic 0 0 0 122 4>;
1092			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1093			status = "disabled";
1094		};
1095
1096		pcie4: pcie@3700000 {
1097			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1098			reg-names = "regs", "config";
1099			interrupts = <0 123 0x4>; /* Level high type */
1100			interrupt-names = "intr";
1101			#address-cells = <3>;
1102			#size-cells = <2>;
1103			device_type = "pci";
1104			dma-coherent;
1105			num-viewport = <6>;
1106			bus-range = <0x0 0xff>;
1107			msi-parent = <&its>;
1108			#interrupt-cells = <1>;
1109			interrupt-map-mask = <0 0 0 7>;
1110			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1111					<0000 0 0 2 &gic 0 0 0 125 4>,
1112					<0000 0 0 3 &gic 0 0 0 126 4>,
1113					<0000 0 0 4 &gic 0 0 0 127 4>;
1114			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1115			status = "disabled";
1116		};
1117
1118		sata0: sata@3200000 {
1119			status = "disabled";
1120			compatible = "fsl,ls2080a-ahci";
1121			reg = <0x0 0x3200000 0x0 0x10000>;
1122			interrupts = <0 133 0x4>; /* Level high type */
1123			clocks = <&clockgen 4 3>;
1124			dma-coherent;
1125		};
1126
1127		sata1: sata@3210000 {
1128			status = "disabled";
1129			compatible = "fsl,ls2080a-ahci";
1130			reg = <0x0 0x3210000 0x0 0x10000>;
1131			interrupts = <0 136 0x4>; /* Level high type */
1132			clocks = <&clockgen 4 3>;
1133			dma-coherent;
1134		};
1135
1136		usb0: usb@3100000 {
1137			status = "disabled";
1138			compatible = "snps,dwc3";
1139			reg = <0x0 0x3100000 0x0 0x10000>;
1140			interrupts = <0 80 0x4>; /* Level high type */
1141			dr_mode = "host";
1142			snps,quirk-frame-length-adjustment = <0x20>;
1143			snps,dis_rxdet_inp3_quirk;
1144			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1145		};
1146
1147		usb1: usb@3110000 {
1148			status = "disabled";
1149			compatible = "snps,dwc3";
1150			reg = <0x0 0x3110000 0x0 0x10000>;
1151			interrupts = <0 81 0x4>; /* Level high type */
1152			dr_mode = "host";
1153			snps,quirk-frame-length-adjustment = <0x20>;
1154			snps,dis_rxdet_inp3_quirk;
1155			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1156		};
1157
1158		ccn@4000000 {
1159			compatible = "arm,ccn-504";
1160			reg = <0x0 0x04000000 0x0 0x01000000>;
1161			interrupts = <0 12 4>;
1162		};
1163
1164		rcpm: power-controller@1e34040 {
1165			compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1166			reg = <0x0 0x1e34040 0x0 0x18>;
1167			#fsl,rcpm-wakeup-cells = <6>;
1168			little-endian;
1169		};
1170
1171		ftm_alarm0: timer@2800000 {
1172			compatible = "fsl,ls208xa-ftm-alarm";
1173			reg = <0x0 0x2800000 0x0 0x10000>;
1174			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1175			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1176		};
1177	};
1178
1179	ddr1: memory-controller@1080000 {
1180		compatible = "fsl,qoriq-memory-controller";
1181		reg = <0x0 0x1080000 0x0 0x1000>;
1182		interrupts = <0 17 0x4>;
1183		little-endian;
1184	};
1185
1186	ddr2: memory-controller@1090000 {
1187		compatible = "fsl,qoriq-memory-controller";
1188		reg = <0x0 0x1090000 0x0 0x1000>;
1189		interrupts = <0 18 0x4>;
1190		little-endian;
1191	};
1192
1193	firmware {
1194		optee {
1195			compatible = "linaro,optee-tz";
1196			method = "smc";
1197		};
1198	};
1199};
1200