1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/thermal/thermal.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/ {
16	compatible = "fsl,ls2080a";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		crypto = &crypto;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		serial2 = &serial2;
26		serial3 = &serial3;
27	};
28
29	cpu: cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32	};
33
34	memory@80000000 {
35		device_type = "memory";
36		reg = <0x00000000 0x80000000 0 0x80000000>;
37		      /* DRAM space - 1, size : 2 GB DRAM */
38	};
39
40	sysclk: sysclk {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <100000000>;
44		clock-output-names = "sysclk";
45	};
46
47	gic: interrupt-controller@6000000 {
48		compatible = "arm,gic-v3";
49		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
50			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
51			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
52			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
53			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
54		#interrupt-cells = <3>;
55		#address-cells = <2>;
56		#size-cells = <2>;
57		ranges;
58		interrupt-controller;
59		interrupts = <1 9 0x4>;
60
61		its: gic-its@6020000 {
62			compatible = "arm,gic-v3-its";
63			msi-controller;
64			reg = <0x0 0x6020000 0 0x20000>;
65		};
66	};
67
68	rstcr: syscon@1e60000 {
69		compatible = "fsl,ls2080a-rstcr", "syscon";
70		reg = <0x0 0x1e60000 0x0 0x4>;
71	};
72
73	reboot {
74		compatible ="syscon-reboot";
75		regmap = <&rstcr>;
76		offset = <0x0>;
77		mask = <0x2>;
78	};
79
80	thermal-zones {
81		cpu_thermal: cpu-thermal {
82			polling-delay-passive = <1000>;
83			polling-delay = <5000>;
84
85			thermal-sensors = <&tmu 4>;
86
87			trips {
88				cpu_alert: cpu-alert {
89					temperature = <75000>;
90					hysteresis = <2000>;
91					type = "passive";
92				};
93				cpu_crit: cpu-crit {
94					temperature = <85000>;
95					hysteresis = <2000>;
96					type = "critical";
97				};
98			};
99
100			cooling-maps {
101				map0 {
102					trip = <&cpu_alert>;
103					cooling-device =
104						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
105						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
106						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
107						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
108						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
109						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
110						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
111						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
112				};
113			};
114		};
115	};
116
117	timer {
118		compatible = "arm,armv8-timer";
119		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
120			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
121			     <1 11 4>, /* Virtual PPI, active-low */
122			     <1 10 4>; /* Hypervisor PPI, active-low */
123		fsl,erratum-a008585;
124	};
125
126	pmu {
127		compatible = "arm,armv8-pmuv3";
128		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
129	};
130
131	psci {
132		compatible = "arm,psci-0.2";
133		method = "smc";
134	};
135
136	soc {
137		compatible = "simple-bus";
138		#address-cells = <2>;
139		#size-cells = <2>;
140		ranges;
141		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
142
143		clockgen: clocking@1300000 {
144			compatible = "fsl,ls2080a-clockgen";
145			reg = <0 0x1300000 0 0xa0000>;
146			#clock-cells = <2>;
147			clocks = <&sysclk>;
148		};
149
150		dcfg: dcfg@1e00000 {
151			compatible = "fsl,ls2080a-dcfg", "syscon";
152			reg = <0x0 0x1e00000 0x0 0x10000>;
153			little-endian;
154		};
155
156		tmu: tmu@1f80000 {
157			compatible = "fsl,qoriq-tmu";
158			reg = <0x0 0x1f80000 0x0 0x10000>;
159			interrupts = <0 23 0x4>;
160			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
161			fsl,tmu-calibration = <0x00000000 0x00000026
162					       0x00000001 0x0000002d
163					       0x00000002 0x00000032
164					       0x00000003 0x00000039
165					       0x00000004 0x0000003f
166					       0x00000005 0x00000046
167					       0x00000006 0x0000004d
168					       0x00000007 0x00000054
169					       0x00000008 0x0000005a
170					       0x00000009 0x00000061
171					       0x0000000a 0x0000006a
172					       0x0000000b 0x00000071
173
174					       0x00010000 0x00000025
175					       0x00010001 0x0000002c
176					       0x00010002 0x00000035
177					       0x00010003 0x0000003d
178					       0x00010004 0x00000045
179					       0x00010005 0x0000004e
180					       0x00010006 0x00000057
181					       0x00010007 0x00000061
182					       0x00010008 0x0000006b
183					       0x00010009 0x00000076
184
185					       0x00020000 0x00000029
186					       0x00020001 0x00000033
187					       0x00020002 0x0000003d
188					       0x00020003 0x00000049
189					       0x00020004 0x00000056
190					       0x00020005 0x00000061
191					       0x00020006 0x0000006d
192
193					       0x00030000 0x00000021
194					       0x00030001 0x0000002a
195					       0x00030002 0x0000003c
196					       0x00030003 0x0000004e>;
197			little-endian;
198			#thermal-sensor-cells = <1>;
199		};
200
201		serial0: serial@21c0500 {
202			compatible = "fsl,ns16550", "ns16550a";
203			reg = <0x0 0x21c0500 0x0 0x100>;
204			clocks = <&clockgen 4 3>;
205			interrupts = <0 32 0x4>; /* Level high type */
206		};
207
208		serial1: serial@21c0600 {
209			compatible = "fsl,ns16550", "ns16550a";
210			reg = <0x0 0x21c0600 0x0 0x100>;
211			clocks = <&clockgen 4 3>;
212			interrupts = <0 32 0x4>; /* Level high type */
213		};
214
215		serial2: serial@21d0500 {
216			compatible = "fsl,ns16550", "ns16550a";
217			reg = <0x0 0x21d0500 0x0 0x100>;
218			clocks = <&clockgen 4 3>;
219			interrupts = <0 33 0x4>; /* Level high type */
220		};
221
222		serial3: serial@21d0600 {
223			compatible = "fsl,ns16550", "ns16550a";
224			reg = <0x0 0x21d0600 0x0 0x100>;
225			clocks = <&clockgen 4 3>;
226			interrupts = <0 33 0x4>; /* Level high type */
227		};
228
229		cluster1_core0_watchdog: wdt@c000000 {
230			compatible = "arm,sp805-wdt", "arm,primecell";
231			reg = <0x0 0xc000000 0x0 0x1000>;
232			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
233			clock-names = "apb_pclk", "wdog_clk";
234		};
235
236		cluster1_core1_watchdog: wdt@c010000 {
237			compatible = "arm,sp805-wdt", "arm,primecell";
238			reg = <0x0 0xc010000 0x0 0x1000>;
239			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
240			clock-names = "apb_pclk", "wdog_clk";
241		};
242
243		cluster2_core0_watchdog: wdt@c100000 {
244			compatible = "arm,sp805-wdt", "arm,primecell";
245			reg = <0x0 0xc100000 0x0 0x1000>;
246			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
247			clock-names = "apb_pclk", "wdog_clk";
248		};
249
250		cluster2_core1_watchdog: wdt@c110000 {
251			compatible = "arm,sp805-wdt", "arm,primecell";
252			reg = <0x0 0xc110000 0x0 0x1000>;
253			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
254			clock-names = "apb_pclk", "wdog_clk";
255		};
256
257		cluster3_core0_watchdog: wdt@c200000 {
258			compatible = "arm,sp805-wdt", "arm,primecell";
259			reg = <0x0 0xc200000 0x0 0x1000>;
260			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
261			clock-names = "apb_pclk", "wdog_clk";
262		};
263
264		cluster3_core1_watchdog: wdt@c210000 {
265			compatible = "arm,sp805-wdt", "arm,primecell";
266			reg = <0x0 0xc210000 0x0 0x1000>;
267			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
268			clock-names = "apb_pclk", "wdog_clk";
269		};
270
271		cluster4_core0_watchdog: wdt@c300000 {
272			compatible = "arm,sp805-wdt", "arm,primecell";
273			reg = <0x0 0xc300000 0x0 0x1000>;
274			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
275			clock-names = "apb_pclk", "wdog_clk";
276		};
277
278		cluster4_core1_watchdog: wdt@c310000 {
279			compatible = "arm,sp805-wdt", "arm,primecell";
280			reg = <0x0 0xc310000 0x0 0x1000>;
281			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
282			clock-names = "apb_pclk", "wdog_clk";
283		};
284
285		crypto: crypto@8000000 {
286			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
287			fsl,sec-era = <8>;
288			#address-cells = <1>;
289			#size-cells = <1>;
290			ranges = <0x0 0x00 0x8000000 0x100000>;
291			reg = <0x00 0x8000000 0x0 0x100000>;
292			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
293			dma-coherent;
294
295			sec_jr0: jr@10000 {
296				compatible = "fsl,sec-v5.0-job-ring",
297					     "fsl,sec-v4.0-job-ring";
298				reg	   = <0x10000 0x10000>;
299				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
300			};
301
302			sec_jr1: jr@20000 {
303				compatible = "fsl,sec-v5.0-job-ring",
304					     "fsl,sec-v4.0-job-ring";
305				reg	   = <0x20000 0x10000>;
306				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
307			};
308
309			sec_jr2: jr@30000 {
310				compatible = "fsl,sec-v5.0-job-ring",
311					     "fsl,sec-v4.0-job-ring";
312				reg	   = <0x30000 0x10000>;
313				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
314			};
315
316			sec_jr3: jr@40000 {
317				compatible = "fsl,sec-v5.0-job-ring",
318					     "fsl,sec-v4.0-job-ring";
319				reg	   = <0x40000 0x10000>;
320				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
321			};
322		};
323
324		ptp-timer@8b95000 {
325			compatible = "fsl,dpaa2-ptp";
326			reg = <0x0 0x8b95000 0x0 0x100>;
327			clocks = <&clockgen 4 1>;
328			little-endian;
329			fsl,extts-fifo;
330		};
331
332		fsl_mc: fsl-mc@80c000000 {
333			compatible = "fsl,qoriq-mc";
334			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
335			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
336			msi-parent = <&its>;
337			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
338			dma-coherent;
339			#address-cells = <3>;
340			#size-cells = <1>;
341
342			/*
343			 * Region type 0x0 - MC portals
344			 * Region type 0x1 - QBMAN portals
345			 */
346			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
347				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
348
349			/*
350			 * Define the maximum number of MACs present on the SoC.
351			 */
352			dpmacs {
353				#address-cells = <1>;
354				#size-cells = <0>;
355
356				dpmac1: dpmac@1 {
357					compatible = "fsl,qoriq-mc-dpmac";
358					reg = <0x1>;
359				};
360
361				dpmac2: dpmac@2 {
362					compatible = "fsl,qoriq-mc-dpmac";
363					reg = <0x2>;
364				};
365
366				dpmac3: dpmac@3 {
367					compatible = "fsl,qoriq-mc-dpmac";
368					reg = <0x3>;
369				};
370
371				dpmac4: dpmac@4 {
372					compatible = "fsl,qoriq-mc-dpmac";
373					reg = <0x4>;
374				};
375
376				dpmac5: dpmac@5 {
377					compatible = "fsl,qoriq-mc-dpmac";
378					reg = <0x5>;
379				};
380
381				dpmac6: dpmac@6 {
382					compatible = "fsl,qoriq-mc-dpmac";
383					reg = <0x6>;
384				};
385
386				dpmac7: dpmac@7 {
387					compatible = "fsl,qoriq-mc-dpmac";
388					reg = <0x7>;
389				};
390
391				dpmac8: dpmac@8 {
392					compatible = "fsl,qoriq-mc-dpmac";
393					reg = <0x8>;
394				};
395
396				dpmac9: dpmac@9 {
397					compatible = "fsl,qoriq-mc-dpmac";
398					reg = <0x9>;
399				};
400
401				dpmac10: dpmac@a {
402					compatible = "fsl,qoriq-mc-dpmac";
403					reg = <0xa>;
404				};
405
406				dpmac11: dpmac@b {
407					compatible = "fsl,qoriq-mc-dpmac";
408					reg = <0xb>;
409				};
410
411				dpmac12: dpmac@c {
412					compatible = "fsl,qoriq-mc-dpmac";
413					reg = <0xc>;
414				};
415
416				dpmac13: dpmac@d {
417					compatible = "fsl,qoriq-mc-dpmac";
418					reg = <0xd>;
419				};
420
421				dpmac14: dpmac@e {
422					compatible = "fsl,qoriq-mc-dpmac";
423					reg = <0xe>;
424				};
425
426				dpmac15: dpmac@f {
427					compatible = "fsl,qoriq-mc-dpmac";
428					reg = <0xf>;
429				};
430
431				dpmac16: dpmac@10 {
432					compatible = "fsl,qoriq-mc-dpmac";
433					reg = <0x10>;
434				};
435			};
436		};
437
438		smmu: iommu@5000000 {
439			compatible = "arm,mmu-500";
440			reg = <0 0x5000000 0 0x800000>;
441			#global-interrupts = <12>;
442			#iommu-cells = <1>;
443			stream-match-mask = <0x7C00>;
444			dma-coherent;
445			interrupts = <0 13 4>, /* global secure fault */
446				     <0 14 4>, /* combined secure interrupt */
447				     <0 15 4>, /* global non-secure fault */
448				     <0 16 4>, /* combined non-secure interrupt */
449				/* performance counter interrupts 0-7 */
450				     <0 211 4>, <0 212 4>,
451				     <0 213 4>, <0 214 4>,
452				     <0 215 4>, <0 216 4>,
453				     <0 217 4>, <0 218 4>,
454				/* per context interrupt, 64 interrupts */
455				     <0 146 4>, <0 147 4>,
456				     <0 148 4>, <0 149 4>,
457				     <0 150 4>, <0 151 4>,
458				     <0 152 4>, <0 153 4>,
459				     <0 154 4>, <0 155 4>,
460				     <0 156 4>, <0 157 4>,
461				     <0 158 4>, <0 159 4>,
462				     <0 160 4>, <0 161 4>,
463				     <0 162 4>, <0 163 4>,
464				     <0 164 4>, <0 165 4>,
465				     <0 166 4>, <0 167 4>,
466				     <0 168 4>, <0 169 4>,
467				     <0 170 4>, <0 171 4>,
468				     <0 172 4>, <0 173 4>,
469				     <0 174 4>, <0 175 4>,
470				     <0 176 4>, <0 177 4>,
471				     <0 178 4>, <0 179 4>,
472				     <0 180 4>, <0 181 4>,
473				     <0 182 4>, <0 183 4>,
474				     <0 184 4>, <0 185 4>,
475				     <0 186 4>, <0 187 4>,
476				     <0 188 4>, <0 189 4>,
477				     <0 190 4>, <0 191 4>,
478				     <0 192 4>, <0 193 4>,
479				     <0 194 4>, <0 195 4>,
480				     <0 196 4>, <0 197 4>,
481				     <0 198 4>, <0 199 4>,
482				     <0 200 4>, <0 201 4>,
483				     <0 202 4>, <0 203 4>,
484				     <0 204 4>, <0 205 4>,
485				     <0 206 4>, <0 207 4>,
486				     <0 208 4>, <0 209 4>;
487		};
488
489		dspi: spi@2100000 {
490			status = "disabled";
491			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
492			#address-cells = <1>;
493			#size-cells = <0>;
494			reg = <0x0 0x2100000 0x0 0x10000>;
495			interrupts = <0 26 0x4>; /* Level high type */
496			clocks = <&clockgen 4 3>;
497			clock-names = "dspi";
498			spi-num-chipselects = <5>;
499			bus-num = <0>;
500		};
501
502		esdhc: esdhc@2140000 {
503			status = "disabled";
504			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
505			reg = <0x0 0x2140000 0x0 0x10000>;
506			interrupts = <0 28 0x4>; /* Level high type */
507			clocks = <&clockgen 4 1>;
508			voltage-ranges = <1800 1800 3300 3300>;
509			sdhci,auto-cmd12;
510			little-endian;
511			bus-width = <4>;
512		};
513
514		gpio0: gpio@2300000 {
515			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
516			reg = <0x0 0x2300000 0x0 0x10000>;
517			interrupts = <0 36 0x4>; /* Level high type */
518			gpio-controller;
519			little-endian;
520			#gpio-cells = <2>;
521			interrupt-controller;
522			#interrupt-cells = <2>;
523		};
524
525		gpio1: gpio@2310000 {
526			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
527			reg = <0x0 0x2310000 0x0 0x10000>;
528			interrupts = <0 36 0x4>; /* Level high type */
529			gpio-controller;
530			little-endian;
531			#gpio-cells = <2>;
532			interrupt-controller;
533			#interrupt-cells = <2>;
534		};
535
536		gpio2: gpio@2320000 {
537			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
538			reg = <0x0 0x2320000 0x0 0x10000>;
539			interrupts = <0 37 0x4>; /* Level high type */
540			gpio-controller;
541			little-endian;
542			#gpio-cells = <2>;
543			interrupt-controller;
544			#interrupt-cells = <2>;
545		};
546
547		gpio3: gpio@2330000 {
548			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
549			reg = <0x0 0x2330000 0x0 0x10000>;
550			interrupts = <0 37 0x4>; /* Level high type */
551			gpio-controller;
552			little-endian;
553			#gpio-cells = <2>;
554			interrupt-controller;
555			#interrupt-cells = <2>;
556		};
557
558		i2c0: i2c@2000000 {
559			status = "disabled";
560			compatible = "fsl,vf610-i2c";
561			#address-cells = <1>;
562			#size-cells = <0>;
563			reg = <0x0 0x2000000 0x0 0x10000>;
564			interrupts = <0 34 0x4>; /* Level high type */
565			clock-names = "i2c";
566			clocks = <&clockgen 4 3>;
567		};
568
569		i2c1: i2c@2010000 {
570			status = "disabled";
571			compatible = "fsl,vf610-i2c";
572			#address-cells = <1>;
573			#size-cells = <0>;
574			reg = <0x0 0x2010000 0x0 0x10000>;
575			interrupts = <0 34 0x4>; /* Level high type */
576			clock-names = "i2c";
577			clocks = <&clockgen 4 3>;
578		};
579
580		i2c2: i2c@2020000 {
581			status = "disabled";
582			compatible = "fsl,vf610-i2c";
583			#address-cells = <1>;
584			#size-cells = <0>;
585			reg = <0x0 0x2020000 0x0 0x10000>;
586			interrupts = <0 35 0x4>; /* Level high type */
587			clock-names = "i2c";
588			clocks = <&clockgen 4 3>;
589		};
590
591		i2c3: i2c@2030000 {
592			status = "disabled";
593			compatible = "fsl,vf610-i2c";
594			#address-cells = <1>;
595			#size-cells = <0>;
596			reg = <0x0 0x2030000 0x0 0x10000>;
597			interrupts = <0 35 0x4>; /* Level high type */
598			clock-names = "i2c";
599			clocks = <&clockgen 4 3>;
600		};
601
602		ifc: ifc@2240000 {
603			compatible = "fsl,ifc", "simple-bus";
604			reg = <0x0 0x2240000 0x0 0x20000>;
605			interrupts = <0 21 0x4>; /* Level high type */
606			little-endian;
607			#address-cells = <2>;
608			#size-cells = <1>;
609
610			ranges = <0 0 0x5 0x80000000 0x08000000
611				  2 0 0x5 0x30000000 0x00010000
612				  3 0 0x5 0x20000000 0x00010000>;
613		};
614
615		qspi: spi@20c0000 {
616			status = "disabled";
617			compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
618			#address-cells = <1>;
619			#size-cells = <0>;
620			reg = <0x0 0x20c0000 0x0 0x10000>,
621			      <0x0 0x20000000 0x0 0x10000000>;
622			reg-names = "QuadSPI", "QuadSPI-memory";
623			interrupts = <0 25 0x4>; /* Level high type */
624			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
625			clock-names = "qspi_en", "qspi";
626		};
627
628		pcie1: pcie@3400000 {
629			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
630			reg-names = "regs", "config";
631			interrupts = <0 108 0x4>; /* Level high type */
632			interrupt-names = "intr";
633			#address-cells = <3>;
634			#size-cells = <2>;
635			device_type = "pci";
636			dma-coherent;
637			num-lanes = <4>;
638			num-viewport = <6>;
639			bus-range = <0x0 0xff>;
640			msi-parent = <&its>;
641			#interrupt-cells = <1>;
642			interrupt-map-mask = <0 0 0 7>;
643			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
644					<0000 0 0 2 &gic 0 0 0 110 4>,
645					<0000 0 0 3 &gic 0 0 0 111 4>,
646					<0000 0 0 4 &gic 0 0 0 112 4>;
647			status = "disabled";
648		};
649
650		pcie2: pcie@3500000 {
651			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
652			reg-names = "regs", "config";
653			interrupts = <0 113 0x4>; /* Level high type */
654			interrupt-names = "intr";
655			#address-cells = <3>;
656			#size-cells = <2>;
657			device_type = "pci";
658			dma-coherent;
659			num-lanes = <4>;
660			num-viewport = <6>;
661			bus-range = <0x0 0xff>;
662			msi-parent = <&its>;
663			#interrupt-cells = <1>;
664			interrupt-map-mask = <0 0 0 7>;
665			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
666					<0000 0 0 2 &gic 0 0 0 115 4>,
667					<0000 0 0 3 &gic 0 0 0 116 4>,
668					<0000 0 0 4 &gic 0 0 0 117 4>;
669			status = "disabled";
670		};
671
672		pcie3: pcie@3600000 {
673			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
674			reg-names = "regs", "config";
675			interrupts = <0 118 0x4>; /* Level high type */
676			interrupt-names = "intr";
677			#address-cells = <3>;
678			#size-cells = <2>;
679			device_type = "pci";
680			dma-coherent;
681			num-lanes = <8>;
682			num-viewport = <256>;
683			bus-range = <0x0 0xff>;
684			msi-parent = <&its>;
685			#interrupt-cells = <1>;
686			interrupt-map-mask = <0 0 0 7>;
687			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
688					<0000 0 0 2 &gic 0 0 0 120 4>,
689					<0000 0 0 3 &gic 0 0 0 121 4>,
690					<0000 0 0 4 &gic 0 0 0 122 4>;
691			status = "disabled";
692		};
693
694		pcie4: pcie@3700000 {
695			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
696			reg-names = "regs", "config";
697			interrupts = <0 123 0x4>; /* Level high type */
698			interrupt-names = "intr";
699			#address-cells = <3>;
700			#size-cells = <2>;
701			device_type = "pci";
702			dma-coherent;
703			num-lanes = <4>;
704			num-viewport = <6>;
705			bus-range = <0x0 0xff>;
706			msi-parent = <&its>;
707			#interrupt-cells = <1>;
708			interrupt-map-mask = <0 0 0 7>;
709			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
710					<0000 0 0 2 &gic 0 0 0 125 4>,
711					<0000 0 0 3 &gic 0 0 0 126 4>,
712					<0000 0 0 4 &gic 0 0 0 127 4>;
713			status = "disabled";
714		};
715
716		sata0: sata@3200000 {
717			status = "disabled";
718			compatible = "fsl,ls2080a-ahci";
719			reg = <0x0 0x3200000 0x0 0x10000>;
720			interrupts = <0 133 0x4>; /* Level high type */
721			clocks = <&clockgen 4 3>;
722			dma-coherent;
723		};
724
725		sata1: sata@3210000 {
726			status = "disabled";
727			compatible = "fsl,ls2080a-ahci";
728			reg = <0x0 0x3210000 0x0 0x10000>;
729			interrupts = <0 136 0x4>; /* Level high type */
730			clocks = <&clockgen 4 3>;
731			dma-coherent;
732		};
733
734		usb0: usb3@3100000 {
735			status = "disabled";
736			compatible = "snps,dwc3";
737			reg = <0x0 0x3100000 0x0 0x10000>;
738			interrupts = <0 80 0x4>; /* Level high type */
739			dr_mode = "host";
740			snps,quirk-frame-length-adjustment = <0x20>;
741			snps,dis_rxdet_inp3_quirk;
742			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
743		};
744
745		usb1: usb3@3110000 {
746			status = "disabled";
747			compatible = "snps,dwc3";
748			reg = <0x0 0x3110000 0x0 0x10000>;
749			interrupts = <0 81 0x4>; /* Level high type */
750			dr_mode = "host";
751			snps,quirk-frame-length-adjustment = <0x20>;
752			snps,dis_rxdet_inp3_quirk;
753			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
754		};
755
756		ccn@4000000 {
757			compatible = "arm,ccn-504";
758			reg = <0x0 0x04000000 0x0 0x01000000>;
759			interrupts = <0 12 4>;
760		};
761	};
762
763	ddr1: memory-controller@1080000 {
764		compatible = "fsl,qoriq-memory-controller";
765		reg = <0x0 0x1080000 0x0 0x1000>;
766		interrupts = <0 17 0x4>;
767		little-endian;
768	};
769
770	ddr2: memory-controller@1090000 {
771		compatible = "fsl,qoriq-memory-controller";
772		reg = <0x0 0x1090000 0x0 0x1000>;
773		interrupts = <0 18 0x4>;
774		little-endian;
775	};
776
777	firmware {
778		optee {
779			compatible = "linaro,optee-tz";
780			method = "smc";
781		};
782	};
783};
784