1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/thermal/thermal.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/ {
16	compatible = "fsl,ls2080a";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		crypto = &crypto;
23		rtc1 = &ftm_alarm0;
24		serial0 = &serial0;
25		serial1 = &serial1;
26		serial2 = &serial2;
27		serial3 = &serial3;
28	};
29
30	cpu: cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33	};
34
35	memory@80000000 {
36		device_type = "memory";
37		reg = <0x00000000 0x80000000 0 0x80000000>;
38		      /* DRAM space - 1, size : 2 GB DRAM */
39	};
40
41	sysclk: sysclk {
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <100000000>;
45		clock-output-names = "sysclk";
46	};
47
48	gic: interrupt-controller@6000000 {
49		compatible = "arm,gic-v3";
50		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
51			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
52			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
53			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
54			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
55		#interrupt-cells = <3>;
56		#address-cells = <2>;
57		#size-cells = <2>;
58		ranges;
59		interrupt-controller;
60		interrupts = <1 9 0x4>;
61
62		its: gic-its@6020000 {
63			compatible = "arm,gic-v3-its";
64			msi-controller;
65			reg = <0x0 0x6020000 0 0x20000>;
66		};
67	};
68
69	rstcr: syscon@1e60000 {
70		compatible = "fsl,ls2080a-rstcr", "syscon";
71		reg = <0x0 0x1e60000 0x0 0x4>;
72	};
73
74	reboot {
75		compatible ="syscon-reboot";
76		regmap = <&rstcr>;
77		offset = <0x0>;
78		mask = <0x2>;
79	};
80
81	thermal-zones {
82		ddr-controller1 {
83			polling-delay-passive = <1000>;
84			polling-delay = <5000>;
85			thermal-sensors = <&tmu 1>;
86
87			trips {
88				ddr-ctrler1-crit {
89					temperature = <95000>;
90					hysteresis = <2000>;
91					type = "critical";
92				};
93			};
94		};
95
96		ddr-controller2 {
97			polling-delay-passive = <1000>;
98			polling-delay = <5000>;
99			thermal-sensors = <&tmu 2>;
100
101			trips {
102				ddr-ctrler2-crit {
103					temperature = <95000>;
104					hysteresis = <2000>;
105					type = "critical";
106				};
107			};
108		};
109
110		ddr-controller3 {
111			polling-delay-passive = <1000>;
112			polling-delay = <5000>;
113			thermal-sensors = <&tmu 3>;
114
115			trips {
116				ddr-ctrler3-crit {
117					temperature = <95000>;
118					hysteresis = <2000>;
119					type = "critical";
120				};
121			};
122		};
123
124		core-cluster1 {
125			polling-delay-passive = <1000>;
126			polling-delay = <5000>;
127			thermal-sensors = <&tmu 4>;
128
129			trips {
130				core_cluster1_alert: core-cluster1-alert {
131					temperature = <85000>;
132					hysteresis = <2000>;
133					type = "passive";
134				};
135
136				core-cluster1-crit {
137					temperature = <95000>;
138					hysteresis = <2000>;
139					type = "critical";
140				};
141			};
142
143			cooling-maps {
144				map0 {
145					trip = <&core_cluster1_alert>;
146					cooling-device =
147						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
148						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149				};
150			};
151		};
152
153		core-cluster2 {
154			polling-delay-passive = <1000>;
155			polling-delay = <5000>;
156			thermal-sensors = <&tmu 5>;
157
158			trips {
159				core_cluster2_alert: core-cluster2-alert {
160					temperature = <85000>;
161					hysteresis = <2000>;
162					type = "passive";
163				};
164
165				core-cluster2-crit {
166					temperature = <95000>;
167					hysteresis = <2000>;
168					type = "critical";
169				};
170			};
171
172			cooling-maps {
173				map0 {
174					trip = <&core_cluster2_alert>;
175					cooling-device =
176						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
177						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
178				};
179			};
180		};
181
182		core-cluster3 {
183			polling-delay-passive = <1000>;
184			polling-delay = <5000>;
185			thermal-sensors = <&tmu 6>;
186
187			trips {
188				core_cluster3_alert: core-cluster3-alert {
189					temperature = <85000>;
190					hysteresis = <2000>;
191					type = "passive";
192				};
193
194				core-cluster3-crit {
195					temperature = <95000>;
196					hysteresis = <2000>;
197					type = "critical";
198				};
199			};
200
201			cooling-maps {
202				map0 {
203					trip = <&core_cluster3_alert>;
204					cooling-device =
205						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
207				};
208			};
209		};
210
211		core-cluster4 {
212			polling-delay-passive = <1000>;
213			polling-delay = <5000>;
214			thermal-sensors = <&tmu 7>;
215
216			trips {
217				core_cluster4_alert: core-cluster4-alert {
218					temperature = <85000>;
219					hysteresis = <2000>;
220					type = "passive";
221				};
222
223				core-cluster4-crit {
224					temperature = <95000>;
225					hysteresis = <2000>;
226					type = "critical";
227				};
228			};
229
230			cooling-maps {
231				map0 {
232					trip = <&core_cluster4_alert>;
233					cooling-device =
234						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
235						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
236				};
237			};
238		};
239	};
240
241	timer {
242		compatible = "arm,armv8-timer";
243		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
244			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
245			     <1 11 4>, /* Virtual PPI, active-low */
246			     <1 10 4>; /* Hypervisor PPI, active-low */
247		fsl,erratum-a008585;
248	};
249
250	pmu {
251		compatible = "arm,armv8-pmuv3";
252		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
253	};
254
255	psci {
256		compatible = "arm,psci-0.2";
257		method = "smc";
258	};
259
260	soc {
261		compatible = "simple-bus";
262		#address-cells = <2>;
263		#size-cells = <2>;
264		ranges;
265		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
266
267		clockgen: clocking@1300000 {
268			compatible = "fsl,ls2080a-clockgen";
269			reg = <0 0x1300000 0 0xa0000>;
270			#clock-cells = <2>;
271			clocks = <&sysclk>;
272		};
273
274		dcfg: dcfg@1e00000 {
275			compatible = "fsl,ls2080a-dcfg", "syscon";
276			reg = <0x0 0x1e00000 0x0 0x10000>;
277			little-endian;
278		};
279
280		tmu: tmu@1f80000 {
281			compatible = "fsl,qoriq-tmu";
282			reg = <0x0 0x1f80000 0x0 0x10000>;
283			interrupts = <0 23 0x4>;
284			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
285			fsl,tmu-calibration = <0x00000000 0x00000026
286					       0x00000001 0x0000002d
287					       0x00000002 0x00000032
288					       0x00000003 0x00000039
289					       0x00000004 0x0000003f
290					       0x00000005 0x00000046
291					       0x00000006 0x0000004d
292					       0x00000007 0x00000054
293					       0x00000008 0x0000005a
294					       0x00000009 0x00000061
295					       0x0000000a 0x0000006a
296					       0x0000000b 0x00000071
297
298					       0x00010000 0x00000025
299					       0x00010001 0x0000002c
300					       0x00010002 0x00000035
301					       0x00010003 0x0000003d
302					       0x00010004 0x00000045
303					       0x00010005 0x0000004e
304					       0x00010006 0x00000057
305					       0x00010007 0x00000061
306					       0x00010008 0x0000006b
307					       0x00010009 0x00000076
308
309					       0x00020000 0x00000029
310					       0x00020001 0x00000033
311					       0x00020002 0x0000003d
312					       0x00020003 0x00000049
313					       0x00020004 0x00000056
314					       0x00020005 0x00000061
315					       0x00020006 0x0000006d
316
317					       0x00030000 0x00000021
318					       0x00030001 0x0000002a
319					       0x00030002 0x0000003c
320					       0x00030003 0x0000004e>;
321			little-endian;
322			#thermal-sensor-cells = <1>;
323		};
324
325		serial0: serial@21c0500 {
326			compatible = "fsl,ns16550", "ns16550a";
327			reg = <0x0 0x21c0500 0x0 0x100>;
328			clocks = <&clockgen 4 3>;
329			interrupts = <0 32 0x4>; /* Level high type */
330		};
331
332		serial1: serial@21c0600 {
333			compatible = "fsl,ns16550", "ns16550a";
334			reg = <0x0 0x21c0600 0x0 0x100>;
335			clocks = <&clockgen 4 3>;
336			interrupts = <0 32 0x4>; /* Level high type */
337		};
338
339		serial2: serial@21d0500 {
340			compatible = "fsl,ns16550", "ns16550a";
341			reg = <0x0 0x21d0500 0x0 0x100>;
342			clocks = <&clockgen 4 3>;
343			interrupts = <0 33 0x4>; /* Level high type */
344		};
345
346		serial3: serial@21d0600 {
347			compatible = "fsl,ns16550", "ns16550a";
348			reg = <0x0 0x21d0600 0x0 0x100>;
349			clocks = <&clockgen 4 3>;
350			interrupts = <0 33 0x4>; /* Level high type */
351		};
352
353		cluster1_core0_watchdog: wdt@c000000 {
354			compatible = "arm,sp805-wdt", "arm,primecell";
355			reg = <0x0 0xc000000 0x0 0x1000>;
356			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
357			clock-names = "wdog_clk", "apb_pclk";
358		};
359
360		cluster1_core1_watchdog: wdt@c010000 {
361			compatible = "arm,sp805-wdt", "arm,primecell";
362			reg = <0x0 0xc010000 0x0 0x1000>;
363			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
364			clock-names = "wdog_clk", "apb_pclk";
365		};
366
367		cluster2_core0_watchdog: wdt@c100000 {
368			compatible = "arm,sp805-wdt", "arm,primecell";
369			reg = <0x0 0xc100000 0x0 0x1000>;
370			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
371			clock-names = "wdog_clk", "apb_pclk";
372		};
373
374		cluster2_core1_watchdog: wdt@c110000 {
375			compatible = "arm,sp805-wdt", "arm,primecell";
376			reg = <0x0 0xc110000 0x0 0x1000>;
377			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
378			clock-names = "wdog_clk", "apb_pclk";
379		};
380
381		cluster3_core0_watchdog: wdt@c200000 {
382			compatible = "arm,sp805-wdt", "arm,primecell";
383			reg = <0x0 0xc200000 0x0 0x1000>;
384			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
385			clock-names = "wdog_clk", "apb_pclk";
386		};
387
388		cluster3_core1_watchdog: wdt@c210000 {
389			compatible = "arm,sp805-wdt", "arm,primecell";
390			reg = <0x0 0xc210000 0x0 0x1000>;
391			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
392			clock-names = "wdog_clk", "apb_pclk";
393		};
394
395		cluster4_core0_watchdog: wdt@c300000 {
396			compatible = "arm,sp805-wdt", "arm,primecell";
397			reg = <0x0 0xc300000 0x0 0x1000>;
398			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
399			clock-names = "wdog_clk", "apb_pclk";
400		};
401
402		cluster4_core1_watchdog: wdt@c310000 {
403			compatible = "arm,sp805-wdt", "arm,primecell";
404			reg = <0x0 0xc310000 0x0 0x1000>;
405			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
406			clock-names = "wdog_clk", "apb_pclk";
407		};
408
409		crypto: crypto@8000000 {
410			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
411			fsl,sec-era = <8>;
412			#address-cells = <1>;
413			#size-cells = <1>;
414			ranges = <0x0 0x00 0x8000000 0x100000>;
415			reg = <0x00 0x8000000 0x0 0x100000>;
416			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
417			dma-coherent;
418
419			sec_jr0: jr@10000 {
420				compatible = "fsl,sec-v5.0-job-ring",
421					     "fsl,sec-v4.0-job-ring";
422				reg	   = <0x10000 0x10000>;
423				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
424			};
425
426			sec_jr1: jr@20000 {
427				compatible = "fsl,sec-v5.0-job-ring",
428					     "fsl,sec-v4.0-job-ring";
429				reg	   = <0x20000 0x10000>;
430				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
431			};
432
433			sec_jr2: jr@30000 {
434				compatible = "fsl,sec-v5.0-job-ring",
435					     "fsl,sec-v4.0-job-ring";
436				reg	   = <0x30000 0x10000>;
437				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
438			};
439
440			sec_jr3: jr@40000 {
441				compatible = "fsl,sec-v5.0-job-ring",
442					     "fsl,sec-v4.0-job-ring";
443				reg	   = <0x40000 0x10000>;
444				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
445			};
446		};
447
448		console@8340020 {
449			compatible = "fsl,dpaa2-console";
450			reg = <0x00000000 0x08340020 0 0x2>;
451		};
452
453		ptp-timer@8b95000 {
454			compatible = "fsl,dpaa2-ptp";
455			reg = <0x0 0x8b95000 0x0 0x100>;
456			clocks = <&clockgen 4 1>;
457			little-endian;
458			fsl,extts-fifo;
459		};
460
461		emdio1: mdio@8b96000 {
462			compatible = "fsl,fman-memac-mdio";
463			reg = <0x0 0x8b96000 0x0 0x1000>;
464			little-endian;
465			#address-cells = <1>;
466			#size-cells = <0>;
467			status = "disabled";
468		};
469
470		emdio2: mdio@8b97000 {
471			compatible = "fsl,fman-memac-mdio";
472			reg = <0x0 0x8b97000 0x0 0x1000>;
473			little-endian;
474			#address-cells = <1>;
475			#size-cells = <0>;
476			status = "disabled";
477		};
478
479		pcs_mdio1: mdio@8c07000 {
480			compatible = "fsl,fman-memac-mdio";
481			reg = <0x0 0x8c07000 0x0 0x1000>;
482			little-endian;
483			#address-cells = <1>;
484			#size-cells = <0>;
485			status = "disabled";
486
487			pcs1: ethernet-phy@0 {
488				reg = <0>;
489			};
490		};
491
492		pcs_mdio2: mdio@8c0b000 {
493			compatible = "fsl,fman-memac-mdio";
494			reg = <0x0 0x8c0b000 0x0 0x1000>;
495			little-endian;
496			#address-cells = <1>;
497			#size-cells = <0>;
498			status = "disabled";
499
500			pcs2: ethernet-phy@0 {
501				reg = <0>;
502			};
503		};
504
505		pcs_mdio3: mdio@8c0f000 {
506			compatible = "fsl,fman-memac-mdio";
507			reg = <0x0 0x8c0f000 0x0 0x1000>;
508			little-endian;
509			#address-cells = <1>;
510			#size-cells = <0>;
511			status = "disabled";
512
513			pcs3: ethernet-phy@0 {
514				reg = <0>;
515			};
516		};
517
518		pcs_mdio4: mdio@8c13000 {
519			compatible = "fsl,fman-memac-mdio";
520			reg = <0x0 0x8c13000 0x0 0x1000>;
521			little-endian;
522			#address-cells = <1>;
523			#size-cells = <0>;
524			status = "disabled";
525
526			pcs4: ethernet-phy@0 {
527				reg = <0>;
528			};
529		};
530
531		pcs_mdio5: mdio@8c17000 {
532			compatible = "fsl,fman-memac-mdio";
533			reg = <0x0 0x8c17000 0x0 0x1000>;
534			little-endian;
535			#address-cells = <1>;
536			#size-cells = <0>;
537			status = "disabled";
538
539			pcs5: ethernet-phy@0 {
540				reg = <0>;
541			};
542		};
543
544		pcs_mdio6: mdio@8c1b000 {
545			compatible = "fsl,fman-memac-mdio";
546			reg = <0x0 0x8c1b000 0x0 0x1000>;
547			little-endian;
548			#address-cells = <1>;
549			#size-cells = <0>;
550			status = "disabled";
551
552			pcs6: ethernet-phy@0 {
553				reg = <0>;
554			};
555		};
556
557		pcs_mdio7: mdio@8c1f000 {
558			compatible = "fsl,fman-memac-mdio";
559			reg = <0x0 0x8c1f000 0x0 0x1000>;
560			little-endian;
561			#address-cells = <1>;
562			#size-cells = <0>;
563			status = "disabled";
564
565			pcs7: ethernet-phy@0 {
566				reg = <0>;
567			};
568		};
569
570		pcs_mdio8: mdio@8c23000 {
571			compatible = "fsl,fman-memac-mdio";
572			reg = <0x0 0x8c23000 0x0 0x1000>;
573			little-endian;
574			#address-cells = <1>;
575			#size-cells = <0>;
576			status = "disabled";
577
578			pcs8: ethernet-phy@0 {
579				reg = <0>;
580			};
581		};
582
583		pcs_mdio9: mdio@8c27000 {
584			compatible = "fsl,fman-memac-mdio";
585			reg = <0x0 0x8c27000 0x0 0x1000>;
586			little-endian;
587			#address-cells = <1>;
588			#size-cells = <0>;
589			status = "disabled";
590
591			pcs9: ethernet-phy@0 {
592				reg = <0>;
593			};
594		};
595
596		pcs_mdio10: mdio@8c2b000 {
597			compatible = "fsl,fman-memac-mdio";
598			reg = <0x0 0x8c2b000 0x0 0x1000>;
599			little-endian;
600			#address-cells = <1>;
601			#size-cells = <0>;
602			status = "disabled";
603
604			pcs10: ethernet-phy@0 {
605				reg = <0>;
606			};
607		};
608
609		pcs_mdio11: mdio@8c2f000 {
610			compatible = "fsl,fman-memac-mdio";
611			reg = <0x0 0x8c2f000 0x0 0x1000>;
612			little-endian;
613			#address-cells = <1>;
614			#size-cells = <0>;
615			status = "disabled";
616
617			pcs11: ethernet-phy@0 {
618				reg = <0>;
619			};
620		};
621
622		pcs_mdio12: mdio@8c33000 {
623			compatible = "fsl,fman-memac-mdio";
624			reg = <0x0 0x8c33000 0x0 0x1000>;
625			little-endian;
626			#address-cells = <1>;
627			#size-cells = <0>;
628			status = "disabled";
629
630			pcs12: ethernet-phy@0 {
631				reg = <0>;
632			};
633		};
634
635		pcs_mdio13: mdio@8c37000 {
636			compatible = "fsl,fman-memac-mdio";
637			reg = <0x0 0x8c37000 0x0 0x1000>;
638			little-endian;
639			#address-cells = <1>;
640			#size-cells = <0>;
641			status = "disabled";
642
643			pcs13: ethernet-phy@0 {
644				reg = <0>;
645			};
646		};
647
648		pcs_mdio14: mdio@8c3b000 {
649			compatible = "fsl,fman-memac-mdio";
650			reg = <0x0 0x8c3b000 0x0 0x1000>;
651			little-endian;
652			#address-cells = <1>;
653			#size-cells = <0>;
654			status = "disabled";
655
656			pcs14: ethernet-phy@0 {
657				reg = <0>;
658			};
659		};
660
661		pcs_mdio15: mdio@8c3f000 {
662			compatible = "fsl,fman-memac-mdio";
663			reg = <0x0 0x8c3f000 0x0 0x1000>;
664			little-endian;
665			#address-cells = <1>;
666			#size-cells = <0>;
667			status = "disabled";
668
669			pcs15: ethernet-phy@0 {
670				reg = <0>;
671			};
672		};
673
674		pcs_mdio16: mdio@8c43000 {
675			compatible = "fsl,fman-memac-mdio";
676			reg = <0x0 0x8c43000 0x0 0x1000>;
677			little-endian;
678			#address-cells = <1>;
679			#size-cells = <0>;
680			status = "disabled";
681
682			pcs16: ethernet-phy@0 {
683				reg = <0>;
684			};
685		};
686
687		fsl_mc: fsl-mc@80c000000 {
688			compatible = "fsl,qoriq-mc";
689			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
690			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
691			msi-parent = <&its>;
692			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
693			dma-coherent;
694			#address-cells = <3>;
695			#size-cells = <1>;
696
697			/*
698			 * Region type 0x0 - MC portals
699			 * Region type 0x1 - QBMAN portals
700			 */
701			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
702				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
703
704			/*
705			 * Define the maximum number of MACs present on the SoC.
706			 */
707			dpmacs {
708				#address-cells = <1>;
709				#size-cells = <0>;
710
711				dpmac1: ethernet@1 {
712					compatible = "fsl,qoriq-mc-dpmac";
713					reg = <0x1>;
714					pcs-handle = <&pcs1>;
715				};
716
717				dpmac2: ethernet@2 {
718					compatible = "fsl,qoriq-mc-dpmac";
719					reg = <0x2>;
720					pcs-handle = <&pcs2>;
721				};
722
723				dpmac3: ethernet@3 {
724					compatible = "fsl,qoriq-mc-dpmac";
725					reg = <0x3>;
726					pcs-handle = <&pcs3>;
727				};
728
729				dpmac4: ethernet@4 {
730					compatible = "fsl,qoriq-mc-dpmac";
731					reg = <0x4>;
732					pcs-handle = <&pcs4>;
733				};
734
735				dpmac5: ethernet@5 {
736					compatible = "fsl,qoriq-mc-dpmac";
737					reg = <0x5>;
738					pcs-handle = <&pcs5>;
739				};
740
741				dpmac6: ethernet@6 {
742					compatible = "fsl,qoriq-mc-dpmac";
743					reg = <0x6>;
744					pcs-handle = <&pcs6>;
745				};
746
747				dpmac7: ethernet@7 {
748					compatible = "fsl,qoriq-mc-dpmac";
749					reg = <0x7>;
750					pcs-handle = <&pcs7>;
751				};
752
753				dpmac8: ethernet@8 {
754					compatible = "fsl,qoriq-mc-dpmac";
755					reg = <0x8>;
756					pcs-handle = <&pcs8>;
757				};
758
759				dpmac9: ethernet@9 {
760					compatible = "fsl,qoriq-mc-dpmac";
761					reg = <0x9>;
762					pcs-handle = <&pcs9>;
763				};
764
765				dpmac10: ethernet@a {
766					compatible = "fsl,qoriq-mc-dpmac";
767					reg = <0xa>;
768					pcs-handle = <&pcs10>;
769				};
770
771				dpmac11: ethernet@b {
772					compatible = "fsl,qoriq-mc-dpmac";
773					reg = <0xb>;
774					pcs-handle = <&pcs11>;
775				};
776
777				dpmac12: ethernet@c {
778					compatible = "fsl,qoriq-mc-dpmac";
779					reg = <0xc>;
780					pcs-handle = <&pcs12>;
781				};
782
783				dpmac13: ethernet@d {
784					compatible = "fsl,qoriq-mc-dpmac";
785					reg = <0xd>;
786					pcs-handle = <&pcs13>;
787				};
788
789				dpmac14: ethernet@e {
790					compatible = "fsl,qoriq-mc-dpmac";
791					reg = <0xe>;
792					pcs-handle = <&pcs14>;
793				};
794
795				dpmac15: ethernet@f {
796					compatible = "fsl,qoriq-mc-dpmac";
797					reg = <0xf>;
798					pcs-handle = <&pcs15>;
799				};
800
801				dpmac16: ethernet@10 {
802					compatible = "fsl,qoriq-mc-dpmac";
803					reg = <0x10>;
804					pcs-handle = <&pcs16>;
805				};
806			};
807		};
808
809		smmu: iommu@5000000 {
810			compatible = "arm,mmu-500";
811			reg = <0 0x5000000 0 0x800000>;
812			#global-interrupts = <12>;
813			#iommu-cells = <1>;
814			stream-match-mask = <0x7C00>;
815			dma-coherent;
816			interrupts = <0 13 4>, /* global secure fault */
817				     <0 14 4>, /* combined secure interrupt */
818				     <0 15 4>, /* global non-secure fault */
819				     <0 16 4>, /* combined non-secure interrupt */
820				/* performance counter interrupts 0-7 */
821				     <0 211 4>, <0 212 4>,
822				     <0 213 4>, <0 214 4>,
823				     <0 215 4>, <0 216 4>,
824				     <0 217 4>, <0 218 4>,
825				/* per context interrupt, 64 interrupts */
826				     <0 146 4>, <0 147 4>,
827				     <0 148 4>, <0 149 4>,
828				     <0 150 4>, <0 151 4>,
829				     <0 152 4>, <0 153 4>,
830				     <0 154 4>, <0 155 4>,
831				     <0 156 4>, <0 157 4>,
832				     <0 158 4>, <0 159 4>,
833				     <0 160 4>, <0 161 4>,
834				     <0 162 4>, <0 163 4>,
835				     <0 164 4>, <0 165 4>,
836				     <0 166 4>, <0 167 4>,
837				     <0 168 4>, <0 169 4>,
838				     <0 170 4>, <0 171 4>,
839				     <0 172 4>, <0 173 4>,
840				     <0 174 4>, <0 175 4>,
841				     <0 176 4>, <0 177 4>,
842				     <0 178 4>, <0 179 4>,
843				     <0 180 4>, <0 181 4>,
844				     <0 182 4>, <0 183 4>,
845				     <0 184 4>, <0 185 4>,
846				     <0 186 4>, <0 187 4>,
847				     <0 188 4>, <0 189 4>,
848				     <0 190 4>, <0 191 4>,
849				     <0 192 4>, <0 193 4>,
850				     <0 194 4>, <0 195 4>,
851				     <0 196 4>, <0 197 4>,
852				     <0 198 4>, <0 199 4>,
853				     <0 200 4>, <0 201 4>,
854				     <0 202 4>, <0 203 4>,
855				     <0 204 4>, <0 205 4>,
856				     <0 206 4>, <0 207 4>,
857				     <0 208 4>, <0 209 4>;
858		};
859
860		dspi: spi@2100000 {
861			status = "disabled";
862			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
863			#address-cells = <1>;
864			#size-cells = <0>;
865			reg = <0x0 0x2100000 0x0 0x10000>;
866			interrupts = <0 26 0x4>; /* Level high type */
867			clocks = <&clockgen 4 3>;
868			clock-names = "dspi";
869			spi-num-chipselects = <5>;
870			bus-num = <0>;
871		};
872
873		esdhc: esdhc@2140000 {
874			status = "disabled";
875			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
876			reg = <0x0 0x2140000 0x0 0x10000>;
877			interrupts = <0 28 0x4>; /* Level high type */
878			clocks = <&clockgen 4 1>;
879			voltage-ranges = <1800 1800 3300 3300>;
880			sdhci,auto-cmd12;
881			little-endian;
882			bus-width = <4>;
883		};
884
885		gpio0: gpio@2300000 {
886			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
887			reg = <0x0 0x2300000 0x0 0x10000>;
888			interrupts = <0 36 0x4>; /* Level high type */
889			gpio-controller;
890			little-endian;
891			#gpio-cells = <2>;
892			interrupt-controller;
893			#interrupt-cells = <2>;
894		};
895
896		gpio1: gpio@2310000 {
897			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
898			reg = <0x0 0x2310000 0x0 0x10000>;
899			interrupts = <0 36 0x4>; /* Level high type */
900			gpio-controller;
901			little-endian;
902			#gpio-cells = <2>;
903			interrupt-controller;
904			#interrupt-cells = <2>;
905		};
906
907		gpio2: gpio@2320000 {
908			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
909			reg = <0x0 0x2320000 0x0 0x10000>;
910			interrupts = <0 37 0x4>; /* Level high type */
911			gpio-controller;
912			little-endian;
913			#gpio-cells = <2>;
914			interrupt-controller;
915			#interrupt-cells = <2>;
916		};
917
918		gpio3: gpio@2330000 {
919			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
920			reg = <0x0 0x2330000 0x0 0x10000>;
921			interrupts = <0 37 0x4>; /* Level high type */
922			gpio-controller;
923			little-endian;
924			#gpio-cells = <2>;
925			interrupt-controller;
926			#interrupt-cells = <2>;
927		};
928
929		i2c0: i2c@2000000 {
930			status = "disabled";
931			compatible = "fsl,vf610-i2c";
932			#address-cells = <1>;
933			#size-cells = <0>;
934			reg = <0x0 0x2000000 0x0 0x10000>;
935			interrupts = <0 34 0x4>; /* Level high type */
936			clock-names = "i2c";
937			clocks = <&clockgen 4 3>;
938		};
939
940		i2c1: i2c@2010000 {
941			status = "disabled";
942			compatible = "fsl,vf610-i2c";
943			#address-cells = <1>;
944			#size-cells = <0>;
945			reg = <0x0 0x2010000 0x0 0x10000>;
946			interrupts = <0 34 0x4>; /* Level high type */
947			clock-names = "i2c";
948			clocks = <&clockgen 4 3>;
949		};
950
951		i2c2: i2c@2020000 {
952			status = "disabled";
953			compatible = "fsl,vf610-i2c";
954			#address-cells = <1>;
955			#size-cells = <0>;
956			reg = <0x0 0x2020000 0x0 0x10000>;
957			interrupts = <0 35 0x4>; /* Level high type */
958			clock-names = "i2c";
959			clocks = <&clockgen 4 3>;
960		};
961
962		i2c3: i2c@2030000 {
963			status = "disabled";
964			compatible = "fsl,vf610-i2c";
965			#address-cells = <1>;
966			#size-cells = <0>;
967			reg = <0x0 0x2030000 0x0 0x10000>;
968			interrupts = <0 35 0x4>; /* Level high type */
969			clock-names = "i2c";
970			clocks = <&clockgen 4 3>;
971		};
972
973		ifc: ifc@2240000 {
974			compatible = "fsl,ifc", "simple-bus";
975			reg = <0x0 0x2240000 0x0 0x20000>;
976			interrupts = <0 21 0x4>; /* Level high type */
977			little-endian;
978			#address-cells = <2>;
979			#size-cells = <1>;
980
981			ranges = <0 0 0x5 0x80000000 0x08000000
982				  2 0 0x5 0x30000000 0x00010000
983				  3 0 0x5 0x20000000 0x00010000>;
984		};
985
986		qspi: spi@20c0000 {
987			compatible = "fsl,ls2080a-qspi";
988			#address-cells = <1>;
989			#size-cells = <0>;
990			reg = <0x0 0x20c0000 0x0 0x10000>,
991			      <0x0 0x20000000 0x0 0x10000000>;
992			reg-names = "QuadSPI", "QuadSPI-memory";
993			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
994			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
995			clock-names = "qspi_en", "qspi";
996			status = "disabled";
997		};
998
999		pcie1: pcie@3400000 {
1000			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1001			reg-names = "regs", "config";
1002			interrupts = <0 108 0x4>; /* Level high type */
1003			interrupt-names = "intr";
1004			#address-cells = <3>;
1005			#size-cells = <2>;
1006			device_type = "pci";
1007			dma-coherent;
1008			num-viewport = <6>;
1009			bus-range = <0x0 0xff>;
1010			msi-parent = <&its>;
1011			#interrupt-cells = <1>;
1012			interrupt-map-mask = <0 0 0 7>;
1013			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1014					<0000 0 0 2 &gic 0 0 0 110 4>,
1015					<0000 0 0 3 &gic 0 0 0 111 4>,
1016					<0000 0 0 4 &gic 0 0 0 112 4>;
1017			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1018			status = "disabled";
1019		};
1020
1021		pcie2: pcie@3500000 {
1022			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1023			reg-names = "regs", "config";
1024			interrupts = <0 113 0x4>; /* Level high type */
1025			interrupt-names = "intr";
1026			#address-cells = <3>;
1027			#size-cells = <2>;
1028			device_type = "pci";
1029			dma-coherent;
1030			num-viewport = <6>;
1031			bus-range = <0x0 0xff>;
1032			msi-parent = <&its>;
1033			#interrupt-cells = <1>;
1034			interrupt-map-mask = <0 0 0 7>;
1035			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1036					<0000 0 0 2 &gic 0 0 0 115 4>,
1037					<0000 0 0 3 &gic 0 0 0 116 4>,
1038					<0000 0 0 4 &gic 0 0 0 117 4>;
1039			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1040			status = "disabled";
1041		};
1042
1043		pcie3: pcie@3600000 {
1044			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1045			reg-names = "regs", "config";
1046			interrupts = <0 118 0x4>; /* Level high type */
1047			interrupt-names = "intr";
1048			#address-cells = <3>;
1049			#size-cells = <2>;
1050			device_type = "pci";
1051			dma-coherent;
1052			num-viewport = <256>;
1053			bus-range = <0x0 0xff>;
1054			msi-parent = <&its>;
1055			#interrupt-cells = <1>;
1056			interrupt-map-mask = <0 0 0 7>;
1057			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1058					<0000 0 0 2 &gic 0 0 0 120 4>,
1059					<0000 0 0 3 &gic 0 0 0 121 4>,
1060					<0000 0 0 4 &gic 0 0 0 122 4>;
1061			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1062			status = "disabled";
1063		};
1064
1065		pcie4: pcie@3700000 {
1066			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1067			reg-names = "regs", "config";
1068			interrupts = <0 123 0x4>; /* Level high type */
1069			interrupt-names = "intr";
1070			#address-cells = <3>;
1071			#size-cells = <2>;
1072			device_type = "pci";
1073			dma-coherent;
1074			num-viewport = <6>;
1075			bus-range = <0x0 0xff>;
1076			msi-parent = <&its>;
1077			#interrupt-cells = <1>;
1078			interrupt-map-mask = <0 0 0 7>;
1079			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1080					<0000 0 0 2 &gic 0 0 0 125 4>,
1081					<0000 0 0 3 &gic 0 0 0 126 4>,
1082					<0000 0 0 4 &gic 0 0 0 127 4>;
1083			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1084			status = "disabled";
1085		};
1086
1087		sata0: sata@3200000 {
1088			status = "disabled";
1089			compatible = "fsl,ls2080a-ahci";
1090			reg = <0x0 0x3200000 0x0 0x10000>;
1091			interrupts = <0 133 0x4>; /* Level high type */
1092			clocks = <&clockgen 4 3>;
1093			dma-coherent;
1094		};
1095
1096		sata1: sata@3210000 {
1097			status = "disabled";
1098			compatible = "fsl,ls2080a-ahci";
1099			reg = <0x0 0x3210000 0x0 0x10000>;
1100			interrupts = <0 136 0x4>; /* Level high type */
1101			clocks = <&clockgen 4 3>;
1102			dma-coherent;
1103		};
1104
1105		usb0: usb@3100000 {
1106			status = "disabled";
1107			compatible = "snps,dwc3";
1108			reg = <0x0 0x3100000 0x0 0x10000>;
1109			interrupts = <0 80 0x4>; /* Level high type */
1110			dr_mode = "host";
1111			snps,quirk-frame-length-adjustment = <0x20>;
1112			snps,dis_rxdet_inp3_quirk;
1113			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1114		};
1115
1116		usb1: usb@3110000 {
1117			status = "disabled";
1118			compatible = "snps,dwc3";
1119			reg = <0x0 0x3110000 0x0 0x10000>;
1120			interrupts = <0 81 0x4>; /* Level high type */
1121			dr_mode = "host";
1122			snps,quirk-frame-length-adjustment = <0x20>;
1123			snps,dis_rxdet_inp3_quirk;
1124			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1125		};
1126
1127		ccn@4000000 {
1128			compatible = "arm,ccn-504";
1129			reg = <0x0 0x04000000 0x0 0x01000000>;
1130			interrupts = <0 12 4>;
1131		};
1132
1133		rcpm: power-controller@1e34040 {
1134			compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1135			reg = <0x0 0x1e34040 0x0 0x18>;
1136			#fsl,rcpm-wakeup-cells = <6>;
1137		};
1138
1139		ftm_alarm0: timer@2800000 {
1140			compatible = "fsl,ls208xa-ftm-alarm";
1141			reg = <0x0 0x2800000 0x0 0x10000>;
1142			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1143			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1144		};
1145	};
1146
1147	ddr1: memory-controller@1080000 {
1148		compatible = "fsl,qoriq-memory-controller";
1149		reg = <0x0 0x1080000 0x0 0x1000>;
1150		interrupts = <0 17 0x4>;
1151		little-endian;
1152	};
1153
1154	ddr2: memory-controller@1090000 {
1155		compatible = "fsl,qoriq-memory-controller";
1156		reg = <0x0 0x1090000 0x0 0x1000>;
1157		interrupts = <0 18 0x4>;
1158		little-endian;
1159	};
1160
1161	firmware {
1162		optee {
1163			compatible = "linaro,optee-tz";
1164			method = "smc";
1165		};
1166	};
1167};
1168