1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2017 NXP 7 * 8 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 9 * 10 */ 11 12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14 15/ { 16 compatible = "fsl,ls2080a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 crypto = &crypto; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 }; 26 27 cpu: cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 reg = <0x00000000 0x80000000 0 0x80000000>; 35 /* DRAM space - 1, size : 2 GB DRAM */ 36 }; 37 38 sysclk: sysclk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <100000000>; 42 clock-output-names = "sysclk"; 43 }; 44 45 gic: interrupt-controller@6000000 { 46 compatible = "arm,gic-v3"; 47 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 48 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 49 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 50 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 51 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 52 #interrupt-cells = <3>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 ranges; 56 interrupt-controller; 57 interrupts = <1 9 0x4>; 58 59 its: gic-its@6020000 { 60 compatible = "arm,gic-v3-its"; 61 msi-controller; 62 reg = <0x0 0x6020000 0 0x20000>; 63 }; 64 }; 65 66 rstcr: syscon@1e60000 { 67 compatible = "fsl,ls2080a-rstcr", "syscon"; 68 reg = <0x0 0x1e60000 0x0 0x4>; 69 }; 70 71 reboot { 72 compatible ="syscon-reboot"; 73 regmap = <&rstcr>; 74 offset = <0x0>; 75 mask = <0x2>; 76 }; 77 78 thermal-zones { 79 cpu_thermal: cpu-thermal { 80 polling-delay-passive = <1000>; 81 polling-delay = <5000>; 82 83 thermal-sensors = <&tmu 4>; 84 85 trips { 86 cpu_alert: cpu-alert { 87 temperature = <75000>; 88 hysteresis = <2000>; 89 type = "passive"; 90 }; 91 cpu_crit: cpu-crit { 92 temperature = <85000>; 93 hysteresis = <2000>; 94 type = "critical"; 95 }; 96 }; 97 98 cooling-maps { 99 map0 { 100 trip = <&cpu_alert>; 101 cooling-device = 102 <&cpu0 THERMAL_NO_LIMIT 103 THERMAL_NO_LIMIT>; 104 }; 105 map1 { 106 trip = <&cpu_alert>; 107 cooling-device = 108 <&cpu2 THERMAL_NO_LIMIT 109 THERMAL_NO_LIMIT>; 110 }; 111 map2 { 112 trip = <&cpu_alert>; 113 cooling-device = 114 <&cpu4 THERMAL_NO_LIMIT 115 THERMAL_NO_LIMIT>; 116 }; 117 map3 { 118 trip = <&cpu_alert>; 119 cooling-device = 120 <&cpu6 THERMAL_NO_LIMIT 121 THERMAL_NO_LIMIT>; 122 }; 123 }; 124 }; 125 }; 126 127 timer { 128 compatible = "arm,armv8-timer"; 129 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ 130 <1 14 4>, /* Physical Non-Secure PPI, active-low */ 131 <1 11 4>, /* Virtual PPI, active-low */ 132 <1 10 4>; /* Hypervisor PPI, active-low */ 133 fsl,erratum-a008585; 134 }; 135 136 pmu { 137 compatible = "arm,armv8-pmuv3"; 138 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 139 }; 140 141 psci { 142 compatible = "arm,psci-0.2"; 143 method = "smc"; 144 }; 145 146 soc { 147 compatible = "simple-bus"; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 clockgen: clocking@1300000 { 153 compatible = "fsl,ls2080a-clockgen"; 154 reg = <0 0x1300000 0 0xa0000>; 155 #clock-cells = <2>; 156 clocks = <&sysclk>; 157 }; 158 159 dcfg: dcfg@1e00000 { 160 compatible = "fsl,ls2080a-dcfg", "syscon"; 161 reg = <0x0 0x1e00000 0x0 0x10000>; 162 little-endian; 163 }; 164 165 tmu: tmu@1f80000 { 166 compatible = "fsl,qoriq-tmu"; 167 reg = <0x0 0x1f80000 0x0 0x10000>; 168 interrupts = <0 23 0x4>; 169 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 170 fsl,tmu-calibration = <0x00000000 0x00000026 171 0x00000001 0x0000002d 172 0x00000002 0x00000032 173 0x00000003 0x00000039 174 0x00000004 0x0000003f 175 0x00000005 0x00000046 176 0x00000006 0x0000004d 177 0x00000007 0x00000054 178 0x00000008 0x0000005a 179 0x00000009 0x00000061 180 0x0000000a 0x0000006a 181 0x0000000b 0x00000071 182 183 0x00010000 0x00000025 184 0x00010001 0x0000002c 185 0x00010002 0x00000035 186 0x00010003 0x0000003d 187 0x00010004 0x00000045 188 0x00010005 0x0000004e 189 0x00010006 0x00000057 190 0x00010007 0x00000061 191 0x00010008 0x0000006b 192 0x00010009 0x00000076 193 194 0x00020000 0x00000029 195 0x00020001 0x00000033 196 0x00020002 0x0000003d 197 0x00020003 0x00000049 198 0x00020004 0x00000056 199 0x00020005 0x00000061 200 0x00020006 0x0000006d 201 202 0x00030000 0x00000021 203 0x00030001 0x0000002a 204 0x00030002 0x0000003c 205 0x00030003 0x0000004e>; 206 little-endian; 207 #thermal-sensor-cells = <1>; 208 }; 209 210 serial0: serial@21c0500 { 211 compatible = "fsl,ns16550", "ns16550a"; 212 reg = <0x0 0x21c0500 0x0 0x100>; 213 clocks = <&clockgen 4 3>; 214 interrupts = <0 32 0x4>; /* Level high type */ 215 }; 216 217 serial1: serial@21c0600 { 218 compatible = "fsl,ns16550", "ns16550a"; 219 reg = <0x0 0x21c0600 0x0 0x100>; 220 clocks = <&clockgen 4 3>; 221 interrupts = <0 32 0x4>; /* Level high type */ 222 }; 223 224 cluster1_core0_watchdog: wdt@c000000 { 225 compatible = "arm,sp805-wdt", "arm,primecell"; 226 reg = <0x0 0xc000000 0x0 0x1000>; 227 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 228 clock-names = "apb_pclk", "wdog_clk"; 229 }; 230 231 cluster1_core1_watchdog: wdt@c010000 { 232 compatible = "arm,sp805-wdt", "arm,primecell"; 233 reg = <0x0 0xc010000 0x0 0x1000>; 234 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 235 clock-names = "apb_pclk", "wdog_clk"; 236 }; 237 238 cluster2_core0_watchdog: wdt@c100000 { 239 compatible = "arm,sp805-wdt", "arm,primecell"; 240 reg = <0x0 0xc100000 0x0 0x1000>; 241 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 242 clock-names = "apb_pclk", "wdog_clk"; 243 }; 244 245 cluster2_core1_watchdog: wdt@c110000 { 246 compatible = "arm,sp805-wdt", "arm,primecell"; 247 reg = <0x0 0xc110000 0x0 0x1000>; 248 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 249 clock-names = "apb_pclk", "wdog_clk"; 250 }; 251 252 cluster3_core0_watchdog: wdt@c200000 { 253 compatible = "arm,sp805-wdt", "arm,primecell"; 254 reg = <0x0 0xc200000 0x0 0x1000>; 255 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 256 clock-names = "apb_pclk", "wdog_clk"; 257 }; 258 259 cluster3_core1_watchdog: wdt@c210000 { 260 compatible = "arm,sp805-wdt", "arm,primecell"; 261 reg = <0x0 0xc210000 0x0 0x1000>; 262 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 263 clock-names = "apb_pclk", "wdog_clk"; 264 }; 265 266 cluster4_core0_watchdog: wdt@c300000 { 267 compatible = "arm,sp805-wdt", "arm,primecell"; 268 reg = <0x0 0xc300000 0x0 0x1000>; 269 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 270 clock-names = "apb_pclk", "wdog_clk"; 271 }; 272 273 cluster4_core1_watchdog: wdt@c310000 { 274 compatible = "arm,sp805-wdt", "arm,primecell"; 275 reg = <0x0 0xc310000 0x0 0x1000>; 276 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 277 clock-names = "apb_pclk", "wdog_clk"; 278 }; 279 280 crypto: crypto@8000000 { 281 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 282 fsl,sec-era = <8>; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 ranges = <0x0 0x00 0x8000000 0x100000>; 286 reg = <0x00 0x8000000 0x0 0x100000>; 287 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 288 dma-coherent; 289 290 sec_jr0: jr@10000 { 291 compatible = "fsl,sec-v5.0-job-ring", 292 "fsl,sec-v4.0-job-ring"; 293 reg = <0x10000 0x10000>; 294 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 295 }; 296 297 sec_jr1: jr@20000 { 298 compatible = "fsl,sec-v5.0-job-ring", 299 "fsl,sec-v4.0-job-ring"; 300 reg = <0x20000 0x10000>; 301 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 302 }; 303 304 sec_jr2: jr@30000 { 305 compatible = "fsl,sec-v5.0-job-ring", 306 "fsl,sec-v4.0-job-ring"; 307 reg = <0x30000 0x10000>; 308 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 309 }; 310 311 sec_jr3: jr@40000 { 312 compatible = "fsl,sec-v5.0-job-ring", 313 "fsl,sec-v4.0-job-ring"; 314 reg = <0x40000 0x10000>; 315 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 316 }; 317 }; 318 319 fsl_mc: fsl-mc@80c000000 { 320 compatible = "fsl,qoriq-mc"; 321 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 322 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 323 msi-parent = <&its>; 324 #address-cells = <3>; 325 #size-cells = <1>; 326 327 /* 328 * Region type 0x0 - MC portals 329 * Region type 0x1 - QBMAN portals 330 */ 331 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 332 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 333 334 /* 335 * Define the maximum number of MACs present on the SoC. 336 */ 337 dpmacs { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 341 dpmac1: dpmac@1 { 342 compatible = "fsl,qoriq-mc-dpmac"; 343 reg = <0x1>; 344 }; 345 346 dpmac2: dpmac@2 { 347 compatible = "fsl,qoriq-mc-dpmac"; 348 reg = <0x2>; 349 }; 350 351 dpmac3: dpmac@3 { 352 compatible = "fsl,qoriq-mc-dpmac"; 353 reg = <0x3>; 354 }; 355 356 dpmac4: dpmac@4 { 357 compatible = "fsl,qoriq-mc-dpmac"; 358 reg = <0x4>; 359 }; 360 361 dpmac5: dpmac@5 { 362 compatible = "fsl,qoriq-mc-dpmac"; 363 reg = <0x5>; 364 }; 365 366 dpmac6: dpmac@6 { 367 compatible = "fsl,qoriq-mc-dpmac"; 368 reg = <0x6>; 369 }; 370 371 dpmac7: dpmac@7 { 372 compatible = "fsl,qoriq-mc-dpmac"; 373 reg = <0x7>; 374 }; 375 376 dpmac8: dpmac@8 { 377 compatible = "fsl,qoriq-mc-dpmac"; 378 reg = <0x8>; 379 }; 380 381 dpmac9: dpmac@9 { 382 compatible = "fsl,qoriq-mc-dpmac"; 383 reg = <0x9>; 384 }; 385 386 dpmac10: dpmac@a { 387 compatible = "fsl,qoriq-mc-dpmac"; 388 reg = <0xa>; 389 }; 390 391 dpmac11: dpmac@b { 392 compatible = "fsl,qoriq-mc-dpmac"; 393 reg = <0xb>; 394 }; 395 396 dpmac12: dpmac@c { 397 compatible = "fsl,qoriq-mc-dpmac"; 398 reg = <0xc>; 399 }; 400 401 dpmac13: dpmac@d { 402 compatible = "fsl,qoriq-mc-dpmac"; 403 reg = <0xd>; 404 }; 405 406 dpmac14: dpmac@e { 407 compatible = "fsl,qoriq-mc-dpmac"; 408 reg = <0xe>; 409 }; 410 411 dpmac15: dpmac@f { 412 compatible = "fsl,qoriq-mc-dpmac"; 413 reg = <0xf>; 414 }; 415 416 dpmac16: dpmac@10 { 417 compatible = "fsl,qoriq-mc-dpmac"; 418 reg = <0x10>; 419 }; 420 }; 421 }; 422 423 smmu: iommu@5000000 { 424 compatible = "arm,mmu-500"; 425 reg = <0 0x5000000 0 0x800000>; 426 #global-interrupts = <12>; 427 interrupts = <0 13 4>, /* global secure fault */ 428 <0 14 4>, /* combined secure interrupt */ 429 <0 15 4>, /* global non-secure fault */ 430 <0 16 4>, /* combined non-secure interrupt */ 431 /* performance counter interrupts 0-7 */ 432 <0 211 4>, <0 212 4>, 433 <0 213 4>, <0 214 4>, 434 <0 215 4>, <0 216 4>, 435 <0 217 4>, <0 218 4>, 436 /* per context interrupt, 64 interrupts */ 437 <0 146 4>, <0 147 4>, 438 <0 148 4>, <0 149 4>, 439 <0 150 4>, <0 151 4>, 440 <0 152 4>, <0 153 4>, 441 <0 154 4>, <0 155 4>, 442 <0 156 4>, <0 157 4>, 443 <0 158 4>, <0 159 4>, 444 <0 160 4>, <0 161 4>, 445 <0 162 4>, <0 163 4>, 446 <0 164 4>, <0 165 4>, 447 <0 166 4>, <0 167 4>, 448 <0 168 4>, <0 169 4>, 449 <0 170 4>, <0 171 4>, 450 <0 172 4>, <0 173 4>, 451 <0 174 4>, <0 175 4>, 452 <0 176 4>, <0 177 4>, 453 <0 178 4>, <0 179 4>, 454 <0 180 4>, <0 181 4>, 455 <0 182 4>, <0 183 4>, 456 <0 184 4>, <0 185 4>, 457 <0 186 4>, <0 187 4>, 458 <0 188 4>, <0 189 4>, 459 <0 190 4>, <0 191 4>, 460 <0 192 4>, <0 193 4>, 461 <0 194 4>, <0 195 4>, 462 <0 196 4>, <0 197 4>, 463 <0 198 4>, <0 199 4>, 464 <0 200 4>, <0 201 4>, 465 <0 202 4>, <0 203 4>, 466 <0 204 4>, <0 205 4>, 467 <0 206 4>, <0 207 4>, 468 <0 208 4>, <0 209 4>; 469 mmu-masters = <&fsl_mc 0x300 0>; 470 }; 471 472 dspi: dspi@2100000 { 473 status = "disabled"; 474 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 reg = <0x0 0x2100000 0x0 0x10000>; 478 interrupts = <0 26 0x4>; /* Level high type */ 479 clocks = <&clockgen 4 3>; 480 clock-names = "dspi"; 481 spi-num-chipselects = <5>; 482 bus-num = <0>; 483 }; 484 485 esdhc: esdhc@2140000 { 486 status = "disabled"; 487 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 488 reg = <0x0 0x2140000 0x0 0x10000>; 489 interrupts = <0 28 0x4>; /* Level high type */ 490 clocks = <&clockgen 4 1>; 491 voltage-ranges = <1800 1800 3300 3300>; 492 sdhci,auto-cmd12; 493 little-endian; 494 bus-width = <4>; 495 }; 496 497 gpio0: gpio@2300000 { 498 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 499 reg = <0x0 0x2300000 0x0 0x10000>; 500 interrupts = <0 36 0x4>; /* Level high type */ 501 gpio-controller; 502 little-endian; 503 #gpio-cells = <2>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 }; 507 508 gpio1: gpio@2310000 { 509 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 510 reg = <0x0 0x2310000 0x0 0x10000>; 511 interrupts = <0 36 0x4>; /* Level high type */ 512 gpio-controller; 513 little-endian; 514 #gpio-cells = <2>; 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 }; 518 519 gpio2: gpio@2320000 { 520 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 521 reg = <0x0 0x2320000 0x0 0x10000>; 522 interrupts = <0 37 0x4>; /* Level high type */ 523 gpio-controller; 524 little-endian; 525 #gpio-cells = <2>; 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 }; 529 530 gpio3: gpio@2330000 { 531 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 532 reg = <0x0 0x2330000 0x0 0x10000>; 533 interrupts = <0 37 0x4>; /* Level high type */ 534 gpio-controller; 535 little-endian; 536 #gpio-cells = <2>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 }; 540 541 i2c0: i2c@2000000 { 542 status = "disabled"; 543 compatible = "fsl,vf610-i2c"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 reg = <0x0 0x2000000 0x0 0x10000>; 547 interrupts = <0 34 0x4>; /* Level high type */ 548 clock-names = "i2c"; 549 clocks = <&clockgen 4 3>; 550 }; 551 552 i2c1: i2c@2010000 { 553 status = "disabled"; 554 compatible = "fsl,vf610-i2c"; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 reg = <0x0 0x2010000 0x0 0x10000>; 558 interrupts = <0 34 0x4>; /* Level high type */ 559 clock-names = "i2c"; 560 clocks = <&clockgen 4 3>; 561 }; 562 563 i2c2: i2c@2020000 { 564 status = "disabled"; 565 compatible = "fsl,vf610-i2c"; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 reg = <0x0 0x2020000 0x0 0x10000>; 569 interrupts = <0 35 0x4>; /* Level high type */ 570 clock-names = "i2c"; 571 clocks = <&clockgen 4 3>; 572 }; 573 574 i2c3: i2c@2030000 { 575 status = "disabled"; 576 compatible = "fsl,vf610-i2c"; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 reg = <0x0 0x2030000 0x0 0x10000>; 580 interrupts = <0 35 0x4>; /* Level high type */ 581 clock-names = "i2c"; 582 clocks = <&clockgen 4 3>; 583 }; 584 585 ifc: ifc@2240000 { 586 compatible = "fsl,ifc", "simple-bus"; 587 reg = <0x0 0x2240000 0x0 0x20000>; 588 interrupts = <0 21 0x4>; /* Level high type */ 589 little-endian; 590 #address-cells = <2>; 591 #size-cells = <1>; 592 593 ranges = <0 0 0x5 0x80000000 0x08000000 594 2 0 0x5 0x30000000 0x00010000 595 3 0 0x5 0x20000000 0x00010000>; 596 }; 597 598 qspi: quadspi@20c0000 { 599 status = "disabled"; 600 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 reg = <0x0 0x20c0000 0x0 0x10000>, 604 <0x0 0x20000000 0x0 0x10000000>; 605 reg-names = "QuadSPI", "QuadSPI-memory"; 606 interrupts = <0 25 0x4>; /* Level high type */ 607 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 608 clock-names = "qspi_en", "qspi"; 609 }; 610 611 pcie1: pcie@3400000 { 612 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 613 "snps,dw-pcie"; 614 reg-names = "regs", "config"; 615 interrupts = <0 108 0x4>; /* Level high type */ 616 interrupt-names = "intr"; 617 #address-cells = <3>; 618 #size-cells = <2>; 619 device_type = "pci"; 620 dma-coherent; 621 num-lanes = <4>; 622 bus-range = <0x0 0xff>; 623 msi-parent = <&its>; 624 #interrupt-cells = <1>; 625 interrupt-map-mask = <0 0 0 7>; 626 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, 627 <0000 0 0 2 &gic 0 0 0 110 4>, 628 <0000 0 0 3 &gic 0 0 0 111 4>, 629 <0000 0 0 4 &gic 0 0 0 112 4>; 630 }; 631 632 pcie2: pcie@3500000 { 633 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 634 "snps,dw-pcie"; 635 reg-names = "regs", "config"; 636 interrupts = <0 113 0x4>; /* Level high type */ 637 interrupt-names = "intr"; 638 #address-cells = <3>; 639 #size-cells = <2>; 640 device_type = "pci"; 641 dma-coherent; 642 num-lanes = <4>; 643 bus-range = <0x0 0xff>; 644 msi-parent = <&its>; 645 #interrupt-cells = <1>; 646 interrupt-map-mask = <0 0 0 7>; 647 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, 648 <0000 0 0 2 &gic 0 0 0 115 4>, 649 <0000 0 0 3 &gic 0 0 0 116 4>, 650 <0000 0 0 4 &gic 0 0 0 117 4>; 651 }; 652 653 pcie3: pcie@3600000 { 654 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 655 "snps,dw-pcie"; 656 reg-names = "regs", "config"; 657 interrupts = <0 118 0x4>; /* Level high type */ 658 interrupt-names = "intr"; 659 #address-cells = <3>; 660 #size-cells = <2>; 661 device_type = "pci"; 662 dma-coherent; 663 num-lanes = <8>; 664 bus-range = <0x0 0xff>; 665 msi-parent = <&its>; 666 #interrupt-cells = <1>; 667 interrupt-map-mask = <0 0 0 7>; 668 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, 669 <0000 0 0 2 &gic 0 0 0 120 4>, 670 <0000 0 0 3 &gic 0 0 0 121 4>, 671 <0000 0 0 4 &gic 0 0 0 122 4>; 672 }; 673 674 pcie4: pcie@3700000 { 675 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 676 "snps,dw-pcie"; 677 reg-names = "regs", "config"; 678 interrupts = <0 123 0x4>; /* Level high type */ 679 interrupt-names = "intr"; 680 #address-cells = <3>; 681 #size-cells = <2>; 682 device_type = "pci"; 683 dma-coherent; 684 num-lanes = <4>; 685 bus-range = <0x0 0xff>; 686 msi-parent = <&its>; 687 #interrupt-cells = <1>; 688 interrupt-map-mask = <0 0 0 7>; 689 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, 690 <0000 0 0 2 &gic 0 0 0 125 4>, 691 <0000 0 0 3 &gic 0 0 0 126 4>, 692 <0000 0 0 4 &gic 0 0 0 127 4>; 693 }; 694 695 sata0: sata@3200000 { 696 status = "disabled"; 697 compatible = "fsl,ls2080a-ahci"; 698 reg = <0x0 0x3200000 0x0 0x10000>; 699 interrupts = <0 133 0x4>; /* Level high type */ 700 clocks = <&clockgen 4 3>; 701 dma-coherent; 702 }; 703 704 sata1: sata@3210000 { 705 status = "disabled"; 706 compatible = "fsl,ls2080a-ahci"; 707 reg = <0x0 0x3210000 0x0 0x10000>; 708 interrupts = <0 136 0x4>; /* Level high type */ 709 clocks = <&clockgen 4 3>; 710 dma-coherent; 711 }; 712 713 usb0: usb3@3100000 { 714 status = "disabled"; 715 compatible = "snps,dwc3"; 716 reg = <0x0 0x3100000 0x0 0x10000>; 717 interrupts = <0 80 0x4>; /* Level high type */ 718 dr_mode = "host"; 719 snps,quirk-frame-length-adjustment = <0x20>; 720 snps,dis_rxdet_inp3_quirk; 721 }; 722 723 usb1: usb3@3110000 { 724 status = "disabled"; 725 compatible = "snps,dwc3"; 726 reg = <0x0 0x3110000 0x0 0x10000>; 727 interrupts = <0 81 0x4>; /* Level high type */ 728 dr_mode = "host"; 729 snps,quirk-frame-length-adjustment = <0x20>; 730 snps,dis_rxdet_inp3_quirk; 731 }; 732 733 ccn@4000000 { 734 compatible = "arm,ccn-504"; 735 reg = <0x0 0x04000000 0x0 0x01000000>; 736 interrupts = <0 12 4>; 737 }; 738 }; 739 740 ddr1: memory-controller@1080000 { 741 compatible = "fsl,qoriq-memory-controller"; 742 reg = <0x0 0x1080000 0x0 0x1000>; 743 interrupts = <0 17 0x4>; 744 little-endian; 745 }; 746 747 ddr2: memory-controller@1090000 { 748 compatible = "fsl,qoriq-memory-controller"; 749 reg = <0x0 0x1090000 0x0 0x1000>; 750 interrupts = <0 18 0x4>; 751 little-endian; 752 }; 753 754 firmware { 755 optee { 756 compatible = "linaro,optee-tz"; 757 method = "smc"; 758 }; 759 }; 760}; 761