1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2017 NXP 7 * 8 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 9 * 10 */ 11 12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14 15/ { 16 compatible = "fsl,ls2080a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 crypto = &crypto; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 serial2 = &serial2; 26 serial3 = &serial3; 27 }; 28 29 cpu: cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 reg = <0x00000000 0x80000000 0 0x80000000>; 37 /* DRAM space - 1, size : 2 GB DRAM */ 38 }; 39 40 sysclk: sysclk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <100000000>; 44 clock-output-names = "sysclk"; 45 }; 46 47 gic: interrupt-controller@6000000 { 48 compatible = "arm,gic-v3"; 49 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 50 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 51 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 52 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 53 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 54 #interrupt-cells = <3>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 ranges; 58 interrupt-controller; 59 interrupts = <1 9 0x4>; 60 61 its: gic-its@6020000 { 62 compatible = "arm,gic-v3-its"; 63 msi-controller; 64 reg = <0x0 0x6020000 0 0x20000>; 65 }; 66 }; 67 68 rstcr: syscon@1e60000 { 69 compatible = "fsl,ls2080a-rstcr", "syscon"; 70 reg = <0x0 0x1e60000 0x0 0x4>; 71 }; 72 73 reboot { 74 compatible ="syscon-reboot"; 75 regmap = <&rstcr>; 76 offset = <0x0>; 77 mask = <0x2>; 78 }; 79 80 thermal-zones { 81 cpu_thermal: cpu-thermal { 82 polling-delay-passive = <1000>; 83 polling-delay = <5000>; 84 85 thermal-sensors = <&tmu 4>; 86 87 trips { 88 cpu_alert: cpu-alert { 89 temperature = <75000>; 90 hysteresis = <2000>; 91 type = "passive"; 92 }; 93 cpu_crit: cpu-crit { 94 temperature = <85000>; 95 hysteresis = <2000>; 96 type = "critical"; 97 }; 98 }; 99 100 cooling-maps { 101 map0 { 102 trip = <&cpu_alert>; 103 cooling-device = 104 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 105 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 106 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 107 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 108 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 109 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 110 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 111 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 112 }; 113 }; 114 }; 115 }; 116 117 timer { 118 compatible = "arm,armv8-timer"; 119 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ 120 <1 14 4>, /* Physical Non-Secure PPI, active-low */ 121 <1 11 4>, /* Virtual PPI, active-low */ 122 <1 10 4>; /* Hypervisor PPI, active-low */ 123 fsl,erratum-a008585; 124 }; 125 126 pmu { 127 compatible = "arm,armv8-pmuv3"; 128 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 129 }; 130 131 psci { 132 compatible = "arm,psci-0.2"; 133 method = "smc"; 134 }; 135 136 soc { 137 compatible = "simple-bus"; 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 142 143 clockgen: clocking@1300000 { 144 compatible = "fsl,ls2080a-clockgen"; 145 reg = <0 0x1300000 0 0xa0000>; 146 #clock-cells = <2>; 147 clocks = <&sysclk>; 148 }; 149 150 dcfg: dcfg@1e00000 { 151 compatible = "fsl,ls2080a-dcfg", "syscon"; 152 reg = <0x0 0x1e00000 0x0 0x10000>; 153 little-endian; 154 }; 155 156 tmu: tmu@1f80000 { 157 compatible = "fsl,qoriq-tmu"; 158 reg = <0x0 0x1f80000 0x0 0x10000>; 159 interrupts = <0 23 0x4>; 160 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 161 fsl,tmu-calibration = <0x00000000 0x00000026 162 0x00000001 0x0000002d 163 0x00000002 0x00000032 164 0x00000003 0x00000039 165 0x00000004 0x0000003f 166 0x00000005 0x00000046 167 0x00000006 0x0000004d 168 0x00000007 0x00000054 169 0x00000008 0x0000005a 170 0x00000009 0x00000061 171 0x0000000a 0x0000006a 172 0x0000000b 0x00000071 173 174 0x00010000 0x00000025 175 0x00010001 0x0000002c 176 0x00010002 0x00000035 177 0x00010003 0x0000003d 178 0x00010004 0x00000045 179 0x00010005 0x0000004e 180 0x00010006 0x00000057 181 0x00010007 0x00000061 182 0x00010008 0x0000006b 183 0x00010009 0x00000076 184 185 0x00020000 0x00000029 186 0x00020001 0x00000033 187 0x00020002 0x0000003d 188 0x00020003 0x00000049 189 0x00020004 0x00000056 190 0x00020005 0x00000061 191 0x00020006 0x0000006d 192 193 0x00030000 0x00000021 194 0x00030001 0x0000002a 195 0x00030002 0x0000003c 196 0x00030003 0x0000004e>; 197 little-endian; 198 #thermal-sensor-cells = <1>; 199 }; 200 201 serial0: serial@21c0500 { 202 compatible = "fsl,ns16550", "ns16550a"; 203 reg = <0x0 0x21c0500 0x0 0x100>; 204 clocks = <&clockgen 4 3>; 205 interrupts = <0 32 0x4>; /* Level high type */ 206 }; 207 208 serial1: serial@21c0600 { 209 compatible = "fsl,ns16550", "ns16550a"; 210 reg = <0x0 0x21c0600 0x0 0x100>; 211 clocks = <&clockgen 4 3>; 212 interrupts = <0 32 0x4>; /* Level high type */ 213 }; 214 215 serial2: serial@21d0500 { 216 compatible = "fsl,ns16550", "ns16550a"; 217 reg = <0x0 0x21d0500 0x0 0x100>; 218 clocks = <&clockgen 4 3>; 219 interrupts = <0 33 0x4>; /* Level high type */ 220 }; 221 222 serial3: serial@21d0600 { 223 compatible = "fsl,ns16550", "ns16550a"; 224 reg = <0x0 0x21d0600 0x0 0x100>; 225 clocks = <&clockgen 4 3>; 226 interrupts = <0 33 0x4>; /* Level high type */ 227 }; 228 229 cluster1_core0_watchdog: wdt@c000000 { 230 compatible = "arm,sp805-wdt", "arm,primecell"; 231 reg = <0x0 0xc000000 0x0 0x1000>; 232 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 233 clock-names = "apb_pclk", "wdog_clk"; 234 }; 235 236 cluster1_core1_watchdog: wdt@c010000 { 237 compatible = "arm,sp805-wdt", "arm,primecell"; 238 reg = <0x0 0xc010000 0x0 0x1000>; 239 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 240 clock-names = "apb_pclk", "wdog_clk"; 241 }; 242 243 cluster2_core0_watchdog: wdt@c100000 { 244 compatible = "arm,sp805-wdt", "arm,primecell"; 245 reg = <0x0 0xc100000 0x0 0x1000>; 246 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 247 clock-names = "apb_pclk", "wdog_clk"; 248 }; 249 250 cluster2_core1_watchdog: wdt@c110000 { 251 compatible = "arm,sp805-wdt", "arm,primecell"; 252 reg = <0x0 0xc110000 0x0 0x1000>; 253 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 254 clock-names = "apb_pclk", "wdog_clk"; 255 }; 256 257 cluster3_core0_watchdog: wdt@c200000 { 258 compatible = "arm,sp805-wdt", "arm,primecell"; 259 reg = <0x0 0xc200000 0x0 0x1000>; 260 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 261 clock-names = "apb_pclk", "wdog_clk"; 262 }; 263 264 cluster3_core1_watchdog: wdt@c210000 { 265 compatible = "arm,sp805-wdt", "arm,primecell"; 266 reg = <0x0 0xc210000 0x0 0x1000>; 267 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 268 clock-names = "apb_pclk", "wdog_clk"; 269 }; 270 271 cluster4_core0_watchdog: wdt@c300000 { 272 compatible = "arm,sp805-wdt", "arm,primecell"; 273 reg = <0x0 0xc300000 0x0 0x1000>; 274 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 275 clock-names = "apb_pclk", "wdog_clk"; 276 }; 277 278 cluster4_core1_watchdog: wdt@c310000 { 279 compatible = "arm,sp805-wdt", "arm,primecell"; 280 reg = <0x0 0xc310000 0x0 0x1000>; 281 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 282 clock-names = "apb_pclk", "wdog_clk"; 283 }; 284 285 crypto: crypto@8000000 { 286 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 287 fsl,sec-era = <8>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges = <0x0 0x00 0x8000000 0x100000>; 291 reg = <0x00 0x8000000 0x0 0x100000>; 292 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 293 dma-coherent; 294 295 sec_jr0: jr@10000 { 296 compatible = "fsl,sec-v5.0-job-ring", 297 "fsl,sec-v4.0-job-ring"; 298 reg = <0x10000 0x10000>; 299 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 300 }; 301 302 sec_jr1: jr@20000 { 303 compatible = "fsl,sec-v5.0-job-ring", 304 "fsl,sec-v4.0-job-ring"; 305 reg = <0x20000 0x10000>; 306 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 307 }; 308 309 sec_jr2: jr@30000 { 310 compatible = "fsl,sec-v5.0-job-ring", 311 "fsl,sec-v4.0-job-ring"; 312 reg = <0x30000 0x10000>; 313 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 316 sec_jr3: jr@40000 { 317 compatible = "fsl,sec-v5.0-job-ring", 318 "fsl,sec-v4.0-job-ring"; 319 reg = <0x40000 0x10000>; 320 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 321 }; 322 }; 323 324 fsl_mc: fsl-mc@80c000000 { 325 compatible = "fsl,qoriq-mc"; 326 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 327 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 328 msi-parent = <&its>; 329 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 330 dma-coherent; 331 #address-cells = <3>; 332 #size-cells = <1>; 333 334 /* 335 * Region type 0x0 - MC portals 336 * Region type 0x1 - QBMAN portals 337 */ 338 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 339 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 340 341 /* 342 * Define the maximum number of MACs present on the SoC. 343 */ 344 dpmacs { 345 #address-cells = <1>; 346 #size-cells = <0>; 347 348 dpmac1: dpmac@1 { 349 compatible = "fsl,qoriq-mc-dpmac"; 350 reg = <0x1>; 351 }; 352 353 dpmac2: dpmac@2 { 354 compatible = "fsl,qoriq-mc-dpmac"; 355 reg = <0x2>; 356 }; 357 358 dpmac3: dpmac@3 { 359 compatible = "fsl,qoriq-mc-dpmac"; 360 reg = <0x3>; 361 }; 362 363 dpmac4: dpmac@4 { 364 compatible = "fsl,qoriq-mc-dpmac"; 365 reg = <0x4>; 366 }; 367 368 dpmac5: dpmac@5 { 369 compatible = "fsl,qoriq-mc-dpmac"; 370 reg = <0x5>; 371 }; 372 373 dpmac6: dpmac@6 { 374 compatible = "fsl,qoriq-mc-dpmac"; 375 reg = <0x6>; 376 }; 377 378 dpmac7: dpmac@7 { 379 compatible = "fsl,qoriq-mc-dpmac"; 380 reg = <0x7>; 381 }; 382 383 dpmac8: dpmac@8 { 384 compatible = "fsl,qoriq-mc-dpmac"; 385 reg = <0x8>; 386 }; 387 388 dpmac9: dpmac@9 { 389 compatible = "fsl,qoriq-mc-dpmac"; 390 reg = <0x9>; 391 }; 392 393 dpmac10: dpmac@a { 394 compatible = "fsl,qoriq-mc-dpmac"; 395 reg = <0xa>; 396 }; 397 398 dpmac11: dpmac@b { 399 compatible = "fsl,qoriq-mc-dpmac"; 400 reg = <0xb>; 401 }; 402 403 dpmac12: dpmac@c { 404 compatible = "fsl,qoriq-mc-dpmac"; 405 reg = <0xc>; 406 }; 407 408 dpmac13: dpmac@d { 409 compatible = "fsl,qoriq-mc-dpmac"; 410 reg = <0xd>; 411 }; 412 413 dpmac14: dpmac@e { 414 compatible = "fsl,qoriq-mc-dpmac"; 415 reg = <0xe>; 416 }; 417 418 dpmac15: dpmac@f { 419 compatible = "fsl,qoriq-mc-dpmac"; 420 reg = <0xf>; 421 }; 422 423 dpmac16: dpmac@10 { 424 compatible = "fsl,qoriq-mc-dpmac"; 425 reg = <0x10>; 426 }; 427 }; 428 }; 429 430 smmu: iommu@5000000 { 431 compatible = "arm,mmu-500"; 432 reg = <0 0x5000000 0 0x800000>; 433 #global-interrupts = <12>; 434 #iommu-cells = <1>; 435 stream-match-mask = <0x7C00>; 436 dma-coherent; 437 interrupts = <0 13 4>, /* global secure fault */ 438 <0 14 4>, /* combined secure interrupt */ 439 <0 15 4>, /* global non-secure fault */ 440 <0 16 4>, /* combined non-secure interrupt */ 441 /* performance counter interrupts 0-7 */ 442 <0 211 4>, <0 212 4>, 443 <0 213 4>, <0 214 4>, 444 <0 215 4>, <0 216 4>, 445 <0 217 4>, <0 218 4>, 446 /* per context interrupt, 64 interrupts */ 447 <0 146 4>, <0 147 4>, 448 <0 148 4>, <0 149 4>, 449 <0 150 4>, <0 151 4>, 450 <0 152 4>, <0 153 4>, 451 <0 154 4>, <0 155 4>, 452 <0 156 4>, <0 157 4>, 453 <0 158 4>, <0 159 4>, 454 <0 160 4>, <0 161 4>, 455 <0 162 4>, <0 163 4>, 456 <0 164 4>, <0 165 4>, 457 <0 166 4>, <0 167 4>, 458 <0 168 4>, <0 169 4>, 459 <0 170 4>, <0 171 4>, 460 <0 172 4>, <0 173 4>, 461 <0 174 4>, <0 175 4>, 462 <0 176 4>, <0 177 4>, 463 <0 178 4>, <0 179 4>, 464 <0 180 4>, <0 181 4>, 465 <0 182 4>, <0 183 4>, 466 <0 184 4>, <0 185 4>, 467 <0 186 4>, <0 187 4>, 468 <0 188 4>, <0 189 4>, 469 <0 190 4>, <0 191 4>, 470 <0 192 4>, <0 193 4>, 471 <0 194 4>, <0 195 4>, 472 <0 196 4>, <0 197 4>, 473 <0 198 4>, <0 199 4>, 474 <0 200 4>, <0 201 4>, 475 <0 202 4>, <0 203 4>, 476 <0 204 4>, <0 205 4>, 477 <0 206 4>, <0 207 4>, 478 <0 208 4>, <0 209 4>; 479 }; 480 481 dspi: spi@2100000 { 482 status = "disabled"; 483 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 reg = <0x0 0x2100000 0x0 0x10000>; 487 interrupts = <0 26 0x4>; /* Level high type */ 488 clocks = <&clockgen 4 3>; 489 clock-names = "dspi"; 490 spi-num-chipselects = <5>; 491 bus-num = <0>; 492 }; 493 494 esdhc: esdhc@2140000 { 495 status = "disabled"; 496 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 497 reg = <0x0 0x2140000 0x0 0x10000>; 498 interrupts = <0 28 0x4>; /* Level high type */ 499 clocks = <&clockgen 4 1>; 500 voltage-ranges = <1800 1800 3300 3300>; 501 sdhci,auto-cmd12; 502 little-endian; 503 bus-width = <4>; 504 }; 505 506 gpio0: gpio@2300000 { 507 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 508 reg = <0x0 0x2300000 0x0 0x10000>; 509 interrupts = <0 36 0x4>; /* Level high type */ 510 gpio-controller; 511 little-endian; 512 #gpio-cells = <2>; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 }; 516 517 gpio1: gpio@2310000 { 518 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 519 reg = <0x0 0x2310000 0x0 0x10000>; 520 interrupts = <0 36 0x4>; /* Level high type */ 521 gpio-controller; 522 little-endian; 523 #gpio-cells = <2>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 }; 527 528 gpio2: gpio@2320000 { 529 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 530 reg = <0x0 0x2320000 0x0 0x10000>; 531 interrupts = <0 37 0x4>; /* Level high type */ 532 gpio-controller; 533 little-endian; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 }; 538 539 gpio3: gpio@2330000 { 540 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 541 reg = <0x0 0x2330000 0x0 0x10000>; 542 interrupts = <0 37 0x4>; /* Level high type */ 543 gpio-controller; 544 little-endian; 545 #gpio-cells = <2>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 550 i2c0: i2c@2000000 { 551 status = "disabled"; 552 compatible = "fsl,vf610-i2c"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <0x0 0x2000000 0x0 0x10000>; 556 interrupts = <0 34 0x4>; /* Level high type */ 557 clock-names = "i2c"; 558 clocks = <&clockgen 4 3>; 559 }; 560 561 i2c1: i2c@2010000 { 562 status = "disabled"; 563 compatible = "fsl,vf610-i2c"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 reg = <0x0 0x2010000 0x0 0x10000>; 567 interrupts = <0 34 0x4>; /* Level high type */ 568 clock-names = "i2c"; 569 clocks = <&clockgen 4 3>; 570 }; 571 572 i2c2: i2c@2020000 { 573 status = "disabled"; 574 compatible = "fsl,vf610-i2c"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 reg = <0x0 0x2020000 0x0 0x10000>; 578 interrupts = <0 35 0x4>; /* Level high type */ 579 clock-names = "i2c"; 580 clocks = <&clockgen 4 3>; 581 }; 582 583 i2c3: i2c@2030000 { 584 status = "disabled"; 585 compatible = "fsl,vf610-i2c"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 reg = <0x0 0x2030000 0x0 0x10000>; 589 interrupts = <0 35 0x4>; /* Level high type */ 590 clock-names = "i2c"; 591 clocks = <&clockgen 4 3>; 592 }; 593 594 ifc: ifc@2240000 { 595 compatible = "fsl,ifc", "simple-bus"; 596 reg = <0x0 0x2240000 0x0 0x20000>; 597 interrupts = <0 21 0x4>; /* Level high type */ 598 little-endian; 599 #address-cells = <2>; 600 #size-cells = <1>; 601 602 ranges = <0 0 0x5 0x80000000 0x08000000 603 2 0 0x5 0x30000000 0x00010000 604 3 0 0x5 0x20000000 0x00010000>; 605 }; 606 607 qspi: spi@20c0000 { 608 status = "disabled"; 609 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 reg = <0x0 0x20c0000 0x0 0x10000>, 613 <0x0 0x20000000 0x0 0x10000000>; 614 reg-names = "QuadSPI", "QuadSPI-memory"; 615 interrupts = <0 25 0x4>; /* Level high type */ 616 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 617 clock-names = "qspi_en", "qspi"; 618 }; 619 620 pcie1: pcie@3400000 { 621 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 622 reg-names = "regs", "config"; 623 interrupts = <0 108 0x4>; /* Level high type */ 624 interrupt-names = "intr"; 625 #address-cells = <3>; 626 #size-cells = <2>; 627 device_type = "pci"; 628 dma-coherent; 629 num-lanes = <4>; 630 bus-range = <0x0 0xff>; 631 msi-parent = <&its>; 632 #interrupt-cells = <1>; 633 interrupt-map-mask = <0 0 0 7>; 634 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, 635 <0000 0 0 2 &gic 0 0 0 110 4>, 636 <0000 0 0 3 &gic 0 0 0 111 4>, 637 <0000 0 0 4 &gic 0 0 0 112 4>; 638 status = "disabled"; 639 }; 640 641 pcie2: pcie@3500000 { 642 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 643 reg-names = "regs", "config"; 644 interrupts = <0 113 0x4>; /* Level high type */ 645 interrupt-names = "intr"; 646 #address-cells = <3>; 647 #size-cells = <2>; 648 device_type = "pci"; 649 dma-coherent; 650 num-lanes = <4>; 651 bus-range = <0x0 0xff>; 652 msi-parent = <&its>; 653 #interrupt-cells = <1>; 654 interrupt-map-mask = <0 0 0 7>; 655 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, 656 <0000 0 0 2 &gic 0 0 0 115 4>, 657 <0000 0 0 3 &gic 0 0 0 116 4>, 658 <0000 0 0 4 &gic 0 0 0 117 4>; 659 status = "disabled"; 660 }; 661 662 pcie3: pcie@3600000 { 663 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 664 reg-names = "regs", "config"; 665 interrupts = <0 118 0x4>; /* Level high type */ 666 interrupt-names = "intr"; 667 #address-cells = <3>; 668 #size-cells = <2>; 669 device_type = "pci"; 670 dma-coherent; 671 num-lanes = <8>; 672 bus-range = <0x0 0xff>; 673 msi-parent = <&its>; 674 #interrupt-cells = <1>; 675 interrupt-map-mask = <0 0 0 7>; 676 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, 677 <0000 0 0 2 &gic 0 0 0 120 4>, 678 <0000 0 0 3 &gic 0 0 0 121 4>, 679 <0000 0 0 4 &gic 0 0 0 122 4>; 680 status = "disabled"; 681 }; 682 683 pcie4: pcie@3700000 { 684 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 685 reg-names = "regs", "config"; 686 interrupts = <0 123 0x4>; /* Level high type */ 687 interrupt-names = "intr"; 688 #address-cells = <3>; 689 #size-cells = <2>; 690 device_type = "pci"; 691 dma-coherent; 692 num-lanes = <4>; 693 bus-range = <0x0 0xff>; 694 msi-parent = <&its>; 695 #interrupt-cells = <1>; 696 interrupt-map-mask = <0 0 0 7>; 697 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, 698 <0000 0 0 2 &gic 0 0 0 125 4>, 699 <0000 0 0 3 &gic 0 0 0 126 4>, 700 <0000 0 0 4 &gic 0 0 0 127 4>; 701 status = "disabled"; 702 }; 703 704 sata0: sata@3200000 { 705 status = "disabled"; 706 compatible = "fsl,ls2080a-ahci"; 707 reg = <0x0 0x3200000 0x0 0x10000>; 708 interrupts = <0 133 0x4>; /* Level high type */ 709 clocks = <&clockgen 4 3>; 710 dma-coherent; 711 }; 712 713 sata1: sata@3210000 { 714 status = "disabled"; 715 compatible = "fsl,ls2080a-ahci"; 716 reg = <0x0 0x3210000 0x0 0x10000>; 717 interrupts = <0 136 0x4>; /* Level high type */ 718 clocks = <&clockgen 4 3>; 719 dma-coherent; 720 }; 721 722 usb0: usb3@3100000 { 723 status = "disabled"; 724 compatible = "snps,dwc3"; 725 reg = <0x0 0x3100000 0x0 0x10000>; 726 interrupts = <0 80 0x4>; /* Level high type */ 727 dr_mode = "host"; 728 snps,quirk-frame-length-adjustment = <0x20>; 729 snps,dis_rxdet_inp3_quirk; 730 }; 731 732 usb1: usb3@3110000 { 733 status = "disabled"; 734 compatible = "snps,dwc3"; 735 reg = <0x0 0x3110000 0x0 0x10000>; 736 interrupts = <0 81 0x4>; /* Level high type */ 737 dr_mode = "host"; 738 snps,quirk-frame-length-adjustment = <0x20>; 739 snps,dis_rxdet_inp3_quirk; 740 }; 741 742 ccn@4000000 { 743 compatible = "arm,ccn-504"; 744 reg = <0x0 0x04000000 0x0 0x01000000>; 745 interrupts = <0 12 4>; 746 }; 747 }; 748 749 ddr1: memory-controller@1080000 { 750 compatible = "fsl,qoriq-memory-controller"; 751 reg = <0x0 0x1080000 0x0 0x1000>; 752 interrupts = <0 17 0x4>; 753 little-endian; 754 }; 755 756 ddr2: memory-controller@1090000 { 757 compatible = "fsl,qoriq-memory-controller"; 758 reg = <0x0 0x1090000 0x0 0x1000>; 759 interrupts = <0 18 0x4>; 760 little-endian; 761 }; 762 763 firmware { 764 optee { 765 compatible = "linaro,optee-tz"; 766 method = "smc"; 767 }; 768 }; 769}; 770