1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/thermal/thermal.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/ {
16	compatible = "fsl,ls2080a";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		crypto = &crypto;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		serial2 = &serial2;
26		serial3 = &serial3;
27	};
28
29	cpu: cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32	};
33
34	memory@80000000 {
35		device_type = "memory";
36		reg = <0x00000000 0x80000000 0 0x80000000>;
37		      /* DRAM space - 1, size : 2 GB DRAM */
38	};
39
40	sysclk: sysclk {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <100000000>;
44		clock-output-names = "sysclk";
45	};
46
47	gic: interrupt-controller@6000000 {
48		compatible = "arm,gic-v3";
49		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
50			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
51			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
52			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
53			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
54		#interrupt-cells = <3>;
55		#address-cells = <2>;
56		#size-cells = <2>;
57		ranges;
58		interrupt-controller;
59		interrupts = <1 9 0x4>;
60
61		its: gic-its@6020000 {
62			compatible = "arm,gic-v3-its";
63			msi-controller;
64			reg = <0x0 0x6020000 0 0x20000>;
65		};
66	};
67
68	rstcr: syscon@1e60000 {
69		compatible = "fsl,ls2080a-rstcr", "syscon";
70		reg = <0x0 0x1e60000 0x0 0x4>;
71	};
72
73	reboot {
74		compatible ="syscon-reboot";
75		regmap = <&rstcr>;
76		offset = <0x0>;
77		mask = <0x2>;
78	};
79
80	thermal-zones {
81		cpu_thermal: cpu-thermal {
82			polling-delay-passive = <1000>;
83			polling-delay = <5000>;
84
85			thermal-sensors = <&tmu 4>;
86
87			trips {
88				cpu_alert: cpu-alert {
89					temperature = <75000>;
90					hysteresis = <2000>;
91					type = "passive";
92				};
93				cpu_crit: cpu-crit {
94					temperature = <85000>;
95					hysteresis = <2000>;
96					type = "critical";
97				};
98			};
99
100			cooling-maps {
101				map0 {
102					trip = <&cpu_alert>;
103					cooling-device =
104						<&cpu0 THERMAL_NO_LIMIT
105						THERMAL_NO_LIMIT>;
106				};
107				map1 {
108					trip = <&cpu_alert>;
109					cooling-device =
110						<&cpu2 THERMAL_NO_LIMIT
111						THERMAL_NO_LIMIT>;
112				};
113				map2 {
114					trip = <&cpu_alert>;
115					cooling-device =
116						<&cpu4 THERMAL_NO_LIMIT
117						THERMAL_NO_LIMIT>;
118				};
119				map3 {
120					trip = <&cpu_alert>;
121					cooling-device =
122						<&cpu6 THERMAL_NO_LIMIT
123						THERMAL_NO_LIMIT>;
124				};
125			};
126		};
127	};
128
129	timer {
130		compatible = "arm,armv8-timer";
131		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
132			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
133			     <1 11 4>, /* Virtual PPI, active-low */
134			     <1 10 4>; /* Hypervisor PPI, active-low */
135		fsl,erratum-a008585;
136	};
137
138	pmu {
139		compatible = "arm,armv8-pmuv3";
140		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
141	};
142
143	psci {
144		compatible = "arm,psci-0.2";
145		method = "smc";
146	};
147
148	soc {
149		compatible = "simple-bus";
150		#address-cells = <2>;
151		#size-cells = <2>;
152		ranges;
153		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
154
155		clockgen: clocking@1300000 {
156			compatible = "fsl,ls2080a-clockgen";
157			reg = <0 0x1300000 0 0xa0000>;
158			#clock-cells = <2>;
159			clocks = <&sysclk>;
160		};
161
162		dcfg: dcfg@1e00000 {
163			compatible = "fsl,ls2080a-dcfg", "syscon";
164			reg = <0x0 0x1e00000 0x0 0x10000>;
165			little-endian;
166		};
167
168		tmu: tmu@1f80000 {
169			compatible = "fsl,qoriq-tmu";
170			reg = <0x0 0x1f80000 0x0 0x10000>;
171			interrupts = <0 23 0x4>;
172			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
173			fsl,tmu-calibration = <0x00000000 0x00000026
174					       0x00000001 0x0000002d
175					       0x00000002 0x00000032
176					       0x00000003 0x00000039
177					       0x00000004 0x0000003f
178					       0x00000005 0x00000046
179					       0x00000006 0x0000004d
180					       0x00000007 0x00000054
181					       0x00000008 0x0000005a
182					       0x00000009 0x00000061
183					       0x0000000a 0x0000006a
184					       0x0000000b 0x00000071
185
186					       0x00010000 0x00000025
187					       0x00010001 0x0000002c
188					       0x00010002 0x00000035
189					       0x00010003 0x0000003d
190					       0x00010004 0x00000045
191					       0x00010005 0x0000004e
192					       0x00010006 0x00000057
193					       0x00010007 0x00000061
194					       0x00010008 0x0000006b
195					       0x00010009 0x00000076
196
197					       0x00020000 0x00000029
198					       0x00020001 0x00000033
199					       0x00020002 0x0000003d
200					       0x00020003 0x00000049
201					       0x00020004 0x00000056
202					       0x00020005 0x00000061
203					       0x00020006 0x0000006d
204
205					       0x00030000 0x00000021
206					       0x00030001 0x0000002a
207					       0x00030002 0x0000003c
208					       0x00030003 0x0000004e>;
209			little-endian;
210			#thermal-sensor-cells = <1>;
211		};
212
213		serial0: serial@21c0500 {
214			compatible = "fsl,ns16550", "ns16550a";
215			reg = <0x0 0x21c0500 0x0 0x100>;
216			clocks = <&clockgen 4 3>;
217			interrupts = <0 32 0x4>; /* Level high type */
218		};
219
220		serial1: serial@21c0600 {
221			compatible = "fsl,ns16550", "ns16550a";
222			reg = <0x0 0x21c0600 0x0 0x100>;
223			clocks = <&clockgen 4 3>;
224			interrupts = <0 32 0x4>; /* Level high type */
225		};
226
227		serial2: serial@21d0500 {
228			compatible = "fsl,ns16550", "ns16550a";
229			reg = <0x0 0x21d0500 0x0 0x100>;
230			clocks = <&clockgen 4 3>;
231			interrupts = <0 33 0x4>; /* Level high type */
232		};
233
234		serial3: serial@21d0600 {
235			compatible = "fsl,ns16550", "ns16550a";
236			reg = <0x0 0x21d0600 0x0 0x100>;
237			clocks = <&clockgen 4 3>;
238			interrupts = <0 33 0x4>; /* Level high type */
239		};
240
241		cluster1_core0_watchdog: wdt@c000000 {
242			compatible = "arm,sp805-wdt", "arm,primecell";
243			reg = <0x0 0xc000000 0x0 0x1000>;
244			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
245			clock-names = "apb_pclk", "wdog_clk";
246		};
247
248		cluster1_core1_watchdog: wdt@c010000 {
249			compatible = "arm,sp805-wdt", "arm,primecell";
250			reg = <0x0 0xc010000 0x0 0x1000>;
251			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
252			clock-names = "apb_pclk", "wdog_clk";
253		};
254
255		cluster2_core0_watchdog: wdt@c100000 {
256			compatible = "arm,sp805-wdt", "arm,primecell";
257			reg = <0x0 0xc100000 0x0 0x1000>;
258			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
259			clock-names = "apb_pclk", "wdog_clk";
260		};
261
262		cluster2_core1_watchdog: wdt@c110000 {
263			compatible = "arm,sp805-wdt", "arm,primecell";
264			reg = <0x0 0xc110000 0x0 0x1000>;
265			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
266			clock-names = "apb_pclk", "wdog_clk";
267		};
268
269		cluster3_core0_watchdog: wdt@c200000 {
270			compatible = "arm,sp805-wdt", "arm,primecell";
271			reg = <0x0 0xc200000 0x0 0x1000>;
272			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
273			clock-names = "apb_pclk", "wdog_clk";
274		};
275
276		cluster3_core1_watchdog: wdt@c210000 {
277			compatible = "arm,sp805-wdt", "arm,primecell";
278			reg = <0x0 0xc210000 0x0 0x1000>;
279			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
280			clock-names = "apb_pclk", "wdog_clk";
281		};
282
283		cluster4_core0_watchdog: wdt@c300000 {
284			compatible = "arm,sp805-wdt", "arm,primecell";
285			reg = <0x0 0xc300000 0x0 0x1000>;
286			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
287			clock-names = "apb_pclk", "wdog_clk";
288		};
289
290		cluster4_core1_watchdog: wdt@c310000 {
291			compatible = "arm,sp805-wdt", "arm,primecell";
292			reg = <0x0 0xc310000 0x0 0x1000>;
293			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
294			clock-names = "apb_pclk", "wdog_clk";
295		};
296
297		crypto: crypto@8000000 {
298			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
299			fsl,sec-era = <8>;
300			#address-cells = <1>;
301			#size-cells = <1>;
302			ranges = <0x0 0x00 0x8000000 0x100000>;
303			reg = <0x00 0x8000000 0x0 0x100000>;
304			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
305			dma-coherent;
306
307			sec_jr0: jr@10000 {
308				compatible = "fsl,sec-v5.0-job-ring",
309					     "fsl,sec-v4.0-job-ring";
310				reg	   = <0x10000 0x10000>;
311				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
312			};
313
314			sec_jr1: jr@20000 {
315				compatible = "fsl,sec-v5.0-job-ring",
316					     "fsl,sec-v4.0-job-ring";
317				reg	   = <0x20000 0x10000>;
318				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
319			};
320
321			sec_jr2: jr@30000 {
322				compatible = "fsl,sec-v5.0-job-ring",
323					     "fsl,sec-v4.0-job-ring";
324				reg	   = <0x30000 0x10000>;
325				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
326			};
327
328			sec_jr3: jr@40000 {
329				compatible = "fsl,sec-v5.0-job-ring",
330					     "fsl,sec-v4.0-job-ring";
331				reg	   = <0x40000 0x10000>;
332				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
333			};
334		};
335
336		fsl_mc: fsl-mc@80c000000 {
337			compatible = "fsl,qoriq-mc";
338			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
339			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
340			msi-parent = <&its>;
341			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
342			dma-coherent;
343			#address-cells = <3>;
344			#size-cells = <1>;
345
346			/*
347			 * Region type 0x0 - MC portals
348			 * Region type 0x1 - QBMAN portals
349			 */
350			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
351				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
352
353			/*
354			 * Define the maximum number of MACs present on the SoC.
355			 */
356			dpmacs {
357				#address-cells = <1>;
358				#size-cells = <0>;
359
360				dpmac1: dpmac@1 {
361					compatible = "fsl,qoriq-mc-dpmac";
362					reg = <0x1>;
363				};
364
365				dpmac2: dpmac@2 {
366					compatible = "fsl,qoriq-mc-dpmac";
367					reg = <0x2>;
368				};
369
370				dpmac3: dpmac@3 {
371					compatible = "fsl,qoriq-mc-dpmac";
372					reg = <0x3>;
373				};
374
375				dpmac4: dpmac@4 {
376					compatible = "fsl,qoriq-mc-dpmac";
377					reg = <0x4>;
378				};
379
380				dpmac5: dpmac@5 {
381					compatible = "fsl,qoriq-mc-dpmac";
382					reg = <0x5>;
383				};
384
385				dpmac6: dpmac@6 {
386					compatible = "fsl,qoriq-mc-dpmac";
387					reg = <0x6>;
388				};
389
390				dpmac7: dpmac@7 {
391					compatible = "fsl,qoriq-mc-dpmac";
392					reg = <0x7>;
393				};
394
395				dpmac8: dpmac@8 {
396					compatible = "fsl,qoriq-mc-dpmac";
397					reg = <0x8>;
398				};
399
400				dpmac9: dpmac@9 {
401					compatible = "fsl,qoriq-mc-dpmac";
402					reg = <0x9>;
403				};
404
405				dpmac10: dpmac@a {
406					compatible = "fsl,qoriq-mc-dpmac";
407					reg = <0xa>;
408				};
409
410				dpmac11: dpmac@b {
411					compatible = "fsl,qoriq-mc-dpmac";
412					reg = <0xb>;
413				};
414
415				dpmac12: dpmac@c {
416					compatible = "fsl,qoriq-mc-dpmac";
417					reg = <0xc>;
418				};
419
420				dpmac13: dpmac@d {
421					compatible = "fsl,qoriq-mc-dpmac";
422					reg = <0xd>;
423				};
424
425				dpmac14: dpmac@e {
426					compatible = "fsl,qoriq-mc-dpmac";
427					reg = <0xe>;
428				};
429
430				dpmac15: dpmac@f {
431					compatible = "fsl,qoriq-mc-dpmac";
432					reg = <0xf>;
433				};
434
435				dpmac16: dpmac@10 {
436					compatible = "fsl,qoriq-mc-dpmac";
437					reg = <0x10>;
438				};
439			};
440		};
441
442		smmu: iommu@5000000 {
443			compatible = "arm,mmu-500";
444			reg = <0 0x5000000 0 0x800000>;
445			#global-interrupts = <12>;
446			#iommu-cells = <1>;
447			stream-match-mask = <0x7C00>;
448			dma-coherent;
449			interrupts = <0 13 4>, /* global secure fault */
450				     <0 14 4>, /* combined secure interrupt */
451				     <0 15 4>, /* global non-secure fault */
452				     <0 16 4>, /* combined non-secure interrupt */
453				/* performance counter interrupts 0-7 */
454				     <0 211 4>, <0 212 4>,
455				     <0 213 4>, <0 214 4>,
456				     <0 215 4>, <0 216 4>,
457				     <0 217 4>, <0 218 4>,
458				/* per context interrupt, 64 interrupts */
459				     <0 146 4>, <0 147 4>,
460				     <0 148 4>, <0 149 4>,
461				     <0 150 4>, <0 151 4>,
462				     <0 152 4>, <0 153 4>,
463				     <0 154 4>, <0 155 4>,
464				     <0 156 4>, <0 157 4>,
465				     <0 158 4>, <0 159 4>,
466				     <0 160 4>, <0 161 4>,
467				     <0 162 4>, <0 163 4>,
468				     <0 164 4>, <0 165 4>,
469				     <0 166 4>, <0 167 4>,
470				     <0 168 4>, <0 169 4>,
471				     <0 170 4>, <0 171 4>,
472				     <0 172 4>, <0 173 4>,
473				     <0 174 4>, <0 175 4>,
474				     <0 176 4>, <0 177 4>,
475				     <0 178 4>, <0 179 4>,
476				     <0 180 4>, <0 181 4>,
477				     <0 182 4>, <0 183 4>,
478				     <0 184 4>, <0 185 4>,
479				     <0 186 4>, <0 187 4>,
480				     <0 188 4>, <0 189 4>,
481				     <0 190 4>, <0 191 4>,
482				     <0 192 4>, <0 193 4>,
483				     <0 194 4>, <0 195 4>,
484				     <0 196 4>, <0 197 4>,
485				     <0 198 4>, <0 199 4>,
486				     <0 200 4>, <0 201 4>,
487				     <0 202 4>, <0 203 4>,
488				     <0 204 4>, <0 205 4>,
489				     <0 206 4>, <0 207 4>,
490				     <0 208 4>, <0 209 4>;
491		};
492
493		dspi: spi@2100000 {
494			status = "disabled";
495			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
496			#address-cells = <1>;
497			#size-cells = <0>;
498			reg = <0x0 0x2100000 0x0 0x10000>;
499			interrupts = <0 26 0x4>; /* Level high type */
500			clocks = <&clockgen 4 3>;
501			clock-names = "dspi";
502			spi-num-chipselects = <5>;
503			bus-num = <0>;
504		};
505
506		esdhc: esdhc@2140000 {
507			status = "disabled";
508			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
509			reg = <0x0 0x2140000 0x0 0x10000>;
510			interrupts = <0 28 0x4>; /* Level high type */
511			clocks = <&clockgen 4 1>;
512			voltage-ranges = <1800 1800 3300 3300>;
513			sdhci,auto-cmd12;
514			little-endian;
515			bus-width = <4>;
516		};
517
518		gpio0: gpio@2300000 {
519			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
520			reg = <0x0 0x2300000 0x0 0x10000>;
521			interrupts = <0 36 0x4>; /* Level high type */
522			gpio-controller;
523			little-endian;
524			#gpio-cells = <2>;
525			interrupt-controller;
526			#interrupt-cells = <2>;
527		};
528
529		gpio1: gpio@2310000 {
530			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
531			reg = <0x0 0x2310000 0x0 0x10000>;
532			interrupts = <0 36 0x4>; /* Level high type */
533			gpio-controller;
534			little-endian;
535			#gpio-cells = <2>;
536			interrupt-controller;
537			#interrupt-cells = <2>;
538		};
539
540		gpio2: gpio@2320000 {
541			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
542			reg = <0x0 0x2320000 0x0 0x10000>;
543			interrupts = <0 37 0x4>; /* Level high type */
544			gpio-controller;
545			little-endian;
546			#gpio-cells = <2>;
547			interrupt-controller;
548			#interrupt-cells = <2>;
549		};
550
551		gpio3: gpio@2330000 {
552			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
553			reg = <0x0 0x2330000 0x0 0x10000>;
554			interrupts = <0 37 0x4>; /* Level high type */
555			gpio-controller;
556			little-endian;
557			#gpio-cells = <2>;
558			interrupt-controller;
559			#interrupt-cells = <2>;
560		};
561
562		i2c0: i2c@2000000 {
563			status = "disabled";
564			compatible = "fsl,vf610-i2c";
565			#address-cells = <1>;
566			#size-cells = <0>;
567			reg = <0x0 0x2000000 0x0 0x10000>;
568			interrupts = <0 34 0x4>; /* Level high type */
569			clock-names = "i2c";
570			clocks = <&clockgen 4 3>;
571		};
572
573		i2c1: i2c@2010000 {
574			status = "disabled";
575			compatible = "fsl,vf610-i2c";
576			#address-cells = <1>;
577			#size-cells = <0>;
578			reg = <0x0 0x2010000 0x0 0x10000>;
579			interrupts = <0 34 0x4>; /* Level high type */
580			clock-names = "i2c";
581			clocks = <&clockgen 4 3>;
582		};
583
584		i2c2: i2c@2020000 {
585			status = "disabled";
586			compatible = "fsl,vf610-i2c";
587			#address-cells = <1>;
588			#size-cells = <0>;
589			reg = <0x0 0x2020000 0x0 0x10000>;
590			interrupts = <0 35 0x4>; /* Level high type */
591			clock-names = "i2c";
592			clocks = <&clockgen 4 3>;
593		};
594
595		i2c3: i2c@2030000 {
596			status = "disabled";
597			compatible = "fsl,vf610-i2c";
598			#address-cells = <1>;
599			#size-cells = <0>;
600			reg = <0x0 0x2030000 0x0 0x10000>;
601			interrupts = <0 35 0x4>; /* Level high type */
602			clock-names = "i2c";
603			clocks = <&clockgen 4 3>;
604		};
605
606		ifc: ifc@2240000 {
607			compatible = "fsl,ifc", "simple-bus";
608			reg = <0x0 0x2240000 0x0 0x20000>;
609			interrupts = <0 21 0x4>; /* Level high type */
610			little-endian;
611			#address-cells = <2>;
612			#size-cells = <1>;
613
614			ranges = <0 0 0x5 0x80000000 0x08000000
615				  2 0 0x5 0x30000000 0x00010000
616				  3 0 0x5 0x20000000 0x00010000>;
617		};
618
619		qspi: spi@20c0000 {
620			status = "disabled";
621			compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
622			#address-cells = <1>;
623			#size-cells = <0>;
624			reg = <0x0 0x20c0000 0x0 0x10000>,
625			      <0x0 0x20000000 0x0 0x10000000>;
626			reg-names = "QuadSPI", "QuadSPI-memory";
627			interrupts = <0 25 0x4>; /* Level high type */
628			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
629			clock-names = "qspi_en", "qspi";
630		};
631
632		pcie1: pcie@3400000 {
633			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
634				     "snps,dw-pcie";
635			reg-names = "regs", "config";
636			interrupts = <0 108 0x4>; /* Level high type */
637			interrupt-names = "intr";
638			#address-cells = <3>;
639			#size-cells = <2>;
640			device_type = "pci";
641			dma-coherent;
642			num-lanes = <4>;
643			bus-range = <0x0 0xff>;
644			msi-parent = <&its>;
645			#interrupt-cells = <1>;
646			interrupt-map-mask = <0 0 0 7>;
647			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
648					<0000 0 0 2 &gic 0 0 0 110 4>,
649					<0000 0 0 3 &gic 0 0 0 111 4>,
650					<0000 0 0 4 &gic 0 0 0 112 4>;
651		};
652
653		pcie2: pcie@3500000 {
654			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
655				     "snps,dw-pcie";
656			reg-names = "regs", "config";
657			interrupts = <0 113 0x4>; /* Level high type */
658			interrupt-names = "intr";
659			#address-cells = <3>;
660			#size-cells = <2>;
661			device_type = "pci";
662			dma-coherent;
663			num-lanes = <4>;
664			bus-range = <0x0 0xff>;
665			msi-parent = <&its>;
666			#interrupt-cells = <1>;
667			interrupt-map-mask = <0 0 0 7>;
668			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
669					<0000 0 0 2 &gic 0 0 0 115 4>,
670					<0000 0 0 3 &gic 0 0 0 116 4>,
671					<0000 0 0 4 &gic 0 0 0 117 4>;
672		};
673
674		pcie3: pcie@3600000 {
675			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
676				     "snps,dw-pcie";
677			reg-names = "regs", "config";
678			interrupts = <0 118 0x4>; /* Level high type */
679			interrupt-names = "intr";
680			#address-cells = <3>;
681			#size-cells = <2>;
682			device_type = "pci";
683			dma-coherent;
684			num-lanes = <8>;
685			bus-range = <0x0 0xff>;
686			msi-parent = <&its>;
687			#interrupt-cells = <1>;
688			interrupt-map-mask = <0 0 0 7>;
689			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
690					<0000 0 0 2 &gic 0 0 0 120 4>,
691					<0000 0 0 3 &gic 0 0 0 121 4>,
692					<0000 0 0 4 &gic 0 0 0 122 4>;
693		};
694
695		pcie4: pcie@3700000 {
696			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
697				     "snps,dw-pcie";
698			reg-names = "regs", "config";
699			interrupts = <0 123 0x4>; /* Level high type */
700			interrupt-names = "intr";
701			#address-cells = <3>;
702			#size-cells = <2>;
703			device_type = "pci";
704			dma-coherent;
705			num-lanes = <4>;
706			bus-range = <0x0 0xff>;
707			msi-parent = <&its>;
708			#interrupt-cells = <1>;
709			interrupt-map-mask = <0 0 0 7>;
710			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
711					<0000 0 0 2 &gic 0 0 0 125 4>,
712					<0000 0 0 3 &gic 0 0 0 126 4>,
713					<0000 0 0 4 &gic 0 0 0 127 4>;
714		};
715
716		sata0: sata@3200000 {
717			status = "disabled";
718			compatible = "fsl,ls2080a-ahci";
719			reg = <0x0 0x3200000 0x0 0x10000>;
720			interrupts = <0 133 0x4>; /* Level high type */
721			clocks = <&clockgen 4 3>;
722			dma-coherent;
723		};
724
725		sata1: sata@3210000 {
726			status = "disabled";
727			compatible = "fsl,ls2080a-ahci";
728			reg = <0x0 0x3210000 0x0 0x10000>;
729			interrupts = <0 136 0x4>; /* Level high type */
730			clocks = <&clockgen 4 3>;
731			dma-coherent;
732		};
733
734		usb0: usb3@3100000 {
735			status = "disabled";
736			compatible = "snps,dwc3";
737			reg = <0x0 0x3100000 0x0 0x10000>;
738			interrupts = <0 80 0x4>; /* Level high type */
739			dr_mode = "host";
740			snps,quirk-frame-length-adjustment = <0x20>;
741			snps,dis_rxdet_inp3_quirk;
742		};
743
744		usb1: usb3@3110000 {
745			status = "disabled";
746			compatible = "snps,dwc3";
747			reg = <0x0 0x3110000 0x0 0x10000>;
748			interrupts = <0 81 0x4>; /* Level high type */
749			dr_mode = "host";
750			snps,quirk-frame-length-adjustment = <0x20>;
751			snps,dis_rxdet_inp3_quirk;
752		};
753
754		ccn@4000000 {
755			compatible = "arm,ccn-504";
756			reg = <0x0 0x04000000 0x0 0x01000000>;
757			interrupts = <0 12 4>;
758		};
759	};
760
761	ddr1: memory-controller@1080000 {
762		compatible = "fsl,qoriq-memory-controller";
763		reg = <0x0 0x1080000 0x0 0x1000>;
764		interrupts = <0 17 0x4>;
765		little-endian;
766	};
767
768	ddr2: memory-controller@1090000 {
769		compatible = "fsl,qoriq-memory-controller";
770		reg = <0x0 0x1090000 0x0 0x1000>;
771		interrupts = <0 18 0x4>;
772		little-endian;
773	};
774
775	firmware {
776		optee {
777			compatible = "linaro,optee-tz";
778			method = "smc";
779		};
780	};
781};
782