1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/thermal/thermal.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
15/ {
16	compatible = "fsl,ls2080a";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		crypto = &crypto;
23		rtc1 = &ftm_alarm0;
24		serial0 = &serial0;
25		serial1 = &serial1;
26		serial2 = &serial2;
27		serial3 = &serial3;
28	};
29
30	cpu: cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33	};
34
35	memory@80000000 {
36		device_type = "memory";
37		reg = <0x00000000 0x80000000 0 0x80000000>;
38		      /* DRAM space - 1, size : 2 GB DRAM */
39	};
40
41	sysclk: sysclk {
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <100000000>;
45		clock-output-names = "sysclk";
46	};
47
48	gic: interrupt-controller@6000000 {
49		compatible = "arm,gic-v3";
50		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
51			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
52			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
53			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
54			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
55		#interrupt-cells = <3>;
56		#address-cells = <2>;
57		#size-cells = <2>;
58		ranges;
59		interrupt-controller;
60		interrupts = <1 9 0x4>;
61
62		its: gic-its@6020000 {
63			compatible = "arm,gic-v3-its";
64			msi-controller;
65			reg = <0x0 0x6020000 0 0x20000>;
66		};
67	};
68
69	rstcr: syscon@1e60000 {
70		compatible = "fsl,ls2080a-rstcr", "syscon";
71		reg = <0x0 0x1e60000 0x0 0x4>;
72	};
73
74	reboot {
75		compatible ="syscon-reboot";
76		regmap = <&rstcr>;
77		offset = <0x0>;
78		mask = <0x2>;
79	};
80
81	thermal-zones {
82		ddr-controller1 {
83			polling-delay-passive = <1000>;
84			polling-delay = <5000>;
85			thermal-sensors = <&tmu 1>;
86
87			trips {
88				ddr-ctrler1-crit {
89					temperature = <95000>;
90					hysteresis = <2000>;
91					type = "critical";
92				};
93			};
94		};
95
96		ddr-controller2 {
97			polling-delay-passive = <1000>;
98			polling-delay = <5000>;
99			thermal-sensors = <&tmu 2>;
100
101			trips {
102				ddr-ctrler2-crit {
103					temperature = <95000>;
104					hysteresis = <2000>;
105					type = "critical";
106				};
107			};
108		};
109
110		ddr-controller3 {
111			polling-delay-passive = <1000>;
112			polling-delay = <5000>;
113			thermal-sensors = <&tmu 3>;
114
115			trips {
116				ddr-ctrler3-crit {
117					temperature = <95000>;
118					hysteresis = <2000>;
119					type = "critical";
120				};
121			};
122		};
123
124		core-cluster1 {
125			polling-delay-passive = <1000>;
126			polling-delay = <5000>;
127			thermal-sensors = <&tmu 4>;
128
129			trips {
130				core_cluster1_alert: core-cluster1-alert {
131					temperature = <85000>;
132					hysteresis = <2000>;
133					type = "passive";
134				};
135
136				core-cluster1-crit {
137					temperature = <95000>;
138					hysteresis = <2000>;
139					type = "critical";
140				};
141			};
142
143			cooling-maps {
144				map0 {
145					trip = <&core_cluster1_alert>;
146					cooling-device =
147						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
148						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149				};
150			};
151		};
152
153		core-cluster2 {
154			polling-delay-passive = <1000>;
155			polling-delay = <5000>;
156			thermal-sensors = <&tmu 5>;
157
158			trips {
159				core_cluster2_alert: core-cluster2-alert {
160					temperature = <85000>;
161					hysteresis = <2000>;
162					type = "passive";
163				};
164
165				core-cluster2-crit {
166					temperature = <95000>;
167					hysteresis = <2000>;
168					type = "critical";
169				};
170			};
171
172			cooling-maps {
173				map0 {
174					trip = <&core_cluster2_alert>;
175					cooling-device =
176						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
177						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
178				};
179			};
180		};
181
182		core-cluster3 {
183			polling-delay-passive = <1000>;
184			polling-delay = <5000>;
185			thermal-sensors = <&tmu 6>;
186
187			trips {
188				core_cluster3_alert: core-cluster3-alert {
189					temperature = <85000>;
190					hysteresis = <2000>;
191					type = "passive";
192				};
193
194				core-cluster3-crit {
195					temperature = <95000>;
196					hysteresis = <2000>;
197					type = "critical";
198				};
199			};
200
201			cooling-maps {
202				map0 {
203					trip = <&core_cluster3_alert>;
204					cooling-device =
205						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
207				};
208			};
209		};
210
211		core-cluster4 {
212			polling-delay-passive = <1000>;
213			polling-delay = <5000>;
214			thermal-sensors = <&tmu 7>;
215
216			trips {
217				core_cluster4_alert: core-cluster4-alert {
218					temperature = <85000>;
219					hysteresis = <2000>;
220					type = "passive";
221				};
222
223				core-cluster4-crit {
224					temperature = <95000>;
225					hysteresis = <2000>;
226					type = "critical";
227				};
228			};
229
230			cooling-maps {
231				map0 {
232					trip = <&core_cluster4_alert>;
233					cooling-device =
234						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
235						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
236				};
237			};
238		};
239	};
240
241	timer {
242		compatible = "arm,armv8-timer";
243		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
244			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
245			     <1 11 4>, /* Virtual PPI, active-low */
246			     <1 10 4>; /* Hypervisor PPI, active-low */
247		fsl,erratum-a008585;
248	};
249
250	pmu {
251		compatible = "arm,armv8-pmuv3";
252		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
253	};
254
255	psci {
256		compatible = "arm,psci-0.2";
257		method = "smc";
258	};
259
260	soc {
261		compatible = "simple-bus";
262		#address-cells = <2>;
263		#size-cells = <2>;
264		ranges;
265		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
266
267		clockgen: clocking@1300000 {
268			compatible = "fsl,ls2080a-clockgen";
269			reg = <0 0x1300000 0 0xa0000>;
270			#clock-cells = <2>;
271			clocks = <&sysclk>;
272		};
273
274		dcfg: dcfg@1e00000 {
275			compatible = "fsl,ls2080a-dcfg", "syscon";
276			reg = <0x0 0x1e00000 0x0 0x10000>;
277			little-endian;
278		};
279
280		tmu: tmu@1f80000 {
281			compatible = "fsl,qoriq-tmu";
282			reg = <0x0 0x1f80000 0x0 0x10000>;
283			interrupts = <0 23 0x4>;
284			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
285			fsl,tmu-calibration = <0x00000000 0x00000026
286					       0x00000001 0x0000002d
287					       0x00000002 0x00000032
288					       0x00000003 0x00000039
289					       0x00000004 0x0000003f
290					       0x00000005 0x00000046
291					       0x00000006 0x0000004d
292					       0x00000007 0x00000054
293					       0x00000008 0x0000005a
294					       0x00000009 0x00000061
295					       0x0000000a 0x0000006a
296					       0x0000000b 0x00000071
297
298					       0x00010000 0x00000025
299					       0x00010001 0x0000002c
300					       0x00010002 0x00000035
301					       0x00010003 0x0000003d
302					       0x00010004 0x00000045
303					       0x00010005 0x0000004e
304					       0x00010006 0x00000057
305					       0x00010007 0x00000061
306					       0x00010008 0x0000006b
307					       0x00010009 0x00000076
308
309					       0x00020000 0x00000029
310					       0x00020001 0x00000033
311					       0x00020002 0x0000003d
312					       0x00020003 0x00000049
313					       0x00020004 0x00000056
314					       0x00020005 0x00000061
315					       0x00020006 0x0000006d
316
317					       0x00030000 0x00000021
318					       0x00030001 0x0000002a
319					       0x00030002 0x0000003c
320					       0x00030003 0x0000004e>;
321			little-endian;
322			#thermal-sensor-cells = <1>;
323		};
324
325		serial0: serial@21c0500 {
326			compatible = "fsl,ns16550", "ns16550a";
327			reg = <0x0 0x21c0500 0x0 0x100>;
328			clocks = <&clockgen 4 3>;
329			interrupts = <0 32 0x4>; /* Level high type */
330		};
331
332		serial1: serial@21c0600 {
333			compatible = "fsl,ns16550", "ns16550a";
334			reg = <0x0 0x21c0600 0x0 0x100>;
335			clocks = <&clockgen 4 3>;
336			interrupts = <0 32 0x4>; /* Level high type */
337		};
338
339		serial2: serial@21d0500 {
340			compatible = "fsl,ns16550", "ns16550a";
341			reg = <0x0 0x21d0500 0x0 0x100>;
342			clocks = <&clockgen 4 3>;
343			interrupts = <0 33 0x4>; /* Level high type */
344		};
345
346		serial3: serial@21d0600 {
347			compatible = "fsl,ns16550", "ns16550a";
348			reg = <0x0 0x21d0600 0x0 0x100>;
349			clocks = <&clockgen 4 3>;
350			interrupts = <0 33 0x4>; /* Level high type */
351		};
352
353		cluster1_core0_watchdog: wdt@c000000 {
354			compatible = "arm,sp805-wdt", "arm,primecell";
355			reg = <0x0 0xc000000 0x0 0x1000>;
356			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
357			clock-names = "wdog_clk", "apb_pclk";
358		};
359
360		cluster1_core1_watchdog: wdt@c010000 {
361			compatible = "arm,sp805-wdt", "arm,primecell";
362			reg = <0x0 0xc010000 0x0 0x1000>;
363			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
364			clock-names = "wdog_clk", "apb_pclk";
365		};
366
367		cluster2_core0_watchdog: wdt@c100000 {
368			compatible = "arm,sp805-wdt", "arm,primecell";
369			reg = <0x0 0xc100000 0x0 0x1000>;
370			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
371			clock-names = "wdog_clk", "apb_pclk";
372		};
373
374		cluster2_core1_watchdog: wdt@c110000 {
375			compatible = "arm,sp805-wdt", "arm,primecell";
376			reg = <0x0 0xc110000 0x0 0x1000>;
377			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
378			clock-names = "wdog_clk", "apb_pclk";
379		};
380
381		cluster3_core0_watchdog: wdt@c200000 {
382			compatible = "arm,sp805-wdt", "arm,primecell";
383			reg = <0x0 0xc200000 0x0 0x1000>;
384			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
385			clock-names = "wdog_clk", "apb_pclk";
386		};
387
388		cluster3_core1_watchdog: wdt@c210000 {
389			compatible = "arm,sp805-wdt", "arm,primecell";
390			reg = <0x0 0xc210000 0x0 0x1000>;
391			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
392			clock-names = "wdog_clk", "apb_pclk";
393		};
394
395		cluster4_core0_watchdog: wdt@c300000 {
396			compatible = "arm,sp805-wdt", "arm,primecell";
397			reg = <0x0 0xc300000 0x0 0x1000>;
398			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
399			clock-names = "wdog_clk", "apb_pclk";
400		};
401
402		cluster4_core1_watchdog: wdt@c310000 {
403			compatible = "arm,sp805-wdt", "arm,primecell";
404			reg = <0x0 0xc310000 0x0 0x1000>;
405			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
406			clock-names = "wdog_clk", "apb_pclk";
407		};
408
409		crypto: crypto@8000000 {
410			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
411			fsl,sec-era = <8>;
412			#address-cells = <1>;
413			#size-cells = <1>;
414			ranges = <0x0 0x00 0x8000000 0x100000>;
415			reg = <0x00 0x8000000 0x0 0x100000>;
416			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
417			dma-coherent;
418
419			sec_jr0: jr@10000 {
420				compatible = "fsl,sec-v5.0-job-ring",
421					     "fsl,sec-v4.0-job-ring";
422				reg	   = <0x10000 0x10000>;
423				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
424			};
425
426			sec_jr1: jr@20000 {
427				compatible = "fsl,sec-v5.0-job-ring",
428					     "fsl,sec-v4.0-job-ring";
429				reg	   = <0x20000 0x10000>;
430				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
431			};
432
433			sec_jr2: jr@30000 {
434				compatible = "fsl,sec-v5.0-job-ring",
435					     "fsl,sec-v4.0-job-ring";
436				reg	   = <0x30000 0x10000>;
437				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
438			};
439
440			sec_jr3: jr@40000 {
441				compatible = "fsl,sec-v5.0-job-ring",
442					     "fsl,sec-v4.0-job-ring";
443				reg	   = <0x40000 0x10000>;
444				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
445			};
446		};
447
448		console@8340020 {
449			compatible = "fsl,dpaa2-console";
450			reg = <0x00000000 0x08340020 0 0x2>;
451		};
452
453		ptp-timer@8b95000 {
454			compatible = "fsl,dpaa2-ptp";
455			reg = <0x0 0x8b95000 0x0 0x100>;
456			clocks = <&clockgen 4 1>;
457			little-endian;
458			fsl,extts-fifo;
459		};
460
461		emdio1: mdio@8b96000 {
462			compatible = "fsl,fman-memac-mdio";
463			reg = <0x0 0x8b96000 0x0 0x1000>;
464			little-endian;
465			#address-cells = <1>;
466			#size-cells = <0>;
467			status = "disabled";
468		};
469
470		emdio2: mdio@8b97000 {
471			compatible = "fsl,fman-memac-mdio";
472			reg = <0x0 0x8b97000 0x0 0x1000>;
473			little-endian;
474			#address-cells = <1>;
475			#size-cells = <0>;
476			status = "disabled";
477		};
478
479		fsl_mc: fsl-mc@80c000000 {
480			compatible = "fsl,qoriq-mc";
481			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
482			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
483			msi-parent = <&its>;
484			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
485			dma-coherent;
486			#address-cells = <3>;
487			#size-cells = <1>;
488
489			/*
490			 * Region type 0x0 - MC portals
491			 * Region type 0x1 - QBMAN portals
492			 */
493			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
494				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
495
496			/*
497			 * Define the maximum number of MACs present on the SoC.
498			 */
499			dpmacs {
500				#address-cells = <1>;
501				#size-cells = <0>;
502
503				dpmac1: dpmac@1 {
504					compatible = "fsl,qoriq-mc-dpmac";
505					reg = <0x1>;
506				};
507
508				dpmac2: dpmac@2 {
509					compatible = "fsl,qoriq-mc-dpmac";
510					reg = <0x2>;
511				};
512
513				dpmac3: dpmac@3 {
514					compatible = "fsl,qoriq-mc-dpmac";
515					reg = <0x3>;
516				};
517
518				dpmac4: dpmac@4 {
519					compatible = "fsl,qoriq-mc-dpmac";
520					reg = <0x4>;
521				};
522
523				dpmac5: dpmac@5 {
524					compatible = "fsl,qoriq-mc-dpmac";
525					reg = <0x5>;
526				};
527
528				dpmac6: dpmac@6 {
529					compatible = "fsl,qoriq-mc-dpmac";
530					reg = <0x6>;
531				};
532
533				dpmac7: dpmac@7 {
534					compatible = "fsl,qoriq-mc-dpmac";
535					reg = <0x7>;
536				};
537
538				dpmac8: dpmac@8 {
539					compatible = "fsl,qoriq-mc-dpmac";
540					reg = <0x8>;
541				};
542
543				dpmac9: dpmac@9 {
544					compatible = "fsl,qoriq-mc-dpmac";
545					reg = <0x9>;
546				};
547
548				dpmac10: dpmac@a {
549					compatible = "fsl,qoriq-mc-dpmac";
550					reg = <0xa>;
551				};
552
553				dpmac11: dpmac@b {
554					compatible = "fsl,qoriq-mc-dpmac";
555					reg = <0xb>;
556				};
557
558				dpmac12: dpmac@c {
559					compatible = "fsl,qoriq-mc-dpmac";
560					reg = <0xc>;
561				};
562
563				dpmac13: dpmac@d {
564					compatible = "fsl,qoriq-mc-dpmac";
565					reg = <0xd>;
566				};
567
568				dpmac14: dpmac@e {
569					compatible = "fsl,qoriq-mc-dpmac";
570					reg = <0xe>;
571				};
572
573				dpmac15: dpmac@f {
574					compatible = "fsl,qoriq-mc-dpmac";
575					reg = <0xf>;
576				};
577
578				dpmac16: dpmac@10 {
579					compatible = "fsl,qoriq-mc-dpmac";
580					reg = <0x10>;
581				};
582			};
583		};
584
585		smmu: iommu@5000000 {
586			compatible = "arm,mmu-500";
587			reg = <0 0x5000000 0 0x800000>;
588			#global-interrupts = <12>;
589			#iommu-cells = <1>;
590			stream-match-mask = <0x7C00>;
591			dma-coherent;
592			interrupts = <0 13 4>, /* global secure fault */
593				     <0 14 4>, /* combined secure interrupt */
594				     <0 15 4>, /* global non-secure fault */
595				     <0 16 4>, /* combined non-secure interrupt */
596				/* performance counter interrupts 0-7 */
597				     <0 211 4>, <0 212 4>,
598				     <0 213 4>, <0 214 4>,
599				     <0 215 4>, <0 216 4>,
600				     <0 217 4>, <0 218 4>,
601				/* per context interrupt, 64 interrupts */
602				     <0 146 4>, <0 147 4>,
603				     <0 148 4>, <0 149 4>,
604				     <0 150 4>, <0 151 4>,
605				     <0 152 4>, <0 153 4>,
606				     <0 154 4>, <0 155 4>,
607				     <0 156 4>, <0 157 4>,
608				     <0 158 4>, <0 159 4>,
609				     <0 160 4>, <0 161 4>,
610				     <0 162 4>, <0 163 4>,
611				     <0 164 4>, <0 165 4>,
612				     <0 166 4>, <0 167 4>,
613				     <0 168 4>, <0 169 4>,
614				     <0 170 4>, <0 171 4>,
615				     <0 172 4>, <0 173 4>,
616				     <0 174 4>, <0 175 4>,
617				     <0 176 4>, <0 177 4>,
618				     <0 178 4>, <0 179 4>,
619				     <0 180 4>, <0 181 4>,
620				     <0 182 4>, <0 183 4>,
621				     <0 184 4>, <0 185 4>,
622				     <0 186 4>, <0 187 4>,
623				     <0 188 4>, <0 189 4>,
624				     <0 190 4>, <0 191 4>,
625				     <0 192 4>, <0 193 4>,
626				     <0 194 4>, <0 195 4>,
627				     <0 196 4>, <0 197 4>,
628				     <0 198 4>, <0 199 4>,
629				     <0 200 4>, <0 201 4>,
630				     <0 202 4>, <0 203 4>,
631				     <0 204 4>, <0 205 4>,
632				     <0 206 4>, <0 207 4>,
633				     <0 208 4>, <0 209 4>;
634		};
635
636		dspi: spi@2100000 {
637			status = "disabled";
638			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
639			#address-cells = <1>;
640			#size-cells = <0>;
641			reg = <0x0 0x2100000 0x0 0x10000>;
642			interrupts = <0 26 0x4>; /* Level high type */
643			clocks = <&clockgen 4 3>;
644			clock-names = "dspi";
645			spi-num-chipselects = <5>;
646			bus-num = <0>;
647		};
648
649		esdhc: esdhc@2140000 {
650			status = "disabled";
651			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
652			reg = <0x0 0x2140000 0x0 0x10000>;
653			interrupts = <0 28 0x4>; /* Level high type */
654			clocks = <&clockgen 4 1>;
655			voltage-ranges = <1800 1800 3300 3300>;
656			sdhci,auto-cmd12;
657			little-endian;
658			bus-width = <4>;
659		};
660
661		gpio0: gpio@2300000 {
662			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
663			reg = <0x0 0x2300000 0x0 0x10000>;
664			interrupts = <0 36 0x4>; /* Level high type */
665			gpio-controller;
666			little-endian;
667			#gpio-cells = <2>;
668			interrupt-controller;
669			#interrupt-cells = <2>;
670		};
671
672		gpio1: gpio@2310000 {
673			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
674			reg = <0x0 0x2310000 0x0 0x10000>;
675			interrupts = <0 36 0x4>; /* Level high type */
676			gpio-controller;
677			little-endian;
678			#gpio-cells = <2>;
679			interrupt-controller;
680			#interrupt-cells = <2>;
681		};
682
683		gpio2: gpio@2320000 {
684			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
685			reg = <0x0 0x2320000 0x0 0x10000>;
686			interrupts = <0 37 0x4>; /* Level high type */
687			gpio-controller;
688			little-endian;
689			#gpio-cells = <2>;
690			interrupt-controller;
691			#interrupt-cells = <2>;
692		};
693
694		gpio3: gpio@2330000 {
695			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
696			reg = <0x0 0x2330000 0x0 0x10000>;
697			interrupts = <0 37 0x4>; /* Level high type */
698			gpio-controller;
699			little-endian;
700			#gpio-cells = <2>;
701			interrupt-controller;
702			#interrupt-cells = <2>;
703		};
704
705		i2c0: i2c@2000000 {
706			status = "disabled";
707			compatible = "fsl,vf610-i2c";
708			#address-cells = <1>;
709			#size-cells = <0>;
710			reg = <0x0 0x2000000 0x0 0x10000>;
711			interrupts = <0 34 0x4>; /* Level high type */
712			clock-names = "i2c";
713			clocks = <&clockgen 4 3>;
714		};
715
716		i2c1: i2c@2010000 {
717			status = "disabled";
718			compatible = "fsl,vf610-i2c";
719			#address-cells = <1>;
720			#size-cells = <0>;
721			reg = <0x0 0x2010000 0x0 0x10000>;
722			interrupts = <0 34 0x4>; /* Level high type */
723			clock-names = "i2c";
724			clocks = <&clockgen 4 3>;
725		};
726
727		i2c2: i2c@2020000 {
728			status = "disabled";
729			compatible = "fsl,vf610-i2c";
730			#address-cells = <1>;
731			#size-cells = <0>;
732			reg = <0x0 0x2020000 0x0 0x10000>;
733			interrupts = <0 35 0x4>; /* Level high type */
734			clock-names = "i2c";
735			clocks = <&clockgen 4 3>;
736		};
737
738		i2c3: i2c@2030000 {
739			status = "disabled";
740			compatible = "fsl,vf610-i2c";
741			#address-cells = <1>;
742			#size-cells = <0>;
743			reg = <0x0 0x2030000 0x0 0x10000>;
744			interrupts = <0 35 0x4>; /* Level high type */
745			clock-names = "i2c";
746			clocks = <&clockgen 4 3>;
747		};
748
749		ifc: ifc@2240000 {
750			compatible = "fsl,ifc", "simple-bus";
751			reg = <0x0 0x2240000 0x0 0x20000>;
752			interrupts = <0 21 0x4>; /* Level high type */
753			little-endian;
754			#address-cells = <2>;
755			#size-cells = <1>;
756
757			ranges = <0 0 0x5 0x80000000 0x08000000
758				  2 0 0x5 0x30000000 0x00010000
759				  3 0 0x5 0x20000000 0x00010000>;
760		};
761
762		qspi: spi@20c0000 {
763			compatible = "fsl,ls2080a-qspi";
764			#address-cells = <1>;
765			#size-cells = <0>;
766			reg = <0x0 0x20c0000 0x0 0x10000>,
767			      <0x0 0x20000000 0x0 0x10000000>;
768			reg-names = "QuadSPI", "QuadSPI-memory";
769			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
770			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
771			clock-names = "qspi_en", "qspi";
772			status = "disabled";
773		};
774
775		pcie1: pcie@3400000 {
776			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
777			reg-names = "regs", "config";
778			interrupts = <0 108 0x4>; /* Level high type */
779			interrupt-names = "intr";
780			#address-cells = <3>;
781			#size-cells = <2>;
782			device_type = "pci";
783			dma-coherent;
784			num-viewport = <6>;
785			bus-range = <0x0 0xff>;
786			msi-parent = <&its>;
787			#interrupt-cells = <1>;
788			interrupt-map-mask = <0 0 0 7>;
789			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
790					<0000 0 0 2 &gic 0 0 0 110 4>,
791					<0000 0 0 3 &gic 0 0 0 111 4>,
792					<0000 0 0 4 &gic 0 0 0 112 4>;
793			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
794			status = "disabled";
795		};
796
797		pcie2: pcie@3500000 {
798			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
799			reg-names = "regs", "config";
800			interrupts = <0 113 0x4>; /* Level high type */
801			interrupt-names = "intr";
802			#address-cells = <3>;
803			#size-cells = <2>;
804			device_type = "pci";
805			dma-coherent;
806			num-viewport = <6>;
807			bus-range = <0x0 0xff>;
808			msi-parent = <&its>;
809			#interrupt-cells = <1>;
810			interrupt-map-mask = <0 0 0 7>;
811			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
812					<0000 0 0 2 &gic 0 0 0 115 4>,
813					<0000 0 0 3 &gic 0 0 0 116 4>,
814					<0000 0 0 4 &gic 0 0 0 117 4>;
815			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
816			status = "disabled";
817		};
818
819		pcie3: pcie@3600000 {
820			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
821			reg-names = "regs", "config";
822			interrupts = <0 118 0x4>; /* Level high type */
823			interrupt-names = "intr";
824			#address-cells = <3>;
825			#size-cells = <2>;
826			device_type = "pci";
827			dma-coherent;
828			num-viewport = <256>;
829			bus-range = <0x0 0xff>;
830			msi-parent = <&its>;
831			#interrupt-cells = <1>;
832			interrupt-map-mask = <0 0 0 7>;
833			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
834					<0000 0 0 2 &gic 0 0 0 120 4>,
835					<0000 0 0 3 &gic 0 0 0 121 4>,
836					<0000 0 0 4 &gic 0 0 0 122 4>;
837			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
838			status = "disabled";
839		};
840
841		pcie4: pcie@3700000 {
842			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
843			reg-names = "regs", "config";
844			interrupts = <0 123 0x4>; /* Level high type */
845			interrupt-names = "intr";
846			#address-cells = <3>;
847			#size-cells = <2>;
848			device_type = "pci";
849			dma-coherent;
850			num-viewport = <6>;
851			bus-range = <0x0 0xff>;
852			msi-parent = <&its>;
853			#interrupt-cells = <1>;
854			interrupt-map-mask = <0 0 0 7>;
855			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
856					<0000 0 0 2 &gic 0 0 0 125 4>,
857					<0000 0 0 3 &gic 0 0 0 126 4>,
858					<0000 0 0 4 &gic 0 0 0 127 4>;
859			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
860			status = "disabled";
861		};
862
863		sata0: sata@3200000 {
864			status = "disabled";
865			compatible = "fsl,ls2080a-ahci";
866			reg = <0x0 0x3200000 0x0 0x10000>;
867			interrupts = <0 133 0x4>; /* Level high type */
868			clocks = <&clockgen 4 3>;
869			dma-coherent;
870		};
871
872		sata1: sata@3210000 {
873			status = "disabled";
874			compatible = "fsl,ls2080a-ahci";
875			reg = <0x0 0x3210000 0x0 0x10000>;
876			interrupts = <0 136 0x4>; /* Level high type */
877			clocks = <&clockgen 4 3>;
878			dma-coherent;
879		};
880
881		usb0: usb@3100000 {
882			status = "disabled";
883			compatible = "snps,dwc3";
884			reg = <0x0 0x3100000 0x0 0x10000>;
885			interrupts = <0 80 0x4>; /* Level high type */
886			dr_mode = "host";
887			snps,quirk-frame-length-adjustment = <0x20>;
888			snps,dis_rxdet_inp3_quirk;
889			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
890		};
891
892		usb1: usb@3110000 {
893			status = "disabled";
894			compatible = "snps,dwc3";
895			reg = <0x0 0x3110000 0x0 0x10000>;
896			interrupts = <0 81 0x4>; /* Level high type */
897			dr_mode = "host";
898			snps,quirk-frame-length-adjustment = <0x20>;
899			snps,dis_rxdet_inp3_quirk;
900			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
901		};
902
903		ccn@4000000 {
904			compatible = "arm,ccn-504";
905			reg = <0x0 0x04000000 0x0 0x01000000>;
906			interrupts = <0 12 4>;
907		};
908
909		rcpm: power-controller@1e34040 {
910			compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
911			reg = <0x0 0x1e34040 0x0 0x18>;
912			#fsl,rcpm-wakeup-cells = <6>;
913		};
914
915		ftm_alarm0: timer@2800000 {
916			compatible = "fsl,ls208xa-ftm-alarm";
917			reg = <0x0 0x2800000 0x0 0x10000>;
918			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
919			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
920		};
921	};
922
923	ddr1: memory-controller@1080000 {
924		compatible = "fsl,qoriq-memory-controller";
925		reg = <0x0 0x1080000 0x0 0x1000>;
926		interrupts = <0 17 0x4>;
927		little-endian;
928	};
929
930	ddr2: memory-controller@1090000 {
931		compatible = "fsl,qoriq-memory-controller";
932		reg = <0x0 0x1090000 0x0 0x1000>;
933		interrupts = <0 18 0x4>;
934		little-endian;
935	};
936
937	firmware {
938		optee {
939			compatible = "linaro,optee-tz";
940			method = "smc";
941		};
942	};
943};
944