1df72c23eSAbhimanyu Saini/* 2df72c23eSAbhimanyu Saini * Device Tree Include file for Freescale Layerscape-2088A family SoC. 3df72c23eSAbhimanyu Saini * 4df72c23eSAbhimanyu Saini * Copyright (C) 2016-17, Freescale Semiconductor 5df72c23eSAbhimanyu Saini * 6df72c23eSAbhimanyu Saini * Abhimanyu Saini <abhimanyu.saini@nxp.com> 7df72c23eSAbhimanyu Saini * 8df72c23eSAbhimanyu Saini * This file is dual-licensed: you can use it either under the terms 9df72c23eSAbhimanyu Saini * of the GPLv2 or the X11 license, at your option. Note that this dual 10df72c23eSAbhimanyu Saini * licensing only applies to this file, and not this project as a 11df72c23eSAbhimanyu Saini * whole. 12df72c23eSAbhimanyu Saini * 13df72c23eSAbhimanyu Saini * a) This library is free software; you can redistribute it and/or 14df72c23eSAbhimanyu Saini * modify it under the terms of the GNU General Public License as 15df72c23eSAbhimanyu Saini * published by the Free Software Foundation; either version 2 of the 16df72c23eSAbhimanyu Saini * License, or (at your option) any later version. 17df72c23eSAbhimanyu Saini * 18df72c23eSAbhimanyu Saini * This library is distributed in the hope that it will be useful, 19df72c23eSAbhimanyu Saini * but WITHOUT ANY WARRANTY; without even the implied warranty of 20df72c23eSAbhimanyu Saini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21df72c23eSAbhimanyu Saini * GNU General Public License for more details. 22df72c23eSAbhimanyu Saini * 23df72c23eSAbhimanyu Saini * Or, alternatively, 24df72c23eSAbhimanyu Saini * 25df72c23eSAbhimanyu Saini * b) Permission is hereby granted, free of charge, to any person 26df72c23eSAbhimanyu Saini * obtaining a copy of this software and associated documentation 27df72c23eSAbhimanyu Saini * files (the "Software"), to deal in the Software without 28df72c23eSAbhimanyu Saini * restriction, including without limitation the rights to use, 29df72c23eSAbhimanyu Saini * copy, modify, merge, publish, distribute, sublicense, and/or 30df72c23eSAbhimanyu Saini * sell copies of the Software, and to permit persons to whom the 31df72c23eSAbhimanyu Saini * Software is furnished to do so, subject to the following 32df72c23eSAbhimanyu Saini * conditions: 33df72c23eSAbhimanyu Saini * 34df72c23eSAbhimanyu Saini * The above copyright notice and this permission notice shall be 35df72c23eSAbhimanyu Saini * included in all copies or substantial portions of the Software. 36df72c23eSAbhimanyu Saini * 37df72c23eSAbhimanyu Saini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38df72c23eSAbhimanyu Saini * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39df72c23eSAbhimanyu Saini * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40df72c23eSAbhimanyu Saini * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41df72c23eSAbhimanyu Saini * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42df72c23eSAbhimanyu Saini * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43df72c23eSAbhimanyu Saini * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44df72c23eSAbhimanyu Saini * OTHER DEALINGS IN THE SOFTWARE. 45df72c23eSAbhimanyu Saini */ 46df72c23eSAbhimanyu Saini 47df72c23eSAbhimanyu Saini#include "fsl-ls208xa.dtsi" 48df72c23eSAbhimanyu Saini 49df72c23eSAbhimanyu Saini&cpu { 50df72c23eSAbhimanyu Saini cpu0: cpu@0 { 51df72c23eSAbhimanyu Saini device_type = "cpu"; 52df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 53df72c23eSAbhimanyu Saini reg = <0x0>; 54df72c23eSAbhimanyu Saini clocks = <&clockgen 1 0>; 55df72c23eSAbhimanyu Saini next-level-cache = <&cluster0_l2>; 56df72c23eSAbhimanyu Saini #cooling-cells = <2>; 57df72c23eSAbhimanyu Saini }; 58df72c23eSAbhimanyu Saini 59df72c23eSAbhimanyu Saini cpu1: cpu@1 { 60df72c23eSAbhimanyu Saini device_type = "cpu"; 61df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 62df72c23eSAbhimanyu Saini reg = <0x1>; 63df72c23eSAbhimanyu Saini clocks = <&clockgen 1 0>; 64df72c23eSAbhimanyu Saini next-level-cache = <&cluster0_l2>; 65df72c23eSAbhimanyu Saini }; 66df72c23eSAbhimanyu Saini 67df72c23eSAbhimanyu Saini cpu2: cpu@100 { 68df72c23eSAbhimanyu Saini device_type = "cpu"; 69df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 70df72c23eSAbhimanyu Saini reg = <0x100>; 71df72c23eSAbhimanyu Saini clocks = <&clockgen 1 1>; 72df72c23eSAbhimanyu Saini next-level-cache = <&cluster1_l2>; 73df72c23eSAbhimanyu Saini #cooling-cells = <2>; 74df72c23eSAbhimanyu Saini }; 75df72c23eSAbhimanyu Saini 76df72c23eSAbhimanyu Saini cpu3: cpu@101 { 77df72c23eSAbhimanyu Saini device_type = "cpu"; 78df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 79df72c23eSAbhimanyu Saini reg = <0x101>; 80df72c23eSAbhimanyu Saini clocks = <&clockgen 1 1>; 81df72c23eSAbhimanyu Saini next-level-cache = <&cluster1_l2>; 82df72c23eSAbhimanyu Saini }; 83df72c23eSAbhimanyu Saini 84df72c23eSAbhimanyu Saini cpu4: cpu@200 { 85df72c23eSAbhimanyu Saini device_type = "cpu"; 86df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 87df72c23eSAbhimanyu Saini reg = <0x200>; 88df72c23eSAbhimanyu Saini clocks = <&clockgen 1 2>; 89df72c23eSAbhimanyu Saini next-level-cache = <&cluster2_l2>; 90df72c23eSAbhimanyu Saini #cooling-cells = <2>; 91df72c23eSAbhimanyu Saini }; 92df72c23eSAbhimanyu Saini 93df72c23eSAbhimanyu Saini cpu5: cpu@201 { 94df72c23eSAbhimanyu Saini device_type = "cpu"; 95df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 96df72c23eSAbhimanyu Saini reg = <0x201>; 97df72c23eSAbhimanyu Saini clocks = <&clockgen 1 2>; 98df72c23eSAbhimanyu Saini next-level-cache = <&cluster2_l2>; 99df72c23eSAbhimanyu Saini }; 100df72c23eSAbhimanyu Saini 101df72c23eSAbhimanyu Saini cpu6: cpu@300 { 102df72c23eSAbhimanyu Saini device_type = "cpu"; 103df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 104df72c23eSAbhimanyu Saini reg = <0x300>; 105df72c23eSAbhimanyu Saini clocks = <&clockgen 1 3>; 106df72c23eSAbhimanyu Saini next-level-cache = <&cluster3_l2>; 107df72c23eSAbhimanyu Saini #cooling-cells = <2>; 108df72c23eSAbhimanyu Saini }; 109df72c23eSAbhimanyu Saini 110df72c23eSAbhimanyu Saini cpu7: cpu@301 { 111df72c23eSAbhimanyu Saini device_type = "cpu"; 112df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 113df72c23eSAbhimanyu Saini reg = <0x301>; 114df72c23eSAbhimanyu Saini clocks = <&clockgen 1 3>; 115df72c23eSAbhimanyu Saini next-level-cache = <&cluster3_l2>; 116df72c23eSAbhimanyu Saini }; 117df72c23eSAbhimanyu Saini 118df72c23eSAbhimanyu Saini cluster0_l2: l2-cache0 { 119df72c23eSAbhimanyu Saini compatible = "cache"; 120df72c23eSAbhimanyu Saini }; 121df72c23eSAbhimanyu Saini 122df72c23eSAbhimanyu Saini cluster1_l2: l2-cache1 { 123df72c23eSAbhimanyu Saini compatible = "cache"; 124df72c23eSAbhimanyu Saini }; 125df72c23eSAbhimanyu Saini 126df72c23eSAbhimanyu Saini cluster2_l2: l2-cache2 { 127df72c23eSAbhimanyu Saini compatible = "cache"; 128df72c23eSAbhimanyu Saini }; 129df72c23eSAbhimanyu Saini 130df72c23eSAbhimanyu Saini cluster3_l2: l2-cache3 { 131df72c23eSAbhimanyu Saini compatible = "cache"; 132df72c23eSAbhimanyu Saini }; 133df72c23eSAbhimanyu Saini}; 134df72c23eSAbhimanyu Saini 135df72c23eSAbhimanyu Saini&pcie1 { 136df72c23eSAbhimanyu Saini reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 137df72c23eSAbhimanyu Saini 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 138df72c23eSAbhimanyu Saini 139df72c23eSAbhimanyu Saini ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 140df72c23eSAbhimanyu Saini 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; 141df72c23eSAbhimanyu Saini}; 142df72c23eSAbhimanyu Saini 143df72c23eSAbhimanyu Saini&pcie2 { 144df72c23eSAbhimanyu Saini reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 145df72c23eSAbhimanyu Saini 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 146df72c23eSAbhimanyu Saini 147df72c23eSAbhimanyu Saini ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 148df72c23eSAbhimanyu Saini 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; 149df72c23eSAbhimanyu Saini}; 150df72c23eSAbhimanyu Saini 151df72c23eSAbhimanyu Saini&pcie3 { 152df72c23eSAbhimanyu Saini reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 153df72c23eSAbhimanyu Saini 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 154df72c23eSAbhimanyu Saini 155df72c23eSAbhimanyu Saini ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 156df72c23eSAbhimanyu Saini 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; 157df72c23eSAbhimanyu Saini}; 158df72c23eSAbhimanyu Saini 159df72c23eSAbhimanyu Saini&pcie4 { 160df72c23eSAbhimanyu Saini reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 161df72c23eSAbhimanyu Saini 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ 162df72c23eSAbhimanyu Saini 163df72c23eSAbhimanyu Saini ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 164df72c23eSAbhimanyu Saini 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; 165df72c23eSAbhimanyu Saini}; 166