17a2aeb91SLi Yang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2df72c23eSAbhimanyu Saini/* 3df72c23eSAbhimanyu Saini * Device Tree Include file for Freescale Layerscape-2088A family SoC. 4df72c23eSAbhimanyu Saini * 58637f58bSLi Yang * Copyright 2016 Freescale Semiconductor, Inc. 68637f58bSLi Yang * Copyright 2017 NXP 7df72c23eSAbhimanyu Saini * 8df72c23eSAbhimanyu Saini * Abhimanyu Saini <abhimanyu.saini@nxp.com> 9df72c23eSAbhimanyu Saini * 10df72c23eSAbhimanyu Saini */ 11df72c23eSAbhimanyu Saini 12df72c23eSAbhimanyu Saini#include "fsl-ls208xa.dtsi" 13df72c23eSAbhimanyu Saini 14df72c23eSAbhimanyu Saini&cpu { 15df72c23eSAbhimanyu Saini cpu0: cpu@0 { 16df72c23eSAbhimanyu Saini device_type = "cpu"; 17df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 18df72c23eSAbhimanyu Saini reg = <0x0>; 19df72c23eSAbhimanyu Saini clocks = <&clockgen 1 0>; 2039a71db1SYuantian Tang cpu-idle-states = <&CPU_PW20>; 21df72c23eSAbhimanyu Saini next-level-cache = <&cluster0_l2>; 22df72c23eSAbhimanyu Saini #cooling-cells = <2>; 23df72c23eSAbhimanyu Saini }; 24df72c23eSAbhimanyu Saini 25df72c23eSAbhimanyu Saini cpu1: cpu@1 { 26df72c23eSAbhimanyu Saini device_type = "cpu"; 27df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 28df72c23eSAbhimanyu Saini reg = <0x1>; 29df72c23eSAbhimanyu Saini clocks = <&clockgen 1 0>; 3039a71db1SYuantian Tang cpu-idle-states = <&CPU_PW20>; 31df72c23eSAbhimanyu Saini next-level-cache = <&cluster0_l2>; 32df72c23eSAbhimanyu Saini }; 33df72c23eSAbhimanyu Saini 34df72c23eSAbhimanyu Saini cpu2: cpu@100 { 35df72c23eSAbhimanyu Saini device_type = "cpu"; 36df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 37df72c23eSAbhimanyu Saini reg = <0x100>; 38df72c23eSAbhimanyu Saini clocks = <&clockgen 1 1>; 3939a71db1SYuantian Tang cpu-idle-states = <&CPU_PW20>; 40df72c23eSAbhimanyu Saini next-level-cache = <&cluster1_l2>; 41df72c23eSAbhimanyu Saini #cooling-cells = <2>; 42df72c23eSAbhimanyu Saini }; 43df72c23eSAbhimanyu Saini 44df72c23eSAbhimanyu Saini cpu3: cpu@101 { 45df72c23eSAbhimanyu Saini device_type = "cpu"; 46df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 47df72c23eSAbhimanyu Saini reg = <0x101>; 48df72c23eSAbhimanyu Saini clocks = <&clockgen 1 1>; 4939a71db1SYuantian Tang cpu-idle-states = <&CPU_PW20>; 50df72c23eSAbhimanyu Saini next-level-cache = <&cluster1_l2>; 51df72c23eSAbhimanyu Saini }; 52df72c23eSAbhimanyu Saini 53df72c23eSAbhimanyu Saini cpu4: cpu@200 { 54df72c23eSAbhimanyu Saini device_type = "cpu"; 55df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 56df72c23eSAbhimanyu Saini reg = <0x200>; 57df72c23eSAbhimanyu Saini clocks = <&clockgen 1 2>; 58df72c23eSAbhimanyu Saini next-level-cache = <&cluster2_l2>; 5939a71db1SYuantian Tang cpu-idle-states = <&CPU_PW20>; 60df72c23eSAbhimanyu Saini #cooling-cells = <2>; 61df72c23eSAbhimanyu Saini }; 62df72c23eSAbhimanyu Saini 63df72c23eSAbhimanyu Saini cpu5: cpu@201 { 64df72c23eSAbhimanyu Saini device_type = "cpu"; 65df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 66df72c23eSAbhimanyu Saini reg = <0x201>; 67df72c23eSAbhimanyu Saini clocks = <&clockgen 1 2>; 6839a71db1SYuantian Tang cpu-idle-states = <&CPU_PW20>; 69df72c23eSAbhimanyu Saini next-level-cache = <&cluster2_l2>; 70df72c23eSAbhimanyu Saini }; 71df72c23eSAbhimanyu Saini 72df72c23eSAbhimanyu Saini cpu6: cpu@300 { 73df72c23eSAbhimanyu Saini device_type = "cpu"; 74df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 75df72c23eSAbhimanyu Saini reg = <0x300>; 76df72c23eSAbhimanyu Saini clocks = <&clockgen 1 3>; 7739a71db1SYuantian Tang cpu-idle-states = <&CPU_PW20>; 78df72c23eSAbhimanyu Saini next-level-cache = <&cluster3_l2>; 79df72c23eSAbhimanyu Saini #cooling-cells = <2>; 80df72c23eSAbhimanyu Saini }; 81df72c23eSAbhimanyu Saini 82df72c23eSAbhimanyu Saini cpu7: cpu@301 { 83df72c23eSAbhimanyu Saini device_type = "cpu"; 84df72c23eSAbhimanyu Saini compatible = "arm,cortex-a72"; 85df72c23eSAbhimanyu Saini reg = <0x301>; 86df72c23eSAbhimanyu Saini clocks = <&clockgen 1 3>; 8739a71db1SYuantian Tang cpu-idle-states = <&CPU_PW20>; 88df72c23eSAbhimanyu Saini next-level-cache = <&cluster3_l2>; 89df72c23eSAbhimanyu Saini }; 90df72c23eSAbhimanyu Saini 91df72c23eSAbhimanyu Saini cluster0_l2: l2-cache0 { 92df72c23eSAbhimanyu Saini compatible = "cache"; 93df72c23eSAbhimanyu Saini }; 94df72c23eSAbhimanyu Saini 95df72c23eSAbhimanyu Saini cluster1_l2: l2-cache1 { 96df72c23eSAbhimanyu Saini compatible = "cache"; 97df72c23eSAbhimanyu Saini }; 98df72c23eSAbhimanyu Saini 99df72c23eSAbhimanyu Saini cluster2_l2: l2-cache2 { 100df72c23eSAbhimanyu Saini compatible = "cache"; 101df72c23eSAbhimanyu Saini }; 102df72c23eSAbhimanyu Saini 103df72c23eSAbhimanyu Saini cluster3_l2: l2-cache3 { 104df72c23eSAbhimanyu Saini compatible = "cache"; 105df72c23eSAbhimanyu Saini }; 10639a71db1SYuantian Tang 10739a71db1SYuantian Tang CPU_PW20: cpu-pw20 { 10839a71db1SYuantian Tang compatible = "arm,idle-state"; 10939a71db1SYuantian Tang idle-state-name = "PW20"; 11069ea29b0SYuantian Tang arm,psci-suspend-param = <0x0>; 11139a71db1SYuantian Tang entry-latency-us = <2000>; 11239a71db1SYuantian Tang exit-latency-us = <2000>; 11339a71db1SYuantian Tang min-residency-us = <6000>; 11439a71db1SYuantian Tang }; 115df72c23eSAbhimanyu Saini}; 116df72c23eSAbhimanyu Saini 117df72c23eSAbhimanyu Saini&pcie1 { 118bef52aacSHou Zhiqiang compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; 119df72c23eSAbhimanyu Saini reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 120df72c23eSAbhimanyu Saini 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 121df72c23eSAbhimanyu Saini 122df72c23eSAbhimanyu Saini ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 123df72c23eSAbhimanyu Saini 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; 124df72c23eSAbhimanyu Saini}; 125df72c23eSAbhimanyu Saini 126df72c23eSAbhimanyu Saini&pcie2 { 127bef52aacSHou Zhiqiang compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; 128df72c23eSAbhimanyu Saini reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 129df72c23eSAbhimanyu Saini 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 130df72c23eSAbhimanyu Saini 131df72c23eSAbhimanyu Saini ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 132df72c23eSAbhimanyu Saini 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; 133df72c23eSAbhimanyu Saini}; 134df72c23eSAbhimanyu Saini 135df72c23eSAbhimanyu Saini&pcie3 { 136bef52aacSHou Zhiqiang compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; 137df72c23eSAbhimanyu Saini reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 138df72c23eSAbhimanyu Saini 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 139df72c23eSAbhimanyu Saini 140df72c23eSAbhimanyu Saini ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 141df72c23eSAbhimanyu Saini 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; 142df72c23eSAbhimanyu Saini}; 143df72c23eSAbhimanyu Saini 144df72c23eSAbhimanyu Saini&pcie4 { 145bef52aacSHou Zhiqiang compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; 146df72c23eSAbhimanyu Saini reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 147df72c23eSAbhimanyu Saini 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ 148df72c23eSAbhimanyu Saini 149df72c23eSAbhimanyu Saini ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 150df72c23eSAbhimanyu Saini 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; 151df72c23eSAbhimanyu Saini}; 152