1/* 2 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 3 * 4 * Copyright (C) 2014-2015, Freescale Semiconductor 5 * 6 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPLv2 or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This library is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This library is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47/ { 48 compatible = "fsl,ls2080a"; 49 interrupt-parent = <&gic>; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 /* 58 * We expect the enable-method for cpu's to be "psci", but this 59 * is dependent on the SoC FW, which will fill this in. 60 * 61 * Currently supported enable-method is psci v0.2 62 */ 63 64 /* We have 4 clusters having 2 Cortex-A57 cores each */ 65 cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a57"; 68 reg = <0x0>; 69 clocks = <&clockgen 1 0>; 70 next-level-cache = <&cluster0_l2>; 71 }; 72 73 cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a57"; 76 reg = <0x1>; 77 clocks = <&clockgen 1 0>; 78 next-level-cache = <&cluster0_l2>; 79 }; 80 81 cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a57"; 84 reg = <0x100>; 85 clocks = <&clockgen 1 1>; 86 next-level-cache = <&cluster1_l2>; 87 }; 88 89 cpu@101 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a57"; 92 reg = <0x101>; 93 clocks = <&clockgen 1 1>; 94 next-level-cache = <&cluster1_l2>; 95 }; 96 97 cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a57"; 100 reg = <0x200>; 101 clocks = <&clockgen 1 2>; 102 next-level-cache = <&cluster2_l2>; 103 }; 104 105 cpu@201 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a57"; 108 reg = <0x201>; 109 clocks = <&clockgen 1 2>; 110 next-level-cache = <&cluster2_l2>; 111 }; 112 113 cpu@300 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a57"; 116 reg = <0x300>; 117 clocks = <&clockgen 1 3>; 118 next-level-cache = <&cluster3_l2>; 119 }; 120 121 cpu@301 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a57"; 124 reg = <0x301>; 125 clocks = <&clockgen 1 3>; 126 next-level-cache = <&cluster3_l2>; 127 }; 128 129 cluster0_l2: l2-cache0 { 130 compatible = "cache"; 131 }; 132 133 cluster1_l2: l2-cache1 { 134 compatible = "cache"; 135 }; 136 137 cluster2_l2: l2-cache2 { 138 compatible = "cache"; 139 }; 140 141 cluster3_l2: l2-cache3 { 142 compatible = "cache"; 143 }; 144 }; 145 146 memory@80000000 { 147 device_type = "memory"; 148 reg = <0x00000000 0x80000000 0 0x80000000>; 149 /* DRAM space - 1, size : 2 GB DRAM */ 150 }; 151 152 sysclk: sysclk { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-frequency = <100000000>; 156 clock-output-names = "sysclk"; 157 }; 158 159 gic: interrupt-controller@6000000 { 160 compatible = "arm,gic-v3"; 161 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 162 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 163 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 164 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 165 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 166 #interrupt-cells = <3>; 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges; 170 interrupt-controller; 171 interrupts = <1 9 0x4>; 172 173 its: gic-its@6020000 { 174 compatible = "arm,gic-v3-its"; 175 msi-controller; 176 reg = <0x0 0x6020000 0 0x20000>; 177 }; 178 }; 179 180 rstcr: syscon@1e60000 { 181 compatible = "fsl,ls2080a-rstcr", "syscon"; 182 reg = <0x0 0x1e60000 0x0 0x4>; 183 }; 184 185 reboot { 186 compatible ="syscon-reboot"; 187 regmap = <&rstcr>; 188 offset = <0x0>; 189 mask = <0x2>; 190 }; 191 192 timer { 193 compatible = "arm,armv8-timer"; 194 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 195 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ 196 <1 11 0x8>, /* Virtual PPI, active-low */ 197 <1 10 0x8>; /* Hypervisor PPI, active-low */ 198 }; 199 200 pmu { 201 compatible = "arm,armv8-pmuv3"; 202 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 203 }; 204 205 soc { 206 compatible = "simple-bus"; 207 #address-cells = <2>; 208 #size-cells = <2>; 209 ranges; 210 211 clockgen: clocking@1300000 { 212 compatible = "fsl,ls2080a-clockgen"; 213 reg = <0 0x1300000 0 0xa0000>; 214 #clock-cells = <2>; 215 clocks = <&sysclk>; 216 }; 217 218 serial0: serial@21c0500 { 219 compatible = "fsl,ns16550", "ns16550a"; 220 reg = <0x0 0x21c0500 0x0 0x100>; 221 clocks = <&clockgen 4 3>; 222 interrupts = <0 32 0x4>; /* Level high type */ 223 }; 224 225 serial1: serial@21c0600 { 226 compatible = "fsl,ns16550", "ns16550a"; 227 reg = <0x0 0x21c0600 0x0 0x100>; 228 clocks = <&clockgen 4 3>; 229 interrupts = <0 32 0x4>; /* Level high type */ 230 }; 231 232 cluster1_core0_watchdog: wdt@c000000 { 233 compatible = "arm,sp805-wdt", "arm,primecell"; 234 reg = <0x0 0xc000000 0x0 0x1000>; 235 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 236 clock-names = "apb_pclk", "wdog_clk"; 237 }; 238 239 cluster1_core1_watchdog: wdt@c010000 { 240 compatible = "arm,sp805-wdt", "arm,primecell"; 241 reg = <0x0 0xc010000 0x0 0x1000>; 242 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 243 clock-names = "apb_pclk", "wdog_clk"; 244 }; 245 246 cluster2_core0_watchdog: wdt@c100000 { 247 compatible = "arm,sp805-wdt", "arm,primecell"; 248 reg = <0x0 0xc100000 0x0 0x1000>; 249 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 250 clock-names = "apb_pclk", "wdog_clk"; 251 }; 252 253 cluster2_core1_watchdog: wdt@c110000 { 254 compatible = "arm,sp805-wdt", "arm,primecell"; 255 reg = <0x0 0xc110000 0x0 0x1000>; 256 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 257 clock-names = "apb_pclk", "wdog_clk"; 258 }; 259 260 cluster3_core0_watchdog: wdt@c200000 { 261 compatible = "arm,sp805-wdt", "arm,primecell"; 262 reg = <0x0 0xc200000 0x0 0x1000>; 263 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 264 clock-names = "apb_pclk", "wdog_clk"; 265 }; 266 267 cluster3_core1_watchdog: wdt@c210000 { 268 compatible = "arm,sp805-wdt", "arm,primecell"; 269 reg = <0x0 0xc210000 0x0 0x1000>; 270 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 271 clock-names = "apb_pclk", "wdog_clk"; 272 }; 273 274 cluster4_core0_watchdog: wdt@c300000 { 275 compatible = "arm,sp805-wdt", "arm,primecell"; 276 reg = <0x0 0xc300000 0x0 0x1000>; 277 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 278 clock-names = "apb_pclk", "wdog_clk"; 279 }; 280 281 cluster4_core1_watchdog: wdt@c310000 { 282 compatible = "arm,sp805-wdt", "arm,primecell"; 283 reg = <0x0 0xc310000 0x0 0x1000>; 284 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 285 clock-names = "apb_pclk", "wdog_clk"; 286 }; 287 288 fsl_mc: fsl-mc@80c000000 { 289 compatible = "fsl,qoriq-mc"; 290 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 291 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 292 msi-parent = <&its>; 293 #address-cells = <3>; 294 #size-cells = <1>; 295 296 /* 297 * Region type 0x0 - MC portals 298 * Region type 0x1 - QBMAN portals 299 */ 300 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 301 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 302 303 /* 304 * Define the maximum number of MACs present on the SoC. 305 */ 306 dpmacs { 307 #address-cells = <1>; 308 #size-cells = <0>; 309 310 dpmac1: dpmac@1 { 311 compatible = "fsl,qoriq-mc-dpmac"; 312 reg = <0x1>; 313 }; 314 315 dpmac2: dpmac@2 { 316 compatible = "fsl,qoriq-mc-dpmac"; 317 reg = <0x2>; 318 }; 319 320 dpmac3: dpmac@3 { 321 compatible = "fsl,qoriq-mc-dpmac"; 322 reg = <0x3>; 323 }; 324 325 dpmac4: dpmac@4 { 326 compatible = "fsl,qoriq-mc-dpmac"; 327 reg = <0x4>; 328 }; 329 330 dpmac5: dpmac@5 { 331 compatible = "fsl,qoriq-mc-dpmac"; 332 reg = <0x5>; 333 }; 334 335 dpmac6: dpmac@6 { 336 compatible = "fsl,qoriq-mc-dpmac"; 337 reg = <0x6>; 338 }; 339 340 dpmac7: dpmac@7 { 341 compatible = "fsl,qoriq-mc-dpmac"; 342 reg = <0x7>; 343 }; 344 345 dpmac8: dpmac@8 { 346 compatible = "fsl,qoriq-mc-dpmac"; 347 reg = <0x8>; 348 }; 349 350 dpmac9: dpmac@9 { 351 compatible = "fsl,qoriq-mc-dpmac"; 352 reg = <0x9>; 353 }; 354 355 dpmac10: dpmac@a { 356 compatible = "fsl,qoriq-mc-dpmac"; 357 reg = <0xa>; 358 }; 359 360 dpmac11: dpmac@b { 361 compatible = "fsl,qoriq-mc-dpmac"; 362 reg = <0xb>; 363 }; 364 365 dpmac12: dpmac@c { 366 compatible = "fsl,qoriq-mc-dpmac"; 367 reg = <0xc>; 368 }; 369 370 dpmac13: dpmac@d { 371 compatible = "fsl,qoriq-mc-dpmac"; 372 reg = <0xd>; 373 }; 374 375 dpmac14: dpmac@e { 376 compatible = "fsl,qoriq-mc-dpmac"; 377 reg = <0xe>; 378 }; 379 380 dpmac15: dpmac@f { 381 compatible = "fsl,qoriq-mc-dpmac"; 382 reg = <0xf>; 383 }; 384 385 dpmac16: dpmac@10 { 386 compatible = "fsl,qoriq-mc-dpmac"; 387 reg = <0x10>; 388 }; 389 }; 390 }; 391 392 smmu: iommu@5000000 { 393 compatible = "arm,mmu-500"; 394 reg = <0 0x5000000 0 0x800000>; 395 #global-interrupts = <12>; 396 interrupts = <0 13 4>, /* global secure fault */ 397 <0 14 4>, /* combined secure interrupt */ 398 <0 15 4>, /* global non-secure fault */ 399 <0 16 4>, /* combined non-secure interrupt */ 400 /* performance counter interrupts 0-7 */ 401 <0 211 4>, <0 212 4>, 402 <0 213 4>, <0 214 4>, 403 <0 215 4>, <0 216 4>, 404 <0 217 4>, <0 218 4>, 405 /* per context interrupt, 64 interrupts */ 406 <0 146 4>, <0 147 4>, 407 <0 148 4>, <0 149 4>, 408 <0 150 4>, <0 151 4>, 409 <0 152 4>, <0 153 4>, 410 <0 154 4>, <0 155 4>, 411 <0 156 4>, <0 157 4>, 412 <0 158 4>, <0 159 4>, 413 <0 160 4>, <0 161 4>, 414 <0 162 4>, <0 163 4>, 415 <0 164 4>, <0 165 4>, 416 <0 166 4>, <0 167 4>, 417 <0 168 4>, <0 169 4>, 418 <0 170 4>, <0 171 4>, 419 <0 172 4>, <0 173 4>, 420 <0 174 4>, <0 175 4>, 421 <0 176 4>, <0 177 4>, 422 <0 178 4>, <0 179 4>, 423 <0 180 4>, <0 181 4>, 424 <0 182 4>, <0 183 4>, 425 <0 184 4>, <0 185 4>, 426 <0 186 4>, <0 187 4>, 427 <0 188 4>, <0 189 4>, 428 <0 190 4>, <0 191 4>, 429 <0 192 4>, <0 193 4>, 430 <0 194 4>, <0 195 4>, 431 <0 196 4>, <0 197 4>, 432 <0 198 4>, <0 199 4>, 433 <0 200 4>, <0 201 4>, 434 <0 202 4>, <0 203 4>, 435 <0 204 4>, <0 205 4>, 436 <0 206 4>, <0 207 4>, 437 <0 208 4>, <0 209 4>; 438 mmu-masters = <&fsl_mc 0x300 0>; 439 }; 440 441 dspi: dspi@2100000 { 442 status = "disabled"; 443 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 reg = <0x0 0x2100000 0x0 0x10000>; 447 interrupts = <0 26 0x4>; /* Level high type */ 448 clocks = <&clockgen 4 3>; 449 clock-names = "dspi"; 450 spi-num-chipselects = <5>; 451 bus-num = <0>; 452 }; 453 454 esdhc: esdhc@2140000 { 455 status = "disabled"; 456 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 457 reg = <0x0 0x2140000 0x0 0x10000>; 458 interrupts = <0 28 0x4>; /* Level high type */ 459 clock-frequency = <0>; /* Updated by bootloader */ 460 voltage-ranges = <1800 1800 3300 3300>; 461 sdhci,auto-cmd12; 462 little-endian; 463 bus-width = <4>; 464 }; 465 466 gpio0: gpio@2300000 { 467 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 468 reg = <0x0 0x2300000 0x0 0x10000>; 469 interrupts = <0 36 0x4>; /* Level high type */ 470 gpio-controller; 471 little-endian; 472 #gpio-cells = <2>; 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 }; 476 477 gpio1: gpio@2310000 { 478 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 479 reg = <0x0 0x2310000 0x0 0x10000>; 480 interrupts = <0 36 0x4>; /* Level high type */ 481 gpio-controller; 482 little-endian; 483 #gpio-cells = <2>; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 }; 487 488 gpio2: gpio@2320000 { 489 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 490 reg = <0x0 0x2320000 0x0 0x10000>; 491 interrupts = <0 37 0x4>; /* Level high type */ 492 gpio-controller; 493 little-endian; 494 #gpio-cells = <2>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 }; 498 499 gpio3: gpio@2330000 { 500 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 501 reg = <0x0 0x2330000 0x0 0x10000>; 502 interrupts = <0 37 0x4>; /* Level high type */ 503 gpio-controller; 504 little-endian; 505 #gpio-cells = <2>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 }; 509 510 i2c0: i2c@2000000 { 511 status = "disabled"; 512 compatible = "fsl,vf610-i2c"; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <0x0 0x2000000 0x0 0x10000>; 516 interrupts = <0 34 0x4>; /* Level high type */ 517 clock-names = "i2c"; 518 clocks = <&clockgen 4 3>; 519 }; 520 521 i2c1: i2c@2010000 { 522 status = "disabled"; 523 compatible = "fsl,vf610-i2c"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <0x0 0x2010000 0x0 0x10000>; 527 interrupts = <0 34 0x4>; /* Level high type */ 528 clock-names = "i2c"; 529 clocks = <&clockgen 4 3>; 530 }; 531 532 i2c2: i2c@2020000 { 533 status = "disabled"; 534 compatible = "fsl,vf610-i2c"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 reg = <0x0 0x2020000 0x0 0x10000>; 538 interrupts = <0 35 0x4>; /* Level high type */ 539 clock-names = "i2c"; 540 clocks = <&clockgen 4 3>; 541 }; 542 543 i2c3: i2c@2030000 { 544 status = "disabled"; 545 compatible = "fsl,vf610-i2c"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 reg = <0x0 0x2030000 0x0 0x10000>; 549 interrupts = <0 35 0x4>; /* Level high type */ 550 clock-names = "i2c"; 551 clocks = <&clockgen 4 3>; 552 }; 553 554 ifc: ifc@2240000 { 555 compatible = "fsl,ifc", "simple-bus"; 556 reg = <0x0 0x2240000 0x0 0x20000>; 557 interrupts = <0 21 0x4>; /* Level high type */ 558 little-endian; 559 #address-cells = <2>; 560 #size-cells = <1>; 561 562 ranges = <0 0 0x5 0x80000000 0x08000000 563 2 0 0x5 0x30000000 0x00010000 564 3 0 0x5 0x20000000 0x00010000>; 565 }; 566 567 qspi: quadspi@20c0000 { 568 status = "disabled"; 569 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 reg = <0x0 0x20c0000 0x0 0x10000>, 573 <0x0 0x20000000 0x0 0x10000000>; 574 reg-names = "QuadSPI", "QuadSPI-memory"; 575 interrupts = <0 25 0x4>; /* Level high type */ 576 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 577 clock-names = "qspi_en", "qspi"; 578 }; 579 580 pcie@3400000 { 581 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 582 "snps,dw-pcie"; 583 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 584 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ 585 reg-names = "regs", "config"; 586 interrupts = <0 108 0x4>; /* Level high type */ 587 interrupt-names = "intr"; 588 #address-cells = <3>; 589 #size-cells = <2>; 590 device_type = "pci"; 591 num-lanes = <4>; 592 bus-range = <0x0 0xff>; 593 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ 594 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 595 msi-parent = <&its>; 596 #interrupt-cells = <1>; 597 interrupt-map-mask = <0 0 0 7>; 598 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, 599 <0000 0 0 2 &gic 0 0 0 110 4>, 600 <0000 0 0 3 &gic 0 0 0 111 4>, 601 <0000 0 0 4 &gic 0 0 0 112 4>; 602 }; 603 604 pcie@3500000 { 605 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 606 "snps,dw-pcie"; 607 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 608 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ 609 reg-names = "regs", "config"; 610 interrupts = <0 113 0x4>; /* Level high type */ 611 interrupt-names = "intr"; 612 #address-cells = <3>; 613 #size-cells = <2>; 614 device_type = "pci"; 615 num-lanes = <4>; 616 bus-range = <0x0 0xff>; 617 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ 618 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 619 msi-parent = <&its>; 620 #interrupt-cells = <1>; 621 interrupt-map-mask = <0 0 0 7>; 622 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, 623 <0000 0 0 2 &gic 0 0 0 115 4>, 624 <0000 0 0 3 &gic 0 0 0 116 4>, 625 <0000 0 0 4 &gic 0 0 0 117 4>; 626 }; 627 628 pcie@3600000 { 629 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 630 "snps,dw-pcie"; 631 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 632 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ 633 reg-names = "regs", "config"; 634 interrupts = <0 118 0x4>; /* Level high type */ 635 interrupt-names = "intr"; 636 #address-cells = <3>; 637 #size-cells = <2>; 638 device_type = "pci"; 639 num-lanes = <8>; 640 bus-range = <0x0 0xff>; 641 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ 642 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 643 msi-parent = <&its>; 644 #interrupt-cells = <1>; 645 interrupt-map-mask = <0 0 0 7>; 646 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, 647 <0000 0 0 2 &gic 0 0 0 120 4>, 648 <0000 0 0 3 &gic 0 0 0 121 4>, 649 <0000 0 0 4 &gic 0 0 0 122 4>; 650 }; 651 652 pcie@3700000 { 653 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 654 "snps,dw-pcie"; 655 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 656 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ 657 reg-names = "regs", "config"; 658 interrupts = <0 123 0x4>; /* Level high type */ 659 interrupt-names = "intr"; 660 #address-cells = <3>; 661 #size-cells = <2>; 662 device_type = "pci"; 663 num-lanes = <4>; 664 bus-range = <0x0 0xff>; 665 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ 666 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 667 msi-parent = <&its>; 668 #interrupt-cells = <1>; 669 interrupt-map-mask = <0 0 0 7>; 670 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, 671 <0000 0 0 2 &gic 0 0 0 125 4>, 672 <0000 0 0 3 &gic 0 0 0 126 4>, 673 <0000 0 0 4 &gic 0 0 0 127 4>; 674 }; 675 676 sata0: sata@3200000 { 677 status = "disabled"; 678 compatible = "fsl,ls2080a-ahci"; 679 reg = <0x0 0x3200000 0x0 0x10000>; 680 interrupts = <0 133 0x4>; /* Level high type */ 681 clocks = <&clockgen 4 3>; 682 }; 683 684 sata1: sata@3210000 { 685 status = "disabled"; 686 compatible = "fsl,ls2080a-ahci"; 687 reg = <0x0 0x3210000 0x0 0x10000>; 688 interrupts = <0 136 0x4>; /* Level high type */ 689 clocks = <&clockgen 4 3>; 690 }; 691 692 usb0: usb3@3100000 { 693 status = "disabled"; 694 compatible = "snps,dwc3"; 695 reg = <0x0 0x3100000 0x0 0x10000>; 696 interrupts = <0 80 0x4>; /* Level high type */ 697 dr_mode = "host"; 698 snps,quirk-frame-length-adjustment = <0x20>; 699 snps,dis_rxdet_inp3_quirk; 700 }; 701 702 usb1: usb3@3110000 { 703 status = "disabled"; 704 compatible = "snps,dwc3"; 705 reg = <0x0 0x3110000 0x0 0x10000>; 706 interrupts = <0 81 0x4>; /* Level high type */ 707 dr_mode = "host"; 708 snps,quirk-frame-length-adjustment = <0x20>; 709 snps,dis_rxdet_inp3_quirk; 710 }; 711 712 ccn@4000000 { 713 compatible = "arm,ccn-504"; 714 reg = <0x0 0x04000000 0x0 0x01000000>; 715 interrupts = <0 12 4>; 716 }; 717 }; 718}; 719