1/* 2 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 3 * 4 * Copyright (C) 2014-2015, Freescale Semiconductor 5 * 6 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPLv2 or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This library is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This library is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/thermal/thermal.h> 48 49/ { 50 compatible = "fsl,ls2080a"; 51 interrupt-parent = <&gic>; 52 #address-cells = <2>; 53 #size-cells = <2>; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 /* 60 * We expect the enable-method for cpu's to be "psci", but this 61 * is dependent on the SoC FW, which will fill this in. 62 * 63 * Currently supported enable-method is psci v0.2 64 */ 65 66 /* We have 4 clusters having 2 Cortex-A57 cores each */ 67 cpu0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a57"; 70 reg = <0x0>; 71 clocks = <&clockgen 1 0>; 72 next-level-cache = <&cluster0_l2>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu1: cpu@1 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a57"; 79 reg = <0x1>; 80 clocks = <&clockgen 1 0>; 81 next-level-cache = <&cluster0_l2>; 82 }; 83 84 cpu2: cpu@100 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a57"; 87 reg = <0x100>; 88 clocks = <&clockgen 1 1>; 89 next-level-cache = <&cluster1_l2>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu3: cpu@101 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a57"; 96 reg = <0x101>; 97 clocks = <&clockgen 1 1>; 98 next-level-cache = <&cluster1_l2>; 99 }; 100 101 cpu4: cpu@200 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a57"; 104 reg = <0x200>; 105 clocks = <&clockgen 1 2>; 106 next-level-cache = <&cluster2_l2>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu5: cpu@201 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a57"; 113 reg = <0x201>; 114 clocks = <&clockgen 1 2>; 115 next-level-cache = <&cluster2_l2>; 116 }; 117 118 cpu6: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a57"; 121 reg = <0x300>; 122 clocks = <&clockgen 1 3>; 123 next-level-cache = <&cluster3_l2>; 124 #cooling-cells = <2>; 125 }; 126 127 cpu7: cpu@301 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a57"; 130 reg = <0x301>; 131 clocks = <&clockgen 1 3>; 132 next-level-cache = <&cluster3_l2>; 133 }; 134 135 cluster0_l2: l2-cache0 { 136 compatible = "cache"; 137 }; 138 139 cluster1_l2: l2-cache1 { 140 compatible = "cache"; 141 }; 142 143 cluster2_l2: l2-cache2 { 144 compatible = "cache"; 145 }; 146 147 cluster3_l2: l2-cache3 { 148 compatible = "cache"; 149 }; 150 }; 151 152 memory@80000000 { 153 device_type = "memory"; 154 reg = <0x00000000 0x80000000 0 0x80000000>; 155 /* DRAM space - 1, size : 2 GB DRAM */ 156 }; 157 158 sysclk: sysclk { 159 compatible = "fixed-clock"; 160 #clock-cells = <0>; 161 clock-frequency = <100000000>; 162 clock-output-names = "sysclk"; 163 }; 164 165 gic: interrupt-controller@6000000 { 166 compatible = "arm,gic-v3"; 167 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 168 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 169 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 170 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 171 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 172 #interrupt-cells = <3>; 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges; 176 interrupt-controller; 177 interrupts = <1 9 0x4>; 178 179 its: gic-its@6020000 { 180 compatible = "arm,gic-v3-its"; 181 msi-controller; 182 reg = <0x0 0x6020000 0 0x20000>; 183 }; 184 }; 185 186 rstcr: syscon@1e60000 { 187 compatible = "fsl,ls2080a-rstcr", "syscon"; 188 reg = <0x0 0x1e60000 0x0 0x4>; 189 }; 190 191 reboot { 192 compatible ="syscon-reboot"; 193 regmap = <&rstcr>; 194 offset = <0x0>; 195 mask = <0x2>; 196 }; 197 198 timer { 199 compatible = "arm,armv8-timer"; 200 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ 201 <1 14 4>, /* Physical Non-Secure PPI, active-low */ 202 <1 11 4>, /* Virtual PPI, active-low */ 203 <1 10 4>; /* Hypervisor PPI, active-low */ 204 fsl,erratum-a008585; 205 }; 206 207 pmu { 208 compatible = "arm,armv8-pmuv3"; 209 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 210 }; 211 212 soc { 213 compatible = "simple-bus"; 214 #address-cells = <2>; 215 #size-cells = <2>; 216 ranges; 217 218 clockgen: clocking@1300000 { 219 compatible = "fsl,ls2080a-clockgen"; 220 reg = <0 0x1300000 0 0xa0000>; 221 #clock-cells = <2>; 222 clocks = <&sysclk>; 223 }; 224 225 dcfg: dcfg@1e00000 { 226 compatible = "fsl,ls2080a-dcfg", "syscon"; 227 reg = <0x0 0x1e00000 0x0 0x10000>; 228 little-endian; 229 }; 230 231 tmu: tmu@1f80000 { 232 compatible = "fsl,qoriq-tmu"; 233 reg = <0x0 0x1f80000 0x0 0x10000>; 234 interrupts = <0 23 0x4>; 235 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 236 fsl,tmu-calibration = <0x00000000 0x00000026 237 0x00000001 0x0000002d 238 0x00000002 0x00000032 239 0x00000003 0x00000039 240 0x00000004 0x0000003f 241 0x00000005 0x00000046 242 0x00000006 0x0000004d 243 0x00000007 0x00000054 244 0x00000008 0x0000005a 245 0x00000009 0x00000061 246 0x0000000a 0x0000006a 247 0x0000000b 0x00000071 248 249 0x00010000 0x00000025 250 0x00010001 0x0000002c 251 0x00010002 0x00000035 252 0x00010003 0x0000003d 253 0x00010004 0x00000045 254 0x00010005 0x0000004e 255 0x00010006 0x00000057 256 0x00010007 0x00000061 257 0x00010008 0x0000006b 258 0x00010009 0x00000076 259 260 0x00020000 0x00000029 261 0x00020001 0x00000033 262 0x00020002 0x0000003d 263 0x00020003 0x00000049 264 0x00020004 0x00000056 265 0x00020005 0x00000061 266 0x00020006 0x0000006d 267 268 0x00030000 0x00000021 269 0x00030001 0x0000002a 270 0x00030002 0x0000003c 271 0x00030003 0x0000004e>; 272 little-endian; 273 #thermal-sensor-cells = <1>; 274 }; 275 276 thermal-zones { 277 cpu_thermal: cpu-thermal { 278 polling-delay-passive = <1000>; 279 polling-delay = <5000>; 280 281 thermal-sensors = <&tmu 4>; 282 283 trips { 284 cpu_alert: cpu-alert { 285 temperature = <75000>; 286 hysteresis = <2000>; 287 type = "passive"; 288 }; 289 cpu_crit: cpu-crit { 290 temperature = <85000>; 291 hysteresis = <2000>; 292 type = "critical"; 293 }; 294 }; 295 296 cooling-maps { 297 map0 { 298 trip = <&cpu_alert>; 299 cooling-device = 300 <&cpu0 THERMAL_NO_LIMIT 301 THERMAL_NO_LIMIT>; 302 }; 303 map1 { 304 trip = <&cpu_alert>; 305 cooling-device = 306 <&cpu2 THERMAL_NO_LIMIT 307 THERMAL_NO_LIMIT>; 308 }; 309 map2 { 310 trip = <&cpu_alert>; 311 cooling-device = 312 <&cpu4 THERMAL_NO_LIMIT 313 THERMAL_NO_LIMIT>; 314 }; 315 map3 { 316 trip = <&cpu_alert>; 317 cooling-device = 318 <&cpu6 THERMAL_NO_LIMIT 319 THERMAL_NO_LIMIT>; 320 }; 321 }; 322 }; 323 }; 324 325 serial0: serial@21c0500 { 326 compatible = "fsl,ns16550", "ns16550a"; 327 reg = <0x0 0x21c0500 0x0 0x100>; 328 clocks = <&clockgen 4 3>; 329 interrupts = <0 32 0x4>; /* Level high type */ 330 }; 331 332 serial1: serial@21c0600 { 333 compatible = "fsl,ns16550", "ns16550a"; 334 reg = <0x0 0x21c0600 0x0 0x100>; 335 clocks = <&clockgen 4 3>; 336 interrupts = <0 32 0x4>; /* Level high type */ 337 }; 338 339 cluster1_core0_watchdog: wdt@c000000 { 340 compatible = "arm,sp805-wdt", "arm,primecell"; 341 reg = <0x0 0xc000000 0x0 0x1000>; 342 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 343 clock-names = "apb_pclk", "wdog_clk"; 344 }; 345 346 cluster1_core1_watchdog: wdt@c010000 { 347 compatible = "arm,sp805-wdt", "arm,primecell"; 348 reg = <0x0 0xc010000 0x0 0x1000>; 349 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 350 clock-names = "apb_pclk", "wdog_clk"; 351 }; 352 353 cluster2_core0_watchdog: wdt@c100000 { 354 compatible = "arm,sp805-wdt", "arm,primecell"; 355 reg = <0x0 0xc100000 0x0 0x1000>; 356 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 357 clock-names = "apb_pclk", "wdog_clk"; 358 }; 359 360 cluster2_core1_watchdog: wdt@c110000 { 361 compatible = "arm,sp805-wdt", "arm,primecell"; 362 reg = <0x0 0xc110000 0x0 0x1000>; 363 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 364 clock-names = "apb_pclk", "wdog_clk"; 365 }; 366 367 cluster3_core0_watchdog: wdt@c200000 { 368 compatible = "arm,sp805-wdt", "arm,primecell"; 369 reg = <0x0 0xc200000 0x0 0x1000>; 370 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 371 clock-names = "apb_pclk", "wdog_clk"; 372 }; 373 374 cluster3_core1_watchdog: wdt@c210000 { 375 compatible = "arm,sp805-wdt", "arm,primecell"; 376 reg = <0x0 0xc210000 0x0 0x1000>; 377 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 378 clock-names = "apb_pclk", "wdog_clk"; 379 }; 380 381 cluster4_core0_watchdog: wdt@c300000 { 382 compatible = "arm,sp805-wdt", "arm,primecell"; 383 reg = <0x0 0xc300000 0x0 0x1000>; 384 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 385 clock-names = "apb_pclk", "wdog_clk"; 386 }; 387 388 cluster4_core1_watchdog: wdt@c310000 { 389 compatible = "arm,sp805-wdt", "arm,primecell"; 390 reg = <0x0 0xc310000 0x0 0x1000>; 391 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 392 clock-names = "apb_pclk", "wdog_clk"; 393 }; 394 395 fsl_mc: fsl-mc@80c000000 { 396 compatible = "fsl,qoriq-mc"; 397 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 398 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 399 msi-parent = <&its>; 400 #address-cells = <3>; 401 #size-cells = <1>; 402 403 /* 404 * Region type 0x0 - MC portals 405 * Region type 0x1 - QBMAN portals 406 */ 407 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 408 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 409 410 /* 411 * Define the maximum number of MACs present on the SoC. 412 */ 413 dpmacs { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 417 dpmac1: dpmac@1 { 418 compatible = "fsl,qoriq-mc-dpmac"; 419 reg = <0x1>; 420 }; 421 422 dpmac2: dpmac@2 { 423 compatible = "fsl,qoriq-mc-dpmac"; 424 reg = <0x2>; 425 }; 426 427 dpmac3: dpmac@3 { 428 compatible = "fsl,qoriq-mc-dpmac"; 429 reg = <0x3>; 430 }; 431 432 dpmac4: dpmac@4 { 433 compatible = "fsl,qoriq-mc-dpmac"; 434 reg = <0x4>; 435 }; 436 437 dpmac5: dpmac@5 { 438 compatible = "fsl,qoriq-mc-dpmac"; 439 reg = <0x5>; 440 }; 441 442 dpmac6: dpmac@6 { 443 compatible = "fsl,qoriq-mc-dpmac"; 444 reg = <0x6>; 445 }; 446 447 dpmac7: dpmac@7 { 448 compatible = "fsl,qoriq-mc-dpmac"; 449 reg = <0x7>; 450 }; 451 452 dpmac8: dpmac@8 { 453 compatible = "fsl,qoriq-mc-dpmac"; 454 reg = <0x8>; 455 }; 456 457 dpmac9: dpmac@9 { 458 compatible = "fsl,qoriq-mc-dpmac"; 459 reg = <0x9>; 460 }; 461 462 dpmac10: dpmac@a { 463 compatible = "fsl,qoriq-mc-dpmac"; 464 reg = <0xa>; 465 }; 466 467 dpmac11: dpmac@b { 468 compatible = "fsl,qoriq-mc-dpmac"; 469 reg = <0xb>; 470 }; 471 472 dpmac12: dpmac@c { 473 compatible = "fsl,qoriq-mc-dpmac"; 474 reg = <0xc>; 475 }; 476 477 dpmac13: dpmac@d { 478 compatible = "fsl,qoriq-mc-dpmac"; 479 reg = <0xd>; 480 }; 481 482 dpmac14: dpmac@e { 483 compatible = "fsl,qoriq-mc-dpmac"; 484 reg = <0xe>; 485 }; 486 487 dpmac15: dpmac@f { 488 compatible = "fsl,qoriq-mc-dpmac"; 489 reg = <0xf>; 490 }; 491 492 dpmac16: dpmac@10 { 493 compatible = "fsl,qoriq-mc-dpmac"; 494 reg = <0x10>; 495 }; 496 }; 497 }; 498 499 smmu: iommu@5000000 { 500 compatible = "arm,mmu-500"; 501 reg = <0 0x5000000 0 0x800000>; 502 #global-interrupts = <12>; 503 interrupts = <0 13 4>, /* global secure fault */ 504 <0 14 4>, /* combined secure interrupt */ 505 <0 15 4>, /* global non-secure fault */ 506 <0 16 4>, /* combined non-secure interrupt */ 507 /* performance counter interrupts 0-7 */ 508 <0 211 4>, <0 212 4>, 509 <0 213 4>, <0 214 4>, 510 <0 215 4>, <0 216 4>, 511 <0 217 4>, <0 218 4>, 512 /* per context interrupt, 64 interrupts */ 513 <0 146 4>, <0 147 4>, 514 <0 148 4>, <0 149 4>, 515 <0 150 4>, <0 151 4>, 516 <0 152 4>, <0 153 4>, 517 <0 154 4>, <0 155 4>, 518 <0 156 4>, <0 157 4>, 519 <0 158 4>, <0 159 4>, 520 <0 160 4>, <0 161 4>, 521 <0 162 4>, <0 163 4>, 522 <0 164 4>, <0 165 4>, 523 <0 166 4>, <0 167 4>, 524 <0 168 4>, <0 169 4>, 525 <0 170 4>, <0 171 4>, 526 <0 172 4>, <0 173 4>, 527 <0 174 4>, <0 175 4>, 528 <0 176 4>, <0 177 4>, 529 <0 178 4>, <0 179 4>, 530 <0 180 4>, <0 181 4>, 531 <0 182 4>, <0 183 4>, 532 <0 184 4>, <0 185 4>, 533 <0 186 4>, <0 187 4>, 534 <0 188 4>, <0 189 4>, 535 <0 190 4>, <0 191 4>, 536 <0 192 4>, <0 193 4>, 537 <0 194 4>, <0 195 4>, 538 <0 196 4>, <0 197 4>, 539 <0 198 4>, <0 199 4>, 540 <0 200 4>, <0 201 4>, 541 <0 202 4>, <0 203 4>, 542 <0 204 4>, <0 205 4>, 543 <0 206 4>, <0 207 4>, 544 <0 208 4>, <0 209 4>; 545 mmu-masters = <&fsl_mc 0x300 0>; 546 }; 547 548 dspi: dspi@2100000 { 549 status = "disabled"; 550 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 reg = <0x0 0x2100000 0x0 0x10000>; 554 interrupts = <0 26 0x4>; /* Level high type */ 555 clocks = <&clockgen 4 3>; 556 clock-names = "dspi"; 557 spi-num-chipselects = <5>; 558 bus-num = <0>; 559 }; 560 561 esdhc: esdhc@2140000 { 562 status = "disabled"; 563 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 564 reg = <0x0 0x2140000 0x0 0x10000>; 565 interrupts = <0 28 0x4>; /* Level high type */ 566 clock-frequency = <0>; /* Updated by bootloader */ 567 voltage-ranges = <1800 1800 3300 3300>; 568 sdhci,auto-cmd12; 569 little-endian; 570 bus-width = <4>; 571 }; 572 573 gpio0: gpio@2300000 { 574 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 575 reg = <0x0 0x2300000 0x0 0x10000>; 576 interrupts = <0 36 0x4>; /* Level high type */ 577 gpio-controller; 578 little-endian; 579 #gpio-cells = <2>; 580 interrupt-controller; 581 #interrupt-cells = <2>; 582 }; 583 584 gpio1: gpio@2310000 { 585 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 586 reg = <0x0 0x2310000 0x0 0x10000>; 587 interrupts = <0 36 0x4>; /* Level high type */ 588 gpio-controller; 589 little-endian; 590 #gpio-cells = <2>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 }; 594 595 gpio2: gpio@2320000 { 596 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 597 reg = <0x0 0x2320000 0x0 0x10000>; 598 interrupts = <0 37 0x4>; /* Level high type */ 599 gpio-controller; 600 little-endian; 601 #gpio-cells = <2>; 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 606 gpio3: gpio@2330000 { 607 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 608 reg = <0x0 0x2330000 0x0 0x10000>; 609 interrupts = <0 37 0x4>; /* Level high type */ 610 gpio-controller; 611 little-endian; 612 #gpio-cells = <2>; 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 }; 616 617 i2c0: i2c@2000000 { 618 status = "disabled"; 619 compatible = "fsl,vf610-i2c"; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0x0 0x2000000 0x0 0x10000>; 623 interrupts = <0 34 0x4>; /* Level high type */ 624 clock-names = "i2c"; 625 clocks = <&clockgen 4 3>; 626 }; 627 628 i2c1: i2c@2010000 { 629 status = "disabled"; 630 compatible = "fsl,vf610-i2c"; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 reg = <0x0 0x2010000 0x0 0x10000>; 634 interrupts = <0 34 0x4>; /* Level high type */ 635 clock-names = "i2c"; 636 clocks = <&clockgen 4 3>; 637 }; 638 639 i2c2: i2c@2020000 { 640 status = "disabled"; 641 compatible = "fsl,vf610-i2c"; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 reg = <0x0 0x2020000 0x0 0x10000>; 645 interrupts = <0 35 0x4>; /* Level high type */ 646 clock-names = "i2c"; 647 clocks = <&clockgen 4 3>; 648 }; 649 650 i2c3: i2c@2030000 { 651 status = "disabled"; 652 compatible = "fsl,vf610-i2c"; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 reg = <0x0 0x2030000 0x0 0x10000>; 656 interrupts = <0 35 0x4>; /* Level high type */ 657 clock-names = "i2c"; 658 clocks = <&clockgen 4 3>; 659 }; 660 661 ifc: ifc@2240000 { 662 compatible = "fsl,ifc", "simple-bus"; 663 reg = <0x0 0x2240000 0x0 0x20000>; 664 interrupts = <0 21 0x4>; /* Level high type */ 665 little-endian; 666 #address-cells = <2>; 667 #size-cells = <1>; 668 669 ranges = <0 0 0x5 0x80000000 0x08000000 670 2 0 0x5 0x30000000 0x00010000 671 3 0 0x5 0x20000000 0x00010000>; 672 }; 673 674 qspi: quadspi@20c0000 { 675 status = "disabled"; 676 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 reg = <0x0 0x20c0000 0x0 0x10000>, 680 <0x0 0x20000000 0x0 0x10000000>; 681 reg-names = "QuadSPI", "QuadSPI-memory"; 682 interrupts = <0 25 0x4>; /* Level high type */ 683 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 684 clock-names = "qspi_en", "qspi"; 685 }; 686 687 pcie@3400000 { 688 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 689 "snps,dw-pcie"; 690 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 691 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ 692 reg-names = "regs", "config"; 693 interrupts = <0 108 0x4>; /* Level high type */ 694 interrupt-names = "intr"; 695 #address-cells = <3>; 696 #size-cells = <2>; 697 device_type = "pci"; 698 dma-coherent; 699 num-lanes = <4>; 700 bus-range = <0x0 0xff>; 701 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ 702 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 703 msi-parent = <&its>; 704 #interrupt-cells = <1>; 705 interrupt-map-mask = <0 0 0 7>; 706 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, 707 <0000 0 0 2 &gic 0 0 0 110 4>, 708 <0000 0 0 3 &gic 0 0 0 111 4>, 709 <0000 0 0 4 &gic 0 0 0 112 4>; 710 }; 711 712 pcie@3500000 { 713 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 714 "snps,dw-pcie"; 715 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 716 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ 717 reg-names = "regs", "config"; 718 interrupts = <0 113 0x4>; /* Level high type */ 719 interrupt-names = "intr"; 720 #address-cells = <3>; 721 #size-cells = <2>; 722 device_type = "pci"; 723 dma-coherent; 724 num-lanes = <4>; 725 bus-range = <0x0 0xff>; 726 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ 727 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 728 msi-parent = <&its>; 729 #interrupt-cells = <1>; 730 interrupt-map-mask = <0 0 0 7>; 731 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, 732 <0000 0 0 2 &gic 0 0 0 115 4>, 733 <0000 0 0 3 &gic 0 0 0 116 4>, 734 <0000 0 0 4 &gic 0 0 0 117 4>; 735 }; 736 737 pcie@3600000 { 738 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 739 "snps,dw-pcie"; 740 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 741 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ 742 reg-names = "regs", "config"; 743 interrupts = <0 118 0x4>; /* Level high type */ 744 interrupt-names = "intr"; 745 #address-cells = <3>; 746 #size-cells = <2>; 747 device_type = "pci"; 748 dma-coherent; 749 num-lanes = <8>; 750 bus-range = <0x0 0xff>; 751 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ 752 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 753 msi-parent = <&its>; 754 #interrupt-cells = <1>; 755 interrupt-map-mask = <0 0 0 7>; 756 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, 757 <0000 0 0 2 &gic 0 0 0 120 4>, 758 <0000 0 0 3 &gic 0 0 0 121 4>, 759 <0000 0 0 4 &gic 0 0 0 122 4>; 760 }; 761 762 pcie@3700000 { 763 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 764 "snps,dw-pcie"; 765 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 766 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ 767 reg-names = "regs", "config"; 768 interrupts = <0 123 0x4>; /* Level high type */ 769 interrupt-names = "intr"; 770 #address-cells = <3>; 771 #size-cells = <2>; 772 device_type = "pci"; 773 dma-coherent; 774 num-lanes = <4>; 775 bus-range = <0x0 0xff>; 776 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ 777 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 778 msi-parent = <&its>; 779 #interrupt-cells = <1>; 780 interrupt-map-mask = <0 0 0 7>; 781 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, 782 <0000 0 0 2 &gic 0 0 0 125 4>, 783 <0000 0 0 3 &gic 0 0 0 126 4>, 784 <0000 0 0 4 &gic 0 0 0 127 4>; 785 }; 786 787 sata0: sata@3200000 { 788 status = "disabled"; 789 compatible = "fsl,ls2080a-ahci"; 790 reg = <0x0 0x3200000 0x0 0x10000>; 791 interrupts = <0 133 0x4>; /* Level high type */ 792 clocks = <&clockgen 4 3>; 793 dma-coherent; 794 }; 795 796 sata1: sata@3210000 { 797 status = "disabled"; 798 compatible = "fsl,ls2080a-ahci"; 799 reg = <0x0 0x3210000 0x0 0x10000>; 800 interrupts = <0 136 0x4>; /* Level high type */ 801 clocks = <&clockgen 4 3>; 802 dma-coherent; 803 }; 804 805 usb0: usb3@3100000 { 806 status = "disabled"; 807 compatible = "snps,dwc3"; 808 reg = <0x0 0x3100000 0x0 0x10000>; 809 interrupts = <0 80 0x4>; /* Level high type */ 810 dr_mode = "host"; 811 snps,quirk-frame-length-adjustment = <0x20>; 812 snps,dis_rxdet_inp3_quirk; 813 }; 814 815 usb1: usb3@3110000 { 816 status = "disabled"; 817 compatible = "snps,dwc3"; 818 reg = <0x0 0x3110000 0x0 0x10000>; 819 interrupts = <0 81 0x4>; /* Level high type */ 820 dr_mode = "host"; 821 snps,quirk-frame-length-adjustment = <0x20>; 822 snps,dis_rxdet_inp3_quirk; 823 }; 824 825 ccn@4000000 { 826 compatible = "arm,ccn-504"; 827 reg = <0x0 0x04000000 0x0 0x01000000>; 828 interrupts = <0 12 4>; 829 }; 830 }; 831 832 ddr1: memory-controller@1080000 { 833 compatible = "fsl,qoriq-memory-controller"; 834 reg = <0x0 0x1080000 0x0 0x1000>; 835 interrupts = <0 17 0x4>; 836 little-endian; 837 }; 838 839 ddr2: memory-controller@1090000 { 840 compatible = "fsl,qoriq-memory-controller"; 841 reg = <0x0 0x1090000 0x0 0x1000>; 842 interrupts = <0 18 0x4>; 843 little-endian; 844 }; 845}; 846