1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 4 * 5 * Copyright 2017 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "fsl,ls1088a"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 crypto = &crypto; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 /* We have 2 clusters having 4 Cortex-A53 cores each */ 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a53"; 31 reg = <0x0>; 32 clocks = <&clockgen 1 0>; 33 cpu-idle-states = <&CPU_PH20>; 34 #cooling-cells = <2>; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x1>; 41 clocks = <&clockgen 1 0>; 42 cpu-idle-states = <&CPU_PH20>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x2>; 50 clocks = <&clockgen 1 0>; 51 cpu-idle-states = <&CPU_PH20>; 52 #cooling-cells = <2>; 53 }; 54 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x3>; 59 clocks = <&clockgen 1 0>; 60 cpu-idle-states = <&CPU_PH20>; 61 #cooling-cells = <2>; 62 }; 63 64 cpu4: cpu@100 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x100>; 68 clocks = <&clockgen 1 1>; 69 cpu-idle-states = <&CPU_PH20>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu5: cpu@101 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x101>; 77 clocks = <&clockgen 1 1>; 78 cpu-idle-states = <&CPU_PH20>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu6: cpu@102 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x102>; 86 clocks = <&clockgen 1 1>; 87 cpu-idle-states = <&CPU_PH20>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu7: cpu@103 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x103>; 95 clocks = <&clockgen 1 1>; 96 cpu-idle-states = <&CPU_PH20>; 97 #cooling-cells = <2>; 98 }; 99 100 CPU_PH20: cpu-ph20 { 101 compatible = "arm,idle-state"; 102 idle-state-name = "PH20"; 103 arm,psci-suspend-param = <0x0>; 104 entry-latency-us = <1000>; 105 exit-latency-us = <1000>; 106 min-residency-us = <3000>; 107 }; 108 }; 109 110 gic: interrupt-controller@6000000 { 111 compatible = "arm,gic-v3"; 112 #interrupt-cells = <3>; 113 interrupt-controller; 114 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 115 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 116 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 117 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 118 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 119 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 120 #address-cells = <2>; 121 #size-cells = <2>; 122 ranges; 123 124 its: gic-its@6020000 { 125 compatible = "arm,gic-v3-its"; 126 msi-controller; 127 reg = <0x0 0x6020000 0 0x20000>; 128 }; 129 }; 130 131 thermal-zones { 132 cpu_thermal: cpu-thermal { 133 polling-delay-passive = <1000>; 134 polling-delay = <5000>; 135 thermal-sensors = <&tmu 0>; 136 137 trips { 138 cpu_alert: cpu-alert { 139 temperature = <85000>; 140 hysteresis = <2000>; 141 type = "passive"; 142 }; 143 144 cpu_crit: cpu-crit { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "critical"; 148 }; 149 }; 150 151 cooling-maps { 152 map0 { 153 trip = <&cpu_alert>; 154 cooling-device = 155 <&cpu0 THERMAL_NO_LIMIT 156 THERMAL_NO_LIMIT>; 157 }; 158 159 map1 { 160 trip = <&cpu_alert>; 161 cooling-device = 162 <&cpu4 THERMAL_NO_LIMIT 163 THERMAL_NO_LIMIT>; 164 }; 165 }; 166 }; 167 }; 168 169 timer { 170 compatible = "arm,armv8-timer"; 171 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 172 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 173 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 174 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 175 }; 176 177 fsl_mc: fsl-mc@80c000000 { 178 compatible = "fsl,qoriq-mc"; 179 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 180 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 181 msi-parent = <&its>; 182 #address-cells = <3>; 183 #size-cells = <1>; 184 185 /* 186 * Region type 0x0 - MC portals 187 * Region type 0x1 - QBMAN portals 188 */ 189 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 190 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 191 192 dpmacs { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 196 dpmac1: dpmac@1 { 197 compatible = "fsl,qoriq-mc-dpmac"; 198 reg = <1>; 199 }; 200 201 dpmac2: dpmac@2 { 202 compatible = "fsl,qoriq-mc-dpmac"; 203 reg = <2>; 204 }; 205 206 dpmac3: dpmac@3 { 207 compatible = "fsl,qoriq-mc-dpmac"; 208 reg = <3>; 209 }; 210 211 dpmac4: dpmac@4 { 212 compatible = "fsl,qoriq-mc-dpmac"; 213 reg = <4>; 214 }; 215 216 dpmac5: dpmac@5 { 217 compatible = "fsl,qoriq-mc-dpmac"; 218 reg = <5>; 219 }; 220 221 dpmac6: dpmac@6 { 222 compatible = "fsl,qoriq-mc-dpmac"; 223 reg = <6>; 224 }; 225 226 dpmac7: dpmac@7 { 227 compatible = "fsl,qoriq-mc-dpmac"; 228 reg = <7>; 229 }; 230 231 dpmac8: dpmac@8 { 232 compatible = "fsl,qoriq-mc-dpmac"; 233 reg = <8>; 234 }; 235 236 dpmac9: dpmac@9 { 237 compatible = "fsl,qoriq-mc-dpmac"; 238 reg = <9>; 239 }; 240 241 dpmac10: dpmac@a { 242 compatible = "fsl,qoriq-mc-dpmac"; 243 reg = <0xa>; 244 }; 245 }; 246 }; 247 248 psci { 249 compatible = "arm,psci-0.2"; 250 method = "smc"; 251 }; 252 253 sysclk: sysclk { 254 compatible = "fixed-clock"; 255 #clock-cells = <0>; 256 clock-frequency = <100000000>; 257 clock-output-names = "sysclk"; 258 }; 259 260 soc { 261 compatible = "simple-bus"; 262 #address-cells = <2>; 263 #size-cells = <2>; 264 ranges; 265 266 clockgen: clocking@1300000 { 267 compatible = "fsl,ls1088a-clockgen"; 268 reg = <0 0x1300000 0 0xa0000>; 269 #clock-cells = <2>; 270 clocks = <&sysclk>; 271 }; 272 273 dcfg: dcfg@1e00000 { 274 compatible = "fsl,ls1088a-dcfg", "syscon"; 275 reg = <0x0 0x1e00000 0x0 0x10000>; 276 little-endian; 277 }; 278 279 tmu: tmu@1f80000 { 280 compatible = "fsl,qoriq-tmu"; 281 reg = <0x0 0x1f80000 0x0 0x10000>; 282 interrupts = <0 23 0x4>; 283 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 284 fsl,tmu-calibration = 285 /* Calibration data group 1 */ 286 <0x00000000 0x00000026 287 0x00000001 0x0000002d 288 0x00000002 0x00000032 289 0x00000003 0x00000039 290 0x00000004 0x0000003f 291 0x00000005 0x00000046 292 0x00000006 0x0000004d 293 0x00000007 0x00000054 294 0x00000008 0x0000005a 295 0x00000009 0x00000061 296 0x0000000a 0x0000006a 297 0x0000000b 0x00000071 298 /* Calibration data group 2 */ 299 0x00010000 0x00000025 300 0x00010001 0x0000002c 301 0x00010002 0x00000035 302 0x00010003 0x0000003d 303 0x00010004 0x00000045 304 0x00010005 0x0000004e 305 0x00010006 0x00000057 306 0x00010007 0x00000061 307 0x00010008 0x0000006b 308 0x00010009 0x00000076 309 /* Calibration data group 3 */ 310 0x00020000 0x00000029 311 0x00020001 0x00000033 312 0x00020002 0x0000003d 313 0x00020003 0x00000049 314 0x00020004 0x00000056 315 0x00020005 0x00000061 316 0x00020006 0x0000006d 317 /* Calibration data group 4 */ 318 0x00030000 0x00000021 319 0x00030001 0x0000002a 320 0x00030002 0x0000003c 321 0x00030003 0x0000004e>; 322 little-endian; 323 #thermal-sensor-cells = <1>; 324 }; 325 326 duart0: serial@21c0500 { 327 compatible = "fsl,ns16550", "ns16550a"; 328 reg = <0x0 0x21c0500 0x0 0x100>; 329 clocks = <&clockgen 4 3>; 330 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 331 status = "disabled"; 332 }; 333 334 duart1: serial@21c0600 { 335 compatible = "fsl,ns16550", "ns16550a"; 336 reg = <0x0 0x21c0600 0x0 0x100>; 337 clocks = <&clockgen 4 3>; 338 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 339 status = "disabled"; 340 }; 341 342 gpio0: gpio@2300000 { 343 compatible = "fsl,qoriq-gpio"; 344 reg = <0x0 0x2300000 0x0 0x10000>; 345 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 }; 351 352 gpio1: gpio@2310000 { 353 compatible = "fsl,qoriq-gpio"; 354 reg = <0x0 0x2310000 0x0 0x10000>; 355 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 356 gpio-controller; 357 #gpio-cells = <2>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 }; 361 362 gpio2: gpio@2320000 { 363 compatible = "fsl,qoriq-gpio"; 364 reg = <0x0 0x2320000 0x0 0x10000>; 365 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 366 gpio-controller; 367 #gpio-cells = <2>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 372 gpio3: gpio@2330000 { 373 compatible = "fsl,qoriq-gpio"; 374 reg = <0x0 0x2330000 0x0 0x10000>; 375 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 376 gpio-controller; 377 #gpio-cells = <2>; 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 }; 381 382 ifc: ifc@2240000 { 383 compatible = "fsl,ifc", "simple-bus"; 384 reg = <0x0 0x2240000 0x0 0x20000>; 385 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 386 little-endian; 387 #address-cells = <2>; 388 #size-cells = <1>; 389 status = "disabled"; 390 }; 391 392 i2c0: i2c@2000000 { 393 compatible = "fsl,vf610-i2c"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0x0 0x2000000 0x0 0x10000>; 397 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clockgen 4 3>; 399 status = "disabled"; 400 }; 401 402 i2c1: i2c@2010000 { 403 compatible = "fsl,vf610-i2c"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0x0 0x2010000 0x0 0x10000>; 407 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clockgen 4 3>; 409 status = "disabled"; 410 }; 411 412 i2c2: i2c@2020000 { 413 compatible = "fsl,vf610-i2c"; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 reg = <0x0 0x2020000 0x0 0x10000>; 417 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clockgen 4 3>; 419 status = "disabled"; 420 }; 421 422 i2c3: i2c@2030000 { 423 compatible = "fsl,vf610-i2c"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 reg = <0x0 0x2030000 0x0 0x10000>; 427 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clockgen 4 3>; 429 status = "disabled"; 430 }; 431 432 esdhc: esdhc@2140000 { 433 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 434 reg = <0x0 0x2140000 0x0 0x10000>; 435 interrupts = <0 28 0x4>; /* Level high type */ 436 clock-frequency = <0>; 437 voltage-ranges = <1800 1800 3300 3300>; 438 sdhci,auto-cmd12; 439 little-endian; 440 bus-width = <4>; 441 status = "disabled"; 442 }; 443 444 usb0: usb3@3100000 { 445 compatible = "snps,dwc3"; 446 reg = <0x0 0x3100000 0x0 0x10000>; 447 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 448 dr_mode = "host"; 449 snps,quirk-frame-length-adjustment = <0x20>; 450 snps,dis_rxdet_inp3_quirk; 451 status = "disabled"; 452 }; 453 454 usb1: usb3@3110000 { 455 compatible = "snps,dwc3"; 456 reg = <0x0 0x3110000 0x0 0x10000>; 457 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 458 dr_mode = "host"; 459 snps,quirk-frame-length-adjustment = <0x20>; 460 snps,dis_rxdet_inp3_quirk; 461 status = "disabled"; 462 }; 463 464 sata: sata@3200000 { 465 compatible = "fsl,ls1088a-ahci"; 466 reg = <0x0 0x3200000 0x0 0x10000>, 467 <0x7 0x100520 0x0 0x4>; 468 reg-names = "ahci", "sata-ecc"; 469 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clockgen 4 3>; 471 dma-coherent; 472 status = "disabled"; 473 }; 474 475 crypto: crypto@8000000 { 476 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 477 fsl,sec-era = <8>; 478 #address-cells = <1>; 479 #size-cells = <1>; 480 ranges = <0x0 0x00 0x8000000 0x100000>; 481 reg = <0x00 0x8000000 0x0 0x100000>; 482 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 483 dma-coherent; 484 485 sec_jr0: jr@10000 { 486 compatible = "fsl,sec-v5.0-job-ring", 487 "fsl,sec-v4.0-job-ring"; 488 reg = <0x10000 0x10000>; 489 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 490 }; 491 492 sec_jr1: jr@20000 { 493 compatible = "fsl,sec-v5.0-job-ring", 494 "fsl,sec-v4.0-job-ring"; 495 reg = <0x20000 0x10000>; 496 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 497 }; 498 499 sec_jr2: jr@30000 { 500 compatible = "fsl,sec-v5.0-job-ring", 501 "fsl,sec-v4.0-job-ring"; 502 reg = <0x30000 0x10000>; 503 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 504 }; 505 506 sec_jr3: jr@40000 { 507 compatible = "fsl,sec-v5.0-job-ring", 508 "fsl,sec-v4.0-job-ring"; 509 reg = <0x40000 0x10000>; 510 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 511 }; 512 }; 513 514 pcie@3400000 { 515 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 516 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 517 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 518 reg-names = "regs", "config"; 519 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 520 interrupt-names = "aer"; 521 #address-cells = <3>; 522 #size-cells = <2>; 523 device_type = "pci"; 524 dma-coherent; 525 num-lanes = <4>; 526 bus-range = <0x0 0xff>; 527 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 528 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 529 msi-parent = <&its>; 530 #interrupt-cells = <1>; 531 interrupt-map-mask = <0 0 0 7>; 532 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 533 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 534 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 535 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 536 }; 537 538 pcie@3500000 { 539 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 540 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 541 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 542 reg-names = "regs", "config"; 543 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 544 interrupt-names = "aer"; 545 #address-cells = <3>; 546 #size-cells = <2>; 547 device_type = "pci"; 548 dma-coherent; 549 num-lanes = <4>; 550 bus-range = <0x0 0xff>; 551 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 552 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 553 msi-parent = <&its>; 554 #interrupt-cells = <1>; 555 interrupt-map-mask = <0 0 0 7>; 556 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 557 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 558 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 559 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 560 }; 561 562 pcie@3600000 { 563 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 564 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 565 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 566 reg-names = "regs", "config"; 567 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 568 interrupt-names = "aer"; 569 #address-cells = <3>; 570 #size-cells = <2>; 571 device_type = "pci"; 572 dma-coherent; 573 num-lanes = <8>; 574 bus-range = <0x0 0xff>; 575 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 576 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 577 msi-parent = <&its>; 578 #interrupt-cells = <1>; 579 interrupt-map-mask = <0 0 0 7>; 580 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 581 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 582 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 583 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 584 }; 585 586 cluster1_core0_watchdog: wdt@c000000 { 587 compatible = "arm,sp805-wdt", "arm,primecell"; 588 reg = <0x0 0xc000000 0x0 0x1000>; 589 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 590 clock-names = "apb_pclk", "wdog_clk"; 591 }; 592 593 cluster1_core1_watchdog: wdt@c010000 { 594 compatible = "arm,sp805-wdt", "arm,primecell"; 595 reg = <0x0 0xc010000 0x0 0x1000>; 596 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 597 clock-names = "apb_pclk", "wdog_clk"; 598 }; 599 600 cluster1_core2_watchdog: wdt@c020000 { 601 compatible = "arm,sp805-wdt", "arm,primecell"; 602 reg = <0x0 0xc020000 0x0 0x1000>; 603 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 604 clock-names = "apb_pclk", "wdog_clk"; 605 }; 606 607 cluster1_core3_watchdog: wdt@c030000 { 608 compatible = "arm,sp805-wdt", "arm,primecell"; 609 reg = <0x0 0xc030000 0x0 0x1000>; 610 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 611 clock-names = "apb_pclk", "wdog_clk"; 612 }; 613 614 cluster2_core0_watchdog: wdt@c100000 { 615 compatible = "arm,sp805-wdt", "arm,primecell"; 616 reg = <0x0 0xc100000 0x0 0x1000>; 617 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 618 clock-names = "apb_pclk", "wdog_clk"; 619 }; 620 621 cluster2_core1_watchdog: wdt@c110000 { 622 compatible = "arm,sp805-wdt", "arm,primecell"; 623 reg = <0x0 0xc110000 0x0 0x1000>; 624 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 625 clock-names = "apb_pclk", "wdog_clk"; 626 }; 627 628 cluster2_core2_watchdog: wdt@c120000 { 629 compatible = "arm,sp805-wdt", "arm,primecell"; 630 reg = <0x0 0xc120000 0x0 0x1000>; 631 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 632 clock-names = "apb_pclk", "wdog_clk"; 633 }; 634 635 cluster2_core3_watchdog: wdt@c130000 { 636 compatible = "arm,sp805-wdt", "arm,primecell"; 637 reg = <0x0 0xc130000 0x0 0x1000>; 638 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 639 clock-names = "apb_pclk", "wdog_clk"; 640 }; 641 }; 642 643 firmware { 644 optee { 645 compatible = "linaro,optee-tz"; 646 method = "smc"; 647 }; 648 }; 649 650}; 651