1/* 2 * Device Tree Include file for NXP Layerscape-1088A family SoC. 3 * 4 * Copyright 2017 NXP 5 * 6 * Harninder Rai <harninder.rai@nxp.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPLv2 or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This library is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This library is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/thermal/thermal.h> 48 49/ { 50 compatible = "fsl,ls1088a"; 51 interrupt-parent = <&gic>; 52 #address-cells = <2>; 53 #size-cells = <2>; 54 55 aliases { 56 crypto = &crypto; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 /* We have 2 clusters having 4 Cortex-A53 cores each */ 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0>; 68 clocks = <&clockgen 1 0>; 69 cpu-idle-states = <&CPU_PH20>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x1>; 77 clocks = <&clockgen 1 0>; 78 cpu-idle-states = <&CPU_PH20>; 79 }; 80 81 cpu2: cpu@2 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x2>; 85 clocks = <&clockgen 1 0>; 86 cpu-idle-states = <&CPU_PH20>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 reg = <0x3>; 93 clocks = <&clockgen 1 0>; 94 cpu-idle-states = <&CPU_PH20>; 95 }; 96 97 cpu4: cpu@100 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x100>; 101 clocks = <&clockgen 1 1>; 102 cpu-idle-states = <&CPU_PH20>; 103 #cooling-cells = <2>; 104 }; 105 106 cpu5: cpu@101 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x101>; 110 clocks = <&clockgen 1 1>; 111 cpu-idle-states = <&CPU_PH20>; 112 }; 113 114 cpu6: cpu@102 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x102>; 118 clocks = <&clockgen 1 1>; 119 cpu-idle-states = <&CPU_PH20>; 120 }; 121 122 cpu7: cpu@103 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x103>; 126 clocks = <&clockgen 1 1>; 127 cpu-idle-states = <&CPU_PH20>; 128 }; 129 130 CPU_PH20: cpu-ph20 { 131 compatible = "arm,idle-state"; 132 idle-state-name = "PH20"; 133 arm,psci-suspend-param = <0x00010000>; 134 entry-latency-us = <1000>; 135 exit-latency-us = <1000>; 136 min-residency-us = <3000>; 137 }; 138 }; 139 140 gic: interrupt-controller@6000000 { 141 compatible = "arm,gic-v3"; 142 #interrupt-cells = <3>; 143 interrupt-controller; 144 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 145 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 146 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 147 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 148 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 149 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 its: gic-its@6020000 { 155 compatible = "arm,gic-v3-its"; 156 msi-controller; 157 reg = <0x0 0x6020000 0 0x20000>; 158 }; 159 }; 160 161 timer { 162 compatible = "arm,armv8-timer"; 163 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 164 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 165 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 166 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 167 }; 168 169 psci { 170 compatible = "arm,psci-0.2"; 171 method = "smc"; 172 }; 173 174 sysclk: sysclk { 175 compatible = "fixed-clock"; 176 #clock-cells = <0>; 177 clock-frequency = <100000000>; 178 clock-output-names = "sysclk"; 179 }; 180 181 soc { 182 compatible = "simple-bus"; 183 #address-cells = <2>; 184 #size-cells = <2>; 185 ranges; 186 187 clockgen: clocking@1300000 { 188 compatible = "fsl,ls1088a-clockgen"; 189 reg = <0 0x1300000 0 0xa0000>; 190 #clock-cells = <2>; 191 clocks = <&sysclk>; 192 }; 193 194 tmu: tmu@1f80000 { 195 compatible = "fsl,qoriq-tmu"; 196 reg = <0x0 0x1f80000 0x0 0x10000>; 197 interrupts = <0 23 0x4>; 198 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 199 fsl,tmu-calibration = 200 /* Calibration data group 1 */ 201 <0x00000000 0x00000026 202 0x00000001 0x0000002d 203 0x00000002 0x00000032 204 0x00000003 0x00000039 205 0x00000004 0x0000003f 206 0x00000005 0x00000046 207 0x00000006 0x0000004d 208 0x00000007 0x00000054 209 0x00000008 0x0000005a 210 0x00000009 0x00000061 211 0x0000000a 0x0000006a 212 0x0000000b 0x00000071 213 /* Calibration data group 2 */ 214 0x00010000 0x00000025 215 0x00010001 0x0000002c 216 0x00010002 0x00000035 217 0x00010003 0x0000003d 218 0x00010004 0x00000045 219 0x00010005 0x0000004e 220 0x00010006 0x00000057 221 0x00010007 0x00000061 222 0x00010008 0x0000006b 223 0x00010009 0x00000076 224 /* Calibration data group 3 */ 225 0x00020000 0x00000029 226 0x00020001 0x00000033 227 0x00020002 0x0000003d 228 0x00020003 0x00000049 229 0x00020004 0x00000056 230 0x00020005 0x00000061 231 0x00020006 0x0000006d 232 /* Calibration data group 4 */ 233 0x00030000 0x00000021 234 0x00030001 0x0000002a 235 0x00030002 0x0000003c 236 0x00030003 0x0000004e>; 237 little-endian; 238 #thermal-sensor-cells = <1>; 239 }; 240 241 thermal-zones { 242 cpu_thermal: cpu-thermal { 243 polling-delay-passive = <1000>; 244 polling-delay = <5000>; 245 thermal-sensors = <&tmu 0>; 246 247 trips { 248 cpu_alert: cpu-alert { 249 temperature = <85000>; 250 hysteresis = <2000>; 251 type = "passive"; 252 }; 253 254 cpu_crit: cpu-crit { 255 temperature = <95000>; 256 hysteresis = <2000>; 257 type = "critical"; 258 }; 259 }; 260 261 cooling-maps { 262 map0 { 263 trip = <&cpu_alert>; 264 cooling-device = 265 <&cpu0 THERMAL_NO_LIMIT 266 THERMAL_NO_LIMIT>; 267 }; 268 269 map1 { 270 trip = <&cpu_alert>; 271 cooling-device = 272 <&cpu4 THERMAL_NO_LIMIT 273 THERMAL_NO_LIMIT>; 274 }; 275 }; 276 }; 277 }; 278 279 duart0: serial@21c0500 { 280 compatible = "fsl,ns16550", "ns16550a"; 281 reg = <0x0 0x21c0500 0x0 0x100>; 282 clocks = <&clockgen 4 3>; 283 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 284 status = "disabled"; 285 }; 286 287 duart1: serial@21c0600 { 288 compatible = "fsl,ns16550", "ns16550a"; 289 reg = <0x0 0x21c0600 0x0 0x100>; 290 clocks = <&clockgen 4 3>; 291 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 292 status = "disabled"; 293 }; 294 295 gpio0: gpio@2300000 { 296 compatible = "fsl,qoriq-gpio"; 297 reg = <0x0 0x2300000 0x0 0x10000>; 298 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 299 gpio-controller; 300 #gpio-cells = <2>; 301 interrupt-controller; 302 #interrupt-cells = <2>; 303 }; 304 305 gpio1: gpio@2310000 { 306 compatible = "fsl,qoriq-gpio"; 307 reg = <0x0 0x2310000 0x0 0x10000>; 308 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 309 gpio-controller; 310 #gpio-cells = <2>; 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 }; 314 315 gpio2: gpio@2320000 { 316 compatible = "fsl,qoriq-gpio"; 317 reg = <0x0 0x2320000 0x0 0x10000>; 318 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 319 gpio-controller; 320 #gpio-cells = <2>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 }; 324 325 gpio3: gpio@2330000 { 326 compatible = "fsl,qoriq-gpio"; 327 reg = <0x0 0x2330000 0x0 0x10000>; 328 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 }; 334 335 ifc: ifc@2240000 { 336 compatible = "fsl,ifc", "simple-bus"; 337 reg = <0x0 0x2240000 0x0 0x20000>; 338 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 339 little-endian; 340 #address-cells = <2>; 341 #size-cells = <1>; 342 status = "disabled"; 343 }; 344 345 i2c0: i2c@2000000 { 346 compatible = "fsl,vf610-i2c"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 reg = <0x0 0x2000000 0x0 0x10000>; 350 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clockgen 4 3>; 352 status = "disabled"; 353 }; 354 355 i2c1: i2c@2010000 { 356 compatible = "fsl,vf610-i2c"; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 reg = <0x0 0x2010000 0x0 0x10000>; 360 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&clockgen 4 3>; 362 status = "disabled"; 363 }; 364 365 i2c2: i2c@2020000 { 366 compatible = "fsl,vf610-i2c"; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <0x0 0x2020000 0x0 0x10000>; 370 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clockgen 4 3>; 372 status = "disabled"; 373 }; 374 375 i2c3: i2c@2030000 { 376 compatible = "fsl,vf610-i2c"; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 reg = <0x0 0x2030000 0x0 0x10000>; 380 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clockgen 4 3>; 382 status = "disabled"; 383 }; 384 385 esdhc: esdhc@2140000 { 386 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 387 reg = <0x0 0x2140000 0x0 0x10000>; 388 interrupts = <0 28 0x4>; /* Level high type */ 389 clock-frequency = <0>; 390 voltage-ranges = <1800 1800 3300 3300>; 391 sdhci,auto-cmd12; 392 little-endian; 393 bus-width = <4>; 394 status = "disabled"; 395 }; 396 397 sata: sata@3200000 { 398 compatible = "fsl,ls1088a-ahci"; 399 reg = <0x0 0x3200000 0x0 0x10000>, 400 <0x7 0x100520 0x0 0x4>; 401 reg-names = "ahci", "sata-ecc"; 402 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clockgen 4 3>; 404 dma-coherent; 405 status = "disabled"; 406 }; 407 408 crypto: crypto@8000000 { 409 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 410 fsl,sec-era = <8>; 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges = <0x0 0x00 0x8000000 0x100000>; 414 reg = <0x00 0x8000000 0x0 0x100000>; 415 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 416 dma-coherent; 417 418 sec_jr0: jr@10000 { 419 compatible = "fsl,sec-v5.0-job-ring", 420 "fsl,sec-v4.0-job-ring"; 421 reg = <0x10000 0x10000>; 422 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 423 }; 424 425 sec_jr1: jr@20000 { 426 compatible = "fsl,sec-v5.0-job-ring", 427 "fsl,sec-v4.0-job-ring"; 428 reg = <0x20000 0x10000>; 429 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 430 }; 431 432 sec_jr2: jr@30000 { 433 compatible = "fsl,sec-v5.0-job-ring", 434 "fsl,sec-v4.0-job-ring"; 435 reg = <0x30000 0x10000>; 436 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 437 }; 438 439 sec_jr3: jr@40000 { 440 compatible = "fsl,sec-v5.0-job-ring", 441 "fsl,sec-v4.0-job-ring"; 442 reg = <0x40000 0x10000>; 443 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 444 }; 445 }; 446 447 pcie@3400000 { 448 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 449 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 450 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 451 reg-names = "regs", "config"; 452 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 453 interrupt-names = "aer"; 454 #address-cells = <3>; 455 #size-cells = <2>; 456 device_type = "pci"; 457 dma-coherent; 458 num-lanes = <4>; 459 bus-range = <0x0 0xff>; 460 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 461 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 462 msi-parent = <&its>; 463 #interrupt-cells = <1>; 464 interrupt-map-mask = <0 0 0 7>; 465 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 466 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 467 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 468 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 469 }; 470 471 pcie@3500000 { 472 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 473 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 474 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 475 reg-names = "regs", "config"; 476 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 477 interrupt-names = "aer"; 478 #address-cells = <3>; 479 #size-cells = <2>; 480 device_type = "pci"; 481 dma-coherent; 482 num-lanes = <4>; 483 bus-range = <0x0 0xff>; 484 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 485 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 486 msi-parent = <&its>; 487 #interrupt-cells = <1>; 488 interrupt-map-mask = <0 0 0 7>; 489 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 490 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 491 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 492 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 493 }; 494 495 pcie@3600000 { 496 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 497 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 498 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 499 reg-names = "regs", "config"; 500 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 501 interrupt-names = "aer"; 502 #address-cells = <3>; 503 #size-cells = <2>; 504 device_type = "pci"; 505 dma-coherent; 506 num-lanes = <8>; 507 bus-range = <0x0 0xff>; 508 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 509 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 510 msi-parent = <&its>; 511 #interrupt-cells = <1>; 512 interrupt-map-mask = <0 0 0 7>; 513 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 514 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 515 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 516 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 517 }; 518 }; 519 520 firmware { 521 optee { 522 compatible = "linaro,optee-tz"; 523 method = "smc"; 524 }; 525 }; 526 527}; 528