1/* 2 * Device Tree Include file for NXP Layerscape-1088A family SoC. 3 * 4 * Copyright 2017 NXP 5 * 6 * Harninder Rai <harninder.rai@nxp.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPLv2 or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This library is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This library is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47 48/ { 49 compatible = "fsl,ls1088a"; 50 interrupt-parent = <&gic>; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 /* We have 2 clusters having 4 Cortex-A53 cores each */ 59 cpu0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clocks = <&clockgen 1 0>; 64 }; 65 66 cpu1: cpu@1 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x1>; 70 clocks = <&clockgen 1 0>; 71 }; 72 73 cpu2: cpu@2 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x2>; 77 clocks = <&clockgen 1 0>; 78 }; 79 80 cpu3: cpu@3 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x3>; 84 clocks = <&clockgen 1 0>; 85 }; 86 87 cpu4: cpu@100 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x100>; 91 clocks = <&clockgen 1 1>; 92 }; 93 94 cpu5: cpu@101 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x101>; 98 clocks = <&clockgen 1 1>; 99 }; 100 101 cpu6: cpu@102 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x102>; 105 clocks = <&clockgen 1 1>; 106 }; 107 108 cpu7: cpu@103 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x103>; 112 clocks = <&clockgen 1 1>; 113 }; 114 }; 115 116 gic: interrupt-controller@6000000 { 117 compatible = "arm,gic-v3"; 118 #interrupt-cells = <3>; 119 interrupt-controller; 120 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 121 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 122 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 123 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 124 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 125 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 126 }; 127 128 timer { 129 compatible = "arm,armv8-timer"; 130 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 131 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 132 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 133 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 134 }; 135 136 sysclk: sysclk { 137 compatible = "fixed-clock"; 138 #clock-cells = <0>; 139 clock-frequency = <100000000>; 140 clock-output-names = "sysclk"; 141 }; 142 143 soc { 144 compatible = "simple-bus"; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges; 148 149 clockgen: clocking@1300000 { 150 compatible = "fsl,ls1088a-clockgen"; 151 reg = <0 0x1300000 0 0xa0000>; 152 #clock-cells = <2>; 153 clocks = <&sysclk>; 154 }; 155 156 duart0: serial@21c0500 { 157 compatible = "fsl,ns16550", "ns16550a"; 158 reg = <0x0 0x21c0500 0x0 0x100>; 159 clocks = <&clockgen 4 3>; 160 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 161 status = "disabled"; 162 }; 163 164 duart1: serial@21c0600 { 165 compatible = "fsl,ns16550", "ns16550a"; 166 reg = <0x0 0x21c0600 0x0 0x100>; 167 clocks = <&clockgen 4 3>; 168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 169 status = "disabled"; 170 }; 171 172 gpio0: gpio@2300000 { 173 compatible = "fsl,qoriq-gpio"; 174 reg = <0x0 0x2300000 0x0 0x10000>; 175 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 176 gpio-controller; 177 #gpio-cells = <2>; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 }; 181 182 gpio1: gpio@2310000 { 183 compatible = "fsl,qoriq-gpio"; 184 reg = <0x0 0x2310000 0x0 0x10000>; 185 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 186 gpio-controller; 187 #gpio-cells = <2>; 188 interrupt-controller; 189 #interrupt-cells = <2>; 190 }; 191 192 gpio2: gpio@2320000 { 193 compatible = "fsl,qoriq-gpio"; 194 reg = <0x0 0x2320000 0x0 0x10000>; 195 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 }; 201 202 gpio3: gpio@2330000 { 203 compatible = "fsl,qoriq-gpio"; 204 reg = <0x0 0x2330000 0x0 0x10000>; 205 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 206 gpio-controller; 207 #gpio-cells = <2>; 208 interrupt-controller; 209 #interrupt-cells = <2>; 210 }; 211 212 ifc: ifc@2240000 { 213 compatible = "fsl,ifc", "simple-bus"; 214 reg = <0x0 0x2240000 0x0 0x20000>; 215 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 216 little-endian; 217 #address-cells = <2>; 218 #size-cells = <1>; 219 220 ranges = <0 0 0x5 0x80000000 0x08000000 221 2 0 0x5 0x30000000 0x00010000 222 3 0 0x5 0x20000000 0x00010000>; 223 status = "disabled"; 224 }; 225 226 i2c0: i2c@2000000 { 227 compatible = "fsl,vf610-i2c"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 reg = <0x0 0x2000000 0x0 0x10000>; 231 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&clockgen 4 3>; 233 status = "disabled"; 234 }; 235 236 i2c1: i2c@2010000 { 237 compatible = "fsl,vf610-i2c"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 reg = <0x0 0x2010000 0x0 0x10000>; 241 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&clockgen 4 3>; 243 status = "disabled"; 244 }; 245 246 i2c2: i2c@2020000 { 247 compatible = "fsl,vf610-i2c"; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 reg = <0x0 0x2020000 0x0 0x10000>; 251 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&clockgen 4 3>; 253 status = "disabled"; 254 }; 255 256 i2c3: i2c@2030000 { 257 compatible = "fsl,vf610-i2c"; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 reg = <0x0 0x2030000 0x0 0x10000>; 261 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&clockgen 4 3>; 263 status = "disabled"; 264 }; 265 266 sata: sata@3200000 { 267 compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci"; 268 reg = <0x0 0x3200000 0x0 0x10000>; 269 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clockgen 4 3>; 271 status = "disabled"; 272 }; 273 }; 274 275}; 276