1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 4 * 5 * Copyright 2017-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1088a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 crypto = &crypto; 22 rtc1 = &ftm_alarm0; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 /* We have 2 clusters having 4 Cortex-A53 cores each */ 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a53"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 cpu-idle-states = <&CPU_PH20>; 36 #cooling-cells = <2>; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x1>; 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 44 cpu-idle-states = <&CPU_PH20>; 45 #cooling-cells = <2>; 46 }; 47 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <0x2>; 52 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 53 cpu-idle-states = <&CPU_PH20>; 54 #cooling-cells = <2>; 55 }; 56 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x3>; 61 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 62 cpu-idle-states = <&CPU_PH20>; 63 #cooling-cells = <2>; 64 }; 65 66 cpu4: cpu@100 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x100>; 70 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 71 cpu-idle-states = <&CPU_PH20>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu5: cpu@101 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x101>; 79 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 80 cpu-idle-states = <&CPU_PH20>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu6: cpu@102 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x102>; 88 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 89 cpu-idle-states = <&CPU_PH20>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu7: cpu@103 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x103>; 97 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 98 cpu-idle-states = <&CPU_PH20>; 99 #cooling-cells = <2>; 100 }; 101 102 CPU_PH20: cpu-ph20 { 103 compatible = "arm,idle-state"; 104 idle-state-name = "PH20"; 105 arm,psci-suspend-param = <0x0>; 106 entry-latency-us = <1000>; 107 exit-latency-us = <1000>; 108 min-residency-us = <3000>; 109 }; 110 }; 111 112 gic: interrupt-controller@6000000 { 113 compatible = "arm,gic-v3"; 114 #interrupt-cells = <3>; 115 interrupt-controller; 116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 121 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 its: gic-its@6020000 { 127 compatible = "arm,gic-v3-its"; 128 msi-controller; 129 reg = <0x0 0x6020000 0 0x20000>; 130 }; 131 }; 132 133 thermal-zones { 134 core-cluster { 135 polling-delay-passive = <1000>; 136 polling-delay = <5000>; 137 thermal-sensors = <&tmu 0>; 138 139 trips { 140 core_cluster_alert: core-cluster-alert { 141 temperature = <85000>; 142 hysteresis = <2000>; 143 type = "passive"; 144 }; 145 146 core-cluster-crit { 147 temperature = <95000>; 148 hysteresis = <2000>; 149 type = "critical"; 150 }; 151 }; 152 153 cooling-maps { 154 map0 { 155 trip = <&core_cluster_alert>; 156 cooling-device = 157 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 158 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 163 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 164 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 165 }; 166 }; 167 }; 168 169 soc { 170 polling-delay-passive = <1000>; 171 polling-delay = <5000>; 172 thermal-sensors = <&tmu 1>; 173 174 trips { 175 soc-crit { 176 temperature = <95000>; 177 hysteresis = <2000>; 178 type = "critical"; 179 }; 180 }; 181 }; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 187 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 188 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 189 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 190 }; 191 192 pmu { 193 compatible = "arm,cortex-a53-pmu"; 194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 195 }; 196 197 psci { 198 compatible = "arm,psci-0.2"; 199 method = "smc"; 200 }; 201 202 sysclk: sysclk { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <100000000>; 206 clock-output-names = "sysclk"; 207 }; 208 209 reboot { 210 compatible = "syscon-reboot"; 211 regmap = <&reset>; 212 offset = <0x0>; 213 mask = <0x02>; 214 }; 215 216 soc { 217 compatible = "simple-bus"; 218 #address-cells = <2>; 219 #size-cells = <2>; 220 ranges; 221 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 222 223 clockgen: clocking@1300000 { 224 compatible = "fsl,ls1088a-clockgen"; 225 reg = <0 0x1300000 0 0xa0000>; 226 #clock-cells = <2>; 227 clocks = <&sysclk>; 228 }; 229 230 dcfg: dcfg@1e00000 { 231 compatible = "fsl,ls1088a-dcfg", "syscon"; 232 reg = <0x0 0x1e00000 0x0 0x10000>; 233 little-endian; 234 }; 235 236 reset: syscon@1e60000 { 237 compatible = "fsl,ls1088a-reset", "syscon"; 238 reg = <0x0 0x1e60000 0x0 0x10000>; 239 }; 240 241 isc: syscon@1f70000 { 242 compatible = "fsl,ls1088a-isc", "syscon"; 243 reg = <0x0 0x1f70000 0x0 0x10000>; 244 little-endian; 245 #address-cells = <1>; 246 #size-cells = <1>; 247 ranges = <0x0 0x0 0x1f70000 0x10000>; 248 249 extirq: interrupt-controller@14 { 250 compatible = "fsl,ls1088a-extirq"; 251 #interrupt-cells = <2>; 252 #address-cells = <0>; 253 interrupt-controller; 254 reg = <0x14 4>; 255 interrupt-map = 256 <0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 257 <1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 258 <2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 259 <3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 260 <4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 261 <5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 262 <6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 263 <7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 264 <8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 265 <9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 266 <10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 267 <11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 268 interrupt-map-mask = <0xffffffff 0x0>; 269 }; 270 }; 271 272 tmu: tmu@1f80000 { 273 compatible = "fsl,qoriq-tmu"; 274 reg = <0x0 0x1f80000 0x0 0x10000>; 275 interrupts = <0 23 0x4>; 276 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 277 fsl,tmu-calibration = 278 /* Calibration data group 1 */ 279 <0x00000000 0x00000023 280 0x00000001 0x0000002a 281 0x00000002 0x00000030 282 0x00000003 0x00000037 283 0x00000004 0x0000003d 284 0x00000005 0x00000044 285 0x00000006 0x0000004a 286 0x00000007 0x00000051 287 0x00000008 0x00000057 288 0x00000009 0x0000005e 289 0x0000000a 0x00000064 290 0x0000000b 0x0000006b 291 /* Calibration data group 2 */ 292 0x00010000 0x00000022 293 0x00010001 0x0000002a 294 0x00010002 0x00000032 295 0x00010003 0x0000003a 296 0x00010004 0x00000042 297 0x00010005 0x0000004a 298 0x00010006 0x00000052 299 0x00010007 0x0000005a 300 0x00010008 0x00000062 301 0x00010009 0x0000006a 302 /* Calibration data group 3 */ 303 0x00020000 0x00000021 304 0x00020001 0x0000002b 305 0x00020002 0x00000035 306 0x00020003 0x00000040 307 0x00020004 0x0000004a 308 0x00020005 0x00000054 309 0x00020006 0x0000005e 310 /* Calibration data group 4 */ 311 0x00030000 0x00000010 312 0x00030001 0x0000001c 313 0x00030002 0x00000027 314 0x00030003 0x00000032 315 0x00030004 0x0000003e 316 0x00030005 0x00000049 317 0x00030006 0x00000054 318 0x00030007 0x00000060>; 319 little-endian; 320 #thermal-sensor-cells = <1>; 321 }; 322 323 dspi: spi@2100000 { 324 compatible = "fsl,ls1088a-dspi", 325 "fsl,ls1021a-v1.0-dspi"; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 reg = <0x0 0x2100000 0x0 0x10000>; 329 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 330 clock-names = "dspi"; 331 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 332 QORIQ_CLK_PLL_DIV(2)>; 333 spi-num-chipselects = <6>; 334 status = "disabled"; 335 }; 336 337 duart0: serial@21c0500 { 338 compatible = "fsl,ns16550", "ns16550a"; 339 reg = <0x0 0x21c0500 0x0 0x100>; 340 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 341 QORIQ_CLK_PLL_DIV(4)>; 342 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 343 status = "disabled"; 344 }; 345 346 duart1: serial@21c0600 { 347 compatible = "fsl,ns16550", "ns16550a"; 348 reg = <0x0 0x21c0600 0x0 0x100>; 349 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 350 QORIQ_CLK_PLL_DIV(4)>; 351 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 352 status = "disabled"; 353 }; 354 355 gpio0: gpio@2300000 { 356 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 357 reg = <0x0 0x2300000 0x0 0x10000>; 358 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 359 little-endian; 360 gpio-controller; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 }; 365 366 gpio1: gpio@2310000 { 367 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 368 reg = <0x0 0x2310000 0x0 0x10000>; 369 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 370 little-endian; 371 gpio-controller; 372 #gpio-cells = <2>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 }; 376 377 gpio2: gpio@2320000 { 378 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 379 reg = <0x0 0x2320000 0x0 0x10000>; 380 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 381 little-endian; 382 gpio-controller; 383 #gpio-cells = <2>; 384 interrupt-controller; 385 #interrupt-cells = <2>; 386 }; 387 388 gpio3: gpio@2330000 { 389 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 390 reg = <0x0 0x2330000 0x0 0x10000>; 391 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 392 little-endian; 393 gpio-controller; 394 #gpio-cells = <2>; 395 interrupt-controller; 396 #interrupt-cells = <2>; 397 }; 398 399 ifc: ifc@2240000 { 400 compatible = "fsl,ifc", "simple-bus"; 401 reg = <0x0 0x2240000 0x0 0x20000>; 402 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 403 little-endian; 404 #address-cells = <2>; 405 #size-cells = <1>; 406 status = "disabled"; 407 }; 408 409 i2c0: i2c@2000000 { 410 compatible = "fsl,vf610-i2c"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <0x0 0x2000000 0x0 0x10000>; 414 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 416 QORIQ_CLK_PLL_DIV(8)>; 417 status = "disabled"; 418 }; 419 420 i2c1: i2c@2010000 { 421 compatible = "fsl,vf610-i2c"; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 reg = <0x0 0x2010000 0x0 0x10000>; 425 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 427 QORIQ_CLK_PLL_DIV(8)>; 428 status = "disabled"; 429 }; 430 431 i2c2: i2c@2020000 { 432 compatible = "fsl,vf610-i2c"; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 reg = <0x0 0x2020000 0x0 0x10000>; 436 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 438 QORIQ_CLK_PLL_DIV(8)>; 439 status = "disabled"; 440 }; 441 442 i2c3: i2c@2030000 { 443 compatible = "fsl,vf610-i2c"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 reg = <0x0 0x2030000 0x0 0x10000>; 447 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 449 QORIQ_CLK_PLL_DIV(8)>; 450 status = "disabled"; 451 }; 452 453 qspi: spi@20c0000 { 454 compatible = "fsl,ls2080a-qspi"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 reg = <0x0 0x20c0000 0x0 0x10000>, 458 <0x0 0x20000000 0x0 0x10000000>; 459 reg-names = "QuadSPI", "QuadSPI-memory"; 460 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 461 clock-names = "qspi_en", "qspi"; 462 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 463 QORIQ_CLK_PLL_DIV(4)>, 464 <&clockgen QORIQ_CLK_PLATFORM_PLL 465 QORIQ_CLK_PLL_DIV(4)>; 466 status = "disabled"; 467 }; 468 469 esdhc: esdhc@2140000 { 470 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 471 reg = <0x0 0x2140000 0x0 0x10000>; 472 interrupts = <0 28 0x4>; /* Level high type */ 473 clock-frequency = <0>; 474 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 475 voltage-ranges = <1800 1800 3300 3300>; 476 sdhci,auto-cmd12; 477 little-endian; 478 bus-width = <4>; 479 status = "disabled"; 480 }; 481 482 usb0: usb@3100000 { 483 compatible = "snps,dwc3"; 484 reg = <0x0 0x3100000 0x0 0x10000>; 485 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 486 dr_mode = "host"; 487 snps,quirk-frame-length-adjustment = <0x20>; 488 snps,dis_rxdet_inp3_quirk; 489 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 490 status = "disabled"; 491 }; 492 493 usb1: usb@3110000 { 494 compatible = "snps,dwc3"; 495 reg = <0x0 0x3110000 0x0 0x10000>; 496 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 497 dr_mode = "host"; 498 snps,quirk-frame-length-adjustment = <0x20>; 499 snps,dis_rxdet_inp3_quirk; 500 status = "disabled"; 501 }; 502 503 sata: sata@3200000 { 504 compatible = "fsl,ls1088a-ahci"; 505 reg = <0x0 0x3200000 0x0 0x10000>, 506 <0x7 0x100520 0x0 0x4>; 507 reg-names = "ahci", "sata-ecc"; 508 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 510 QORIQ_CLK_PLL_DIV(4)>; 511 dma-coherent; 512 status = "disabled"; 513 }; 514 515 crypto: crypto@8000000 { 516 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 517 fsl,sec-era = <8>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 ranges = <0x0 0x00 0x8000000 0x100000>; 521 reg = <0x00 0x8000000 0x0 0x100000>; 522 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 523 dma-coherent; 524 525 sec_jr0: jr@10000 { 526 compatible = "fsl,sec-v5.0-job-ring", 527 "fsl,sec-v4.0-job-ring"; 528 reg = <0x10000 0x10000>; 529 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 530 }; 531 532 sec_jr1: jr@20000 { 533 compatible = "fsl,sec-v5.0-job-ring", 534 "fsl,sec-v4.0-job-ring"; 535 reg = <0x20000 0x10000>; 536 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 537 }; 538 539 sec_jr2: jr@30000 { 540 compatible = "fsl,sec-v5.0-job-ring", 541 "fsl,sec-v4.0-job-ring"; 542 reg = <0x30000 0x10000>; 543 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 544 }; 545 546 sec_jr3: jr@40000 { 547 compatible = "fsl,sec-v5.0-job-ring", 548 "fsl,sec-v4.0-job-ring"; 549 reg = <0x40000 0x10000>; 550 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 551 }; 552 }; 553 554 pcie1: pcie@3400000 { 555 compatible = "fsl,ls1088a-pcie"; 556 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 557 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 558 reg-names = "regs", "config"; 559 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 560 interrupt-names = "aer"; 561 #address-cells = <3>; 562 #size-cells = <2>; 563 device_type = "pci"; 564 dma-coherent; 565 num-viewport = <256>; 566 bus-range = <0x0 0xff>; 567 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 568 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 569 msi-parent = <&its>; 570 #interrupt-cells = <1>; 571 interrupt-map-mask = <0 0 0 7>; 572 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 573 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 574 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 575 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 576 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 577 status = "disabled"; 578 }; 579 580 pcie_ep1: pcie-ep@3400000 { 581 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 582 reg = <0x00 0x03400000 0x0 0x00100000>, 583 <0x20 0x00000000 0x8 0x00000000>; 584 reg-names = "regs", "addr_space"; 585 num-ib-windows = <24>; 586 num-ob-windows = <256>; 587 max-functions = /bits/ 8 <2>; 588 status = "disabled"; 589 }; 590 591 pcie2: pcie@3500000 { 592 compatible = "fsl,ls1088a-pcie"; 593 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 594 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 595 reg-names = "regs", "config"; 596 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 597 interrupt-names = "aer"; 598 #address-cells = <3>; 599 #size-cells = <2>; 600 device_type = "pci"; 601 dma-coherent; 602 num-viewport = <6>; 603 bus-range = <0x0 0xff>; 604 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 605 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 606 msi-parent = <&its>; 607 #interrupt-cells = <1>; 608 interrupt-map-mask = <0 0 0 7>; 609 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 610 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 611 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 612 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 613 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 614 status = "disabled"; 615 }; 616 617 pcie_ep2: pcie-ep@3500000 { 618 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 619 reg = <0x00 0x03500000 0x0 0x00100000>, 620 <0x28 0x00000000 0x8 0x00000000>; 621 reg-names = "regs", "addr_space"; 622 num-ib-windows = <6>; 623 num-ob-windows = <6>; 624 status = "disabled"; 625 }; 626 627 pcie3: pcie@3600000 { 628 compatible = "fsl,ls1088a-pcie"; 629 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 630 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 631 reg-names = "regs", "config"; 632 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 633 interrupt-names = "aer"; 634 #address-cells = <3>; 635 #size-cells = <2>; 636 device_type = "pci"; 637 dma-coherent; 638 num-viewport = <6>; 639 bus-range = <0x0 0xff>; 640 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 641 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 642 msi-parent = <&its>; 643 #interrupt-cells = <1>; 644 interrupt-map-mask = <0 0 0 7>; 645 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 646 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 647 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 648 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 649 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 650 status = "disabled"; 651 }; 652 653 pcie_ep3: pcie-ep@3600000 { 654 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 655 reg = <0x00 0x03600000 0x0 0x00100000>, 656 <0x30 0x00000000 0x8 0x00000000>; 657 reg-names = "regs", "addr_space"; 658 num-ib-windows = <6>; 659 num-ob-windows = <6>; 660 status = "disabled"; 661 }; 662 663 smmu: iommu@5000000 { 664 compatible = "arm,mmu-500"; 665 reg = <0 0x5000000 0 0x800000>; 666 #iommu-cells = <1>; 667 stream-match-mask = <0x7C00>; 668 #global-interrupts = <12>; 669 // global secure fault 670 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 671 // combined secure 672 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 673 // global non-secure fault 674 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 675 // combined non-secure 676 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 677 // performance counter interrupts 0-7 678 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 686 // per context interrupt, 64 interrupts 687 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 751 }; 752 753 console@8340020 { 754 compatible = "fsl,dpaa2-console"; 755 reg = <0x00000000 0x08340020 0 0x2>; 756 }; 757 758 ptp-timer@8b95000 { 759 compatible = "fsl,dpaa2-ptp"; 760 reg = <0x0 0x8b95000 0x0 0x100>; 761 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 762 QORIQ_CLK_PLL_DIV(1)>; 763 little-endian; 764 fsl,extts-fifo; 765 }; 766 767 emdio1: mdio@8b96000 { 768 compatible = "fsl,fman-memac-mdio"; 769 reg = <0x0 0x8b96000 0x0 0x1000>; 770 little-endian; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 emdio2: mdio@8b97000 { 777 compatible = "fsl,fman-memac-mdio"; 778 reg = <0x0 0x8b97000 0x0 0x1000>; 779 little-endian; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 status = "disabled"; 783 }; 784 785 pcs_mdio1: mdio@8c07000 { 786 compatible = "fsl,fman-memac-mdio"; 787 reg = <0x0 0x8c07000 0x0 0x1000>; 788 little-endian; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 793 pcs1: ethernet-phy@0 { 794 reg = <0>; 795 }; 796 }; 797 798 pcs_mdio2: mdio@8c0b000 { 799 compatible = "fsl,fman-memac-mdio"; 800 reg = <0x0 0x8c0b000 0x0 0x1000>; 801 little-endian; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 status = "disabled"; 805 806 pcs2: ethernet-phy@0 { 807 reg = <0>; 808 }; 809 }; 810 811 pcs_mdio3: mdio@8c0f000 { 812 compatible = "fsl,fman-memac-mdio"; 813 reg = <0x0 0x8c0f000 0x0 0x1000>; 814 little-endian; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 status = "disabled"; 818 819 pcs3_0: ethernet-phy@0 { 820 reg = <0>; 821 }; 822 823 pcs3_1: ethernet-phy@1 { 824 reg = <1>; 825 }; 826 827 pcs3_2: ethernet-phy@2 { 828 reg = <2>; 829 }; 830 831 pcs3_3: ethernet-phy@3 { 832 reg = <3>; 833 }; 834 }; 835 836 pcs_mdio7: mdio@8c1f000 { 837 compatible = "fsl,fman-memac-mdio"; 838 reg = <0x0 0x8c1f000 0x0 0x1000>; 839 little-endian; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 844 pcs7_0: ethernet-phy@0 { 845 reg = <0>; 846 }; 847 848 pcs7_1: ethernet-phy@1 { 849 reg = <1>; 850 }; 851 852 pcs7_2: ethernet-phy@2 { 853 reg = <2>; 854 }; 855 856 pcs7_3: ethernet-phy@3 { 857 reg = <3>; 858 }; 859 }; 860 861 cluster1_core0_watchdog: wdt@c000000 { 862 compatible = "arm,sp805", "arm,primecell"; 863 reg = <0x0 0xc000000 0x0 0x1000>; 864 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 865 QORIQ_CLK_PLL_DIV(16)>, 866 <&clockgen QORIQ_CLK_PLATFORM_PLL 867 QORIQ_CLK_PLL_DIV(16)>; 868 clock-names = "wdog_clk", "apb_pclk"; 869 }; 870 871 cluster1_core1_watchdog: wdt@c010000 { 872 compatible = "arm,sp805", "arm,primecell"; 873 reg = <0x0 0xc010000 0x0 0x1000>; 874 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 875 QORIQ_CLK_PLL_DIV(16)>, 876 <&clockgen QORIQ_CLK_PLATFORM_PLL 877 QORIQ_CLK_PLL_DIV(16)>; 878 clock-names = "wdog_clk", "apb_pclk"; 879 }; 880 881 cluster1_core2_watchdog: wdt@c020000 { 882 compatible = "arm,sp805", "arm,primecell"; 883 reg = <0x0 0xc020000 0x0 0x1000>; 884 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 885 QORIQ_CLK_PLL_DIV(16)>, 886 <&clockgen QORIQ_CLK_PLATFORM_PLL 887 QORIQ_CLK_PLL_DIV(16)>; 888 clock-names = "wdog_clk", "apb_pclk"; 889 }; 890 891 cluster1_core3_watchdog: wdt@c030000 { 892 compatible = "arm,sp805", "arm,primecell"; 893 reg = <0x0 0xc030000 0x0 0x1000>; 894 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 895 QORIQ_CLK_PLL_DIV(16)>, 896 <&clockgen QORIQ_CLK_PLATFORM_PLL 897 QORIQ_CLK_PLL_DIV(16)>; 898 clock-names = "wdog_clk", "apb_pclk"; 899 }; 900 901 cluster2_core0_watchdog: wdt@c100000 { 902 compatible = "arm,sp805", "arm,primecell"; 903 reg = <0x0 0xc100000 0x0 0x1000>; 904 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 905 QORIQ_CLK_PLL_DIV(16)>, 906 <&clockgen QORIQ_CLK_PLATFORM_PLL 907 QORIQ_CLK_PLL_DIV(16)>; 908 clock-names = "wdog_clk", "apb_pclk"; 909 }; 910 911 cluster2_core1_watchdog: wdt@c110000 { 912 compatible = "arm,sp805", "arm,primecell"; 913 reg = <0x0 0xc110000 0x0 0x1000>; 914 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 915 QORIQ_CLK_PLL_DIV(16)>, 916 <&clockgen QORIQ_CLK_PLATFORM_PLL 917 QORIQ_CLK_PLL_DIV(16)>; 918 clock-names = "wdog_clk", "apb_pclk"; 919 }; 920 921 cluster2_core2_watchdog: wdt@c120000 { 922 compatible = "arm,sp805", "arm,primecell"; 923 reg = <0x0 0xc120000 0x0 0x1000>; 924 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 925 QORIQ_CLK_PLL_DIV(16)>, 926 <&clockgen QORIQ_CLK_PLATFORM_PLL 927 QORIQ_CLK_PLL_DIV(16)>; 928 clock-names = "wdog_clk", "apb_pclk"; 929 }; 930 931 cluster2_core3_watchdog: wdt@c130000 { 932 compatible = "arm,sp805", "arm,primecell"; 933 reg = <0x0 0xc130000 0x0 0x1000>; 934 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 935 QORIQ_CLK_PLL_DIV(16)>, 936 <&clockgen QORIQ_CLK_PLATFORM_PLL 937 QORIQ_CLK_PLL_DIV(16)>; 938 clock-names = "wdog_clk", "apb_pclk"; 939 }; 940 941 fsl_mc: fsl-mc@80c000000 { 942 compatible = "fsl,qoriq-mc"; 943 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 944 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 945 msi-parent = <&its>; 946 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 947 dma-coherent; 948 #address-cells = <3>; 949 #size-cells = <1>; 950 951 /* 952 * Region type 0x0 - MC portals 953 * Region type 0x1 - QBMAN portals 954 */ 955 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 956 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 957 958 dpmacs { 959 #address-cells = <1>; 960 #size-cells = <0>; 961 962 dpmac1: ethernet@1 { 963 compatible = "fsl,qoriq-mc-dpmac"; 964 reg = <1>; 965 }; 966 967 dpmac2: ethernet@2 { 968 compatible = "fsl,qoriq-mc-dpmac"; 969 reg = <2>; 970 }; 971 972 dpmac3: ethernet@3 { 973 compatible = "fsl,qoriq-mc-dpmac"; 974 reg = <3>; 975 }; 976 977 dpmac4: ethernet@4 { 978 compatible = "fsl,qoriq-mc-dpmac"; 979 reg = <4>; 980 }; 981 982 dpmac5: ethernet@5 { 983 compatible = "fsl,qoriq-mc-dpmac"; 984 reg = <5>; 985 }; 986 987 dpmac6: ethernet@6 { 988 compatible = "fsl,qoriq-mc-dpmac"; 989 reg = <6>; 990 }; 991 992 dpmac7: ethernet@7 { 993 compatible = "fsl,qoriq-mc-dpmac"; 994 reg = <7>; 995 }; 996 997 dpmac8: ethernet@8 { 998 compatible = "fsl,qoriq-mc-dpmac"; 999 reg = <8>; 1000 }; 1001 1002 dpmac9: ethernet@9 { 1003 compatible = "fsl,qoriq-mc-dpmac"; 1004 reg = <9>; 1005 }; 1006 1007 dpmac10: ethernet@a { 1008 compatible = "fsl,qoriq-mc-dpmac"; 1009 reg = <0xa>; 1010 }; 1011 }; 1012 }; 1013 1014 rcpm: power-controller@1e34040 { 1015 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1016 reg = <0x0 0x1e34040 0x0 0x18>; 1017 #fsl,rcpm-wakeup-cells = <6>; 1018 little-endian; 1019 }; 1020 1021 ftm_alarm0: timer@2800000 { 1022 compatible = "fsl,ls1088a-ftm-alarm"; 1023 reg = <0x0 0x2800000 0x0 0x10000>; 1024 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 1025 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1026 }; 1027 }; 1028 1029 firmware { 1030 optee { 1031 compatible = "linaro,optee-tz"; 1032 method = "smc"; 1033 }; 1034 }; 1035}; 1036