17a2aeb91SLi Yang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 27a5d7347SHarninder Rai/* 37a5d7347SHarninder Rai * Device Tree Include file for NXP Layerscape-1088A family SoC. 47a5d7347SHarninder Rai * 57a5d7347SHarninder Rai * Copyright 2017 NXP 67a5d7347SHarninder Rai * 77a5d7347SHarninder Rai * Harninder Rai <harninder.rai@nxp.com> 87a5d7347SHarninder Rai * 97a5d7347SHarninder Rai */ 107a5d7347SHarninder Rai#include <dt-bindings/interrupt-controller/arm-gic.h> 11e4990b44SYuantian Tang#include <dt-bindings/thermal/thermal.h> 127a5d7347SHarninder Rai 137a5d7347SHarninder Rai/ { 147a5d7347SHarninder Rai compatible = "fsl,ls1088a"; 157a5d7347SHarninder Rai interrupt-parent = <&gic>; 167a5d7347SHarninder Rai #address-cells = <2>; 177a5d7347SHarninder Rai #size-cells = <2>; 187a5d7347SHarninder Rai 191e09dec9SHoria Geantă aliases { 201e09dec9SHoria Geantă crypto = &crypto; 21f4fe3a86SBiwen Li rtc1 = &ftm_alarm0; 221e09dec9SHoria Geantă }; 231e09dec9SHoria Geantă 247a5d7347SHarninder Rai cpus { 257a5d7347SHarninder Rai #address-cells = <1>; 267a5d7347SHarninder Rai #size-cells = <0>; 277a5d7347SHarninder Rai 287a5d7347SHarninder Rai /* We have 2 clusters having 4 Cortex-A53 cores each */ 297a5d7347SHarninder Rai cpu0: cpu@0 { 307a5d7347SHarninder Rai device_type = "cpu"; 317a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 327a5d7347SHarninder Rai reg = <0x0>; 337a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 345334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 35e4990b44SYuantian Tang #cooling-cells = <2>; 367a5d7347SHarninder Rai }; 377a5d7347SHarninder Rai 387a5d7347SHarninder Rai cpu1: cpu@1 { 397a5d7347SHarninder Rai device_type = "cpu"; 407a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 417a5d7347SHarninder Rai reg = <0x1>; 427a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 435334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 44346f5976SViresh Kumar #cooling-cells = <2>; 457a5d7347SHarninder Rai }; 467a5d7347SHarninder Rai 477a5d7347SHarninder Rai cpu2: cpu@2 { 487a5d7347SHarninder Rai device_type = "cpu"; 497a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 507a5d7347SHarninder Rai reg = <0x2>; 517a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 525334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 53346f5976SViresh Kumar #cooling-cells = <2>; 547a5d7347SHarninder Rai }; 557a5d7347SHarninder Rai 567a5d7347SHarninder Rai cpu3: cpu@3 { 577a5d7347SHarninder Rai device_type = "cpu"; 587a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 597a5d7347SHarninder Rai reg = <0x3>; 607a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 615334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 62346f5976SViresh Kumar #cooling-cells = <2>; 637a5d7347SHarninder Rai }; 647a5d7347SHarninder Rai 657a5d7347SHarninder Rai cpu4: cpu@100 { 667a5d7347SHarninder Rai device_type = "cpu"; 677a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 687a5d7347SHarninder Rai reg = <0x100>; 697a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 705334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 71e4990b44SYuantian Tang #cooling-cells = <2>; 727a5d7347SHarninder Rai }; 737a5d7347SHarninder Rai 747a5d7347SHarninder Rai cpu5: cpu@101 { 757a5d7347SHarninder Rai device_type = "cpu"; 767a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 777a5d7347SHarninder Rai reg = <0x101>; 787a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 795334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 80346f5976SViresh Kumar #cooling-cells = <2>; 817a5d7347SHarninder Rai }; 827a5d7347SHarninder Rai 837a5d7347SHarninder Rai cpu6: cpu@102 { 847a5d7347SHarninder Rai device_type = "cpu"; 857a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 867a5d7347SHarninder Rai reg = <0x102>; 877a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 885334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 89346f5976SViresh Kumar #cooling-cells = <2>; 907a5d7347SHarninder Rai }; 917a5d7347SHarninder Rai 927a5d7347SHarninder Rai cpu7: cpu@103 { 937a5d7347SHarninder Rai device_type = "cpu"; 947a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 957a5d7347SHarninder Rai reg = <0x103>; 967a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 975334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 98346f5976SViresh Kumar #cooling-cells = <2>; 995334e1a2SYuantian Tang }; 1005334e1a2SYuantian Tang 1015334e1a2SYuantian Tang CPU_PH20: cpu-ph20 { 1025334e1a2SYuantian Tang compatible = "arm,idle-state"; 1035334e1a2SYuantian Tang idle-state-name = "PH20"; 10469ea29b0SYuantian Tang arm,psci-suspend-param = <0x0>; 1055334e1a2SYuantian Tang entry-latency-us = <1000>; 1065334e1a2SYuantian Tang exit-latency-us = <1000>; 1075334e1a2SYuantian Tang min-residency-us = <3000>; 1087a5d7347SHarninder Rai }; 1097a5d7347SHarninder Rai }; 1107a5d7347SHarninder Rai 1117a5d7347SHarninder Rai gic: interrupt-controller@6000000 { 1127a5d7347SHarninder Rai compatible = "arm,gic-v3"; 1137a5d7347SHarninder Rai #interrupt-cells = <3>; 1147a5d7347SHarninder Rai interrupt-controller; 1157a5d7347SHarninder Rai reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1167a5d7347SHarninder Rai <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 1177a5d7347SHarninder Rai <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 1187a5d7347SHarninder Rai <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 1197a5d7347SHarninder Rai <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 1207a5d7347SHarninder Rai interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 121a3bbf4c5SHou Zhiqiang #address-cells = <2>; 122a3bbf4c5SHou Zhiqiang #size-cells = <2>; 123a3bbf4c5SHou Zhiqiang ranges; 124a3bbf4c5SHou Zhiqiang 125a3bbf4c5SHou Zhiqiang its: gic-its@6020000 { 126a3bbf4c5SHou Zhiqiang compatible = "arm,gic-v3-its"; 127a3bbf4c5SHou Zhiqiang msi-controller; 128a3bbf4c5SHou Zhiqiang reg = <0x0 0x6020000 0 0x20000>; 129a3bbf4c5SHou Zhiqiang }; 1307a5d7347SHarninder Rai }; 1317a5d7347SHarninder Rai 13285530a7aSFabio Estevam thermal-zones { 13385530a7aSFabio Estevam cpu_thermal: cpu-thermal { 13485530a7aSFabio Estevam polling-delay-passive = <1000>; 13585530a7aSFabio Estevam polling-delay = <5000>; 13685530a7aSFabio Estevam thermal-sensors = <&tmu 0>; 13785530a7aSFabio Estevam 13885530a7aSFabio Estevam trips { 13985530a7aSFabio Estevam cpu_alert: cpu-alert { 14085530a7aSFabio Estevam temperature = <85000>; 14185530a7aSFabio Estevam hysteresis = <2000>; 14285530a7aSFabio Estevam type = "passive"; 14385530a7aSFabio Estevam }; 14485530a7aSFabio Estevam 14585530a7aSFabio Estevam cpu_crit: cpu-crit { 14685530a7aSFabio Estevam temperature = <95000>; 14785530a7aSFabio Estevam hysteresis = <2000>; 14885530a7aSFabio Estevam type = "critical"; 14985530a7aSFabio Estevam }; 15085530a7aSFabio Estevam }; 15185530a7aSFabio Estevam 15285530a7aSFabio Estevam cooling-maps { 15385530a7aSFabio Estevam map0 { 15485530a7aSFabio Estevam trip = <&cpu_alert>; 15585530a7aSFabio Estevam cooling-device = 156c9a1f243SViresh Kumar <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 157c9a1f243SViresh Kumar <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 158c9a1f243SViresh Kumar <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159c9a1f243SViresh Kumar <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160c9a1f243SViresh Kumar <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161c9a1f243SViresh Kumar <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162c9a1f243SViresh Kumar <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 163c9a1f243SViresh Kumar <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 16485530a7aSFabio Estevam }; 16585530a7aSFabio Estevam }; 16685530a7aSFabio Estevam }; 16785530a7aSFabio Estevam }; 16885530a7aSFabio Estevam 1697a5d7347SHarninder Rai timer { 1707a5d7347SHarninder Rai compatible = "arm,armv8-timer"; 1717a5d7347SHarninder Rai interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 1727a5d7347SHarninder Rai <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 1737a5d7347SHarninder Rai <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 1747a5d7347SHarninder Rai <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 1757a5d7347SHarninder Rai }; 1767a5d7347SHarninder Rai 1775334e1a2SYuantian Tang psci { 1785334e1a2SYuantian Tang compatible = "arm,psci-0.2"; 1795334e1a2SYuantian Tang method = "smc"; 1805334e1a2SYuantian Tang }; 1815334e1a2SYuantian Tang 1827a5d7347SHarninder Rai sysclk: sysclk { 1837a5d7347SHarninder Rai compatible = "fixed-clock"; 1847a5d7347SHarninder Rai #clock-cells = <0>; 1857a5d7347SHarninder Rai clock-frequency = <100000000>; 1867a5d7347SHarninder Rai clock-output-names = "sysclk"; 1877a5d7347SHarninder Rai }; 1887a5d7347SHarninder Rai 1897a5d7347SHarninder Rai soc { 1907a5d7347SHarninder Rai compatible = "simple-bus"; 1917a5d7347SHarninder Rai #address-cells = <2>; 1927a5d7347SHarninder Rai #size-cells = <2>; 1937a5d7347SHarninder Rai ranges; 194d9a71ef0SIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 1957a5d7347SHarninder Rai 1967a5d7347SHarninder Rai clockgen: clocking@1300000 { 1977a5d7347SHarninder Rai compatible = "fsl,ls1088a-clockgen"; 1987a5d7347SHarninder Rai reg = <0 0x1300000 0 0xa0000>; 1997a5d7347SHarninder Rai #clock-cells = <2>; 2007a5d7347SHarninder Rai clocks = <&sysclk>; 2017a5d7347SHarninder Rai }; 2027a5d7347SHarninder Rai 20388b64bb1SAshish Kumar dcfg: dcfg@1e00000 { 20488b64bb1SAshish Kumar compatible = "fsl,ls1088a-dcfg", "syscon"; 20588b64bb1SAshish Kumar reg = <0x0 0x1e00000 0x0 0x10000>; 20688b64bb1SAshish Kumar little-endian; 20788b64bb1SAshish Kumar }; 20888b64bb1SAshish Kumar 209e4990b44SYuantian Tang tmu: tmu@1f80000 { 210e4990b44SYuantian Tang compatible = "fsl,qoriq-tmu"; 211e4990b44SYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 212e4990b44SYuantian Tang interrupts = <0 23 0x4>; 213e4990b44SYuantian Tang fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 214e4990b44SYuantian Tang fsl,tmu-calibration = 215e4990b44SYuantian Tang /* Calibration data group 1 */ 216e4990b44SYuantian Tang <0x00000000 0x00000026 217e4990b44SYuantian Tang 0x00000001 0x0000002d 218e4990b44SYuantian Tang 0x00000002 0x00000032 219e4990b44SYuantian Tang 0x00000003 0x00000039 220e4990b44SYuantian Tang 0x00000004 0x0000003f 221e4990b44SYuantian Tang 0x00000005 0x00000046 222e4990b44SYuantian Tang 0x00000006 0x0000004d 223e4990b44SYuantian Tang 0x00000007 0x00000054 224e4990b44SYuantian Tang 0x00000008 0x0000005a 225e4990b44SYuantian Tang 0x00000009 0x00000061 226e4990b44SYuantian Tang 0x0000000a 0x0000006a 227e4990b44SYuantian Tang 0x0000000b 0x00000071 228e4990b44SYuantian Tang /* Calibration data group 2 */ 229e4990b44SYuantian Tang 0x00010000 0x00000025 230e4990b44SYuantian Tang 0x00010001 0x0000002c 231e4990b44SYuantian Tang 0x00010002 0x00000035 232e4990b44SYuantian Tang 0x00010003 0x0000003d 233e4990b44SYuantian Tang 0x00010004 0x00000045 234e4990b44SYuantian Tang 0x00010005 0x0000004e 235e4990b44SYuantian Tang 0x00010006 0x00000057 236e4990b44SYuantian Tang 0x00010007 0x00000061 237e4990b44SYuantian Tang 0x00010008 0x0000006b 238e4990b44SYuantian Tang 0x00010009 0x00000076 239e4990b44SYuantian Tang /* Calibration data group 3 */ 240e4990b44SYuantian Tang 0x00020000 0x00000029 241e4990b44SYuantian Tang 0x00020001 0x00000033 242e4990b44SYuantian Tang 0x00020002 0x0000003d 243e4990b44SYuantian Tang 0x00020003 0x00000049 244e4990b44SYuantian Tang 0x00020004 0x00000056 245e4990b44SYuantian Tang 0x00020005 0x00000061 246e4990b44SYuantian Tang 0x00020006 0x0000006d 247e4990b44SYuantian Tang /* Calibration data group 4 */ 248e4990b44SYuantian Tang 0x00030000 0x00000021 249e4990b44SYuantian Tang 0x00030001 0x0000002a 250e4990b44SYuantian Tang 0x00030002 0x0000003c 251e4990b44SYuantian Tang 0x00030003 0x0000004e>; 252e4990b44SYuantian Tang little-endian; 253e4990b44SYuantian Tang #thermal-sensor-cells = <1>; 254e4990b44SYuantian Tang }; 255e4990b44SYuantian Tang 25660ca9248SChuanhua Han dspi: spi@2100000 { 25760ca9248SChuanhua Han compatible = "fsl,ls1088a-dspi", 25860ca9248SChuanhua Han "fsl,ls1021a-v1.0-dspi"; 25960ca9248SChuanhua Han #address-cells = <1>; 26060ca9248SChuanhua Han #size-cells = <0>; 26160ca9248SChuanhua Han reg = <0x0 0x2100000 0x0 0x10000>; 26260ca9248SChuanhua Han interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 26360ca9248SChuanhua Han clock-names = "dspi"; 26460ca9248SChuanhua Han clocks = <&clockgen 4 1>; 26560ca9248SChuanhua Han spi-num-chipselects = <6>; 26660ca9248SChuanhua Han status = "disabled"; 26760ca9248SChuanhua Han }; 26860ca9248SChuanhua Han 2697a5d7347SHarninder Rai duart0: serial@21c0500 { 2707a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 2717a5d7347SHarninder Rai reg = <0x0 0x21c0500 0x0 0x100>; 2727a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2737a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 2747a5d7347SHarninder Rai status = "disabled"; 2757a5d7347SHarninder Rai }; 2767a5d7347SHarninder Rai 2777a5d7347SHarninder Rai duart1: serial@21c0600 { 2787a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 2797a5d7347SHarninder Rai reg = <0x0 0x21c0600 0x0 0x100>; 2807a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2817a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 2827a5d7347SHarninder Rai status = "disabled"; 2837a5d7347SHarninder Rai }; 2847a5d7347SHarninder Rai 2857a5d7347SHarninder Rai gpio0: gpio@2300000 { 286afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 2877a5d7347SHarninder Rai reg = <0x0 0x2300000 0x0 0x10000>; 2887a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 28966f1f580SChuanhua Han little-endian; 2907a5d7347SHarninder Rai gpio-controller; 2917a5d7347SHarninder Rai #gpio-cells = <2>; 2927a5d7347SHarninder Rai interrupt-controller; 2937a5d7347SHarninder Rai #interrupt-cells = <2>; 2947a5d7347SHarninder Rai }; 2957a5d7347SHarninder Rai 2967a5d7347SHarninder Rai gpio1: gpio@2310000 { 297afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 2987a5d7347SHarninder Rai reg = <0x0 0x2310000 0x0 0x10000>; 2997a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 30066f1f580SChuanhua Han little-endian; 3017a5d7347SHarninder Rai gpio-controller; 3027a5d7347SHarninder Rai #gpio-cells = <2>; 3037a5d7347SHarninder Rai interrupt-controller; 3047a5d7347SHarninder Rai #interrupt-cells = <2>; 3057a5d7347SHarninder Rai }; 3067a5d7347SHarninder Rai 3077a5d7347SHarninder Rai gpio2: gpio@2320000 { 308afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3097a5d7347SHarninder Rai reg = <0x0 0x2320000 0x0 0x10000>; 3107a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 31166f1f580SChuanhua Han little-endian; 3127a5d7347SHarninder Rai gpio-controller; 3137a5d7347SHarninder Rai #gpio-cells = <2>; 3147a5d7347SHarninder Rai interrupt-controller; 3157a5d7347SHarninder Rai #interrupt-cells = <2>; 3167a5d7347SHarninder Rai }; 3177a5d7347SHarninder Rai 3187a5d7347SHarninder Rai gpio3: gpio@2330000 { 319afd3b35fSSong Hui compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3207a5d7347SHarninder Rai reg = <0x0 0x2330000 0x0 0x10000>; 3217a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 32266f1f580SChuanhua Han little-endian; 3237a5d7347SHarninder Rai gpio-controller; 3247a5d7347SHarninder Rai #gpio-cells = <2>; 3257a5d7347SHarninder Rai interrupt-controller; 3267a5d7347SHarninder Rai #interrupt-cells = <2>; 3277a5d7347SHarninder Rai }; 3287a5d7347SHarninder Rai 3297a5d7347SHarninder Rai ifc: ifc@2240000 { 3307a5d7347SHarninder Rai compatible = "fsl,ifc", "simple-bus"; 3317a5d7347SHarninder Rai reg = <0x0 0x2240000 0x0 0x20000>; 3327a5d7347SHarninder Rai interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 3337a5d7347SHarninder Rai little-endian; 3347a5d7347SHarninder Rai #address-cells = <2>; 3357a5d7347SHarninder Rai #size-cells = <1>; 3367a5d7347SHarninder Rai status = "disabled"; 3377a5d7347SHarninder Rai }; 3387a5d7347SHarninder Rai 3397a5d7347SHarninder Rai i2c0: i2c@2000000 { 3407a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3417a5d7347SHarninder Rai #address-cells = <1>; 3427a5d7347SHarninder Rai #size-cells = <0>; 3437a5d7347SHarninder Rai reg = <0x0 0x2000000 0x0 0x10000>; 3447a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 34586c457e3SChuanhua Han clocks = <&clockgen 4 7>; 3467a5d7347SHarninder Rai status = "disabled"; 3477a5d7347SHarninder Rai }; 3487a5d7347SHarninder Rai 3497a5d7347SHarninder Rai i2c1: i2c@2010000 { 3507a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3517a5d7347SHarninder Rai #address-cells = <1>; 3527a5d7347SHarninder Rai #size-cells = <0>; 3537a5d7347SHarninder Rai reg = <0x0 0x2010000 0x0 0x10000>; 3547a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 35586c457e3SChuanhua Han clocks = <&clockgen 4 7>; 3567a5d7347SHarninder Rai status = "disabled"; 3577a5d7347SHarninder Rai }; 3587a5d7347SHarninder Rai 3597a5d7347SHarninder Rai i2c2: i2c@2020000 { 3607a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3617a5d7347SHarninder Rai #address-cells = <1>; 3627a5d7347SHarninder Rai #size-cells = <0>; 3637a5d7347SHarninder Rai reg = <0x0 0x2020000 0x0 0x10000>; 3647a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 36586c457e3SChuanhua Han clocks = <&clockgen 4 7>; 3667a5d7347SHarninder Rai status = "disabled"; 3677a5d7347SHarninder Rai }; 3687a5d7347SHarninder Rai 3697a5d7347SHarninder Rai i2c3: i2c@2030000 { 3707a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3717a5d7347SHarninder Rai #address-cells = <1>; 3727a5d7347SHarninder Rai #size-cells = <0>; 3737a5d7347SHarninder Rai reg = <0x0 0x2030000 0x0 0x10000>; 3747a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 37586c457e3SChuanhua Han clocks = <&clockgen 4 7>; 3767a5d7347SHarninder Rai status = "disabled"; 3777a5d7347SHarninder Rai }; 3787a5d7347SHarninder Rai 37968a2b3fdSAshish Kumar qspi: spi@20c0000 { 38068a2b3fdSAshish Kumar compatible = "fsl,ls2080a-qspi"; 38168a2b3fdSAshish Kumar #address-cells = <1>; 38268a2b3fdSAshish Kumar #size-cells = <0>; 38368a2b3fdSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 38468a2b3fdSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 38568a2b3fdSAshish Kumar reg-names = "QuadSPI", "QuadSPI-memory"; 38668a2b3fdSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 38768a2b3fdSAshish Kumar clock-names = "qspi_en", "qspi"; 38868a2b3fdSAshish Kumar clocks = <&clockgen 4 3>, <&clockgen 4 3>; 38968a2b3fdSAshish Kumar status = "disabled"; 39068a2b3fdSAshish Kumar }; 39168a2b3fdSAshish Kumar 392e56ae178SYangbo Lu esdhc: esdhc@2140000 { 393e56ae178SYangbo Lu compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 394e56ae178SYangbo Lu reg = <0x0 0x2140000 0x0 0x10000>; 395e56ae178SYangbo Lu interrupts = <0 28 0x4>; /* Level high type */ 396e56ae178SYangbo Lu clock-frequency = <0>; 3974671f9cfSYangbo Lu clocks = <&clockgen 2 1>; 398e56ae178SYangbo Lu voltage-ranges = <1800 1800 3300 3300>; 399e56ae178SYangbo Lu sdhci,auto-cmd12; 400e56ae178SYangbo Lu little-endian; 401e56ae178SYangbo Lu bus-width = <4>; 402e56ae178SYangbo Lu status = "disabled"; 403e56ae178SYangbo Lu }; 404e56ae178SYangbo Lu 405df063a1fSyinbo.zhu usb0: usb3@3100000 { 406df063a1fSyinbo.zhu compatible = "snps,dwc3"; 407df063a1fSyinbo.zhu reg = <0x0 0x3100000 0x0 0x10000>; 408df063a1fSyinbo.zhu interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 409df063a1fSyinbo.zhu dr_mode = "host"; 410df063a1fSyinbo.zhu snps,quirk-frame-length-adjustment = <0x20>; 411df063a1fSyinbo.zhu snps,dis_rxdet_inp3_quirk; 4121000ae68SRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 413df063a1fSyinbo.zhu status = "disabled"; 414df063a1fSyinbo.zhu }; 415df063a1fSyinbo.zhu 416df063a1fSyinbo.zhu usb1: usb3@3110000 { 417df063a1fSyinbo.zhu compatible = "snps,dwc3"; 418df063a1fSyinbo.zhu reg = <0x0 0x3110000 0x0 0x10000>; 419df063a1fSyinbo.zhu interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 420df063a1fSyinbo.zhu dr_mode = "host"; 421df063a1fSyinbo.zhu snps,quirk-frame-length-adjustment = <0x20>; 422df063a1fSyinbo.zhu snps,dis_rxdet_inp3_quirk; 423df063a1fSyinbo.zhu status = "disabled"; 424df063a1fSyinbo.zhu }; 425df063a1fSyinbo.zhu 4267a5d7347SHarninder Rai sata: sata@3200000 { 427375b6755SYuantian Tang compatible = "fsl,ls1088a-ahci"; 42883d0c697SYuantian Tang reg = <0x0 0x3200000 0x0 0x10000>, 429375b6755SYuantian Tang <0x7 0x100520 0x0 0x4>; 43083d0c697SYuantian Tang reg-names = "ahci", "sata-ecc"; 4317a5d7347SHarninder Rai interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 4327a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 43383d0c697SYuantian Tang dma-coherent; 4347a5d7347SHarninder Rai status = "disabled"; 4357a5d7347SHarninder Rai }; 4361e09dec9SHoria Geantă 4371e09dec9SHoria Geantă crypto: crypto@8000000 { 4381e09dec9SHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 4391e09dec9SHoria Geantă fsl,sec-era = <8>; 4401e09dec9SHoria Geantă #address-cells = <1>; 4411e09dec9SHoria Geantă #size-cells = <1>; 4421e09dec9SHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 4431e09dec9SHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 4441e09dec9SHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 4451e09dec9SHoria Geantă dma-coherent; 4461e09dec9SHoria Geantă 4471e09dec9SHoria Geantă sec_jr0: jr@10000 { 4481e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4491e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4501e09dec9SHoria Geantă reg = <0x10000 0x10000>; 4511e09dec9SHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4521e09dec9SHoria Geantă }; 4531e09dec9SHoria Geantă 4541e09dec9SHoria Geantă sec_jr1: jr@20000 { 4551e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4561e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4571e09dec9SHoria Geantă reg = <0x20000 0x10000>; 4581e09dec9SHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 4591e09dec9SHoria Geantă }; 4601e09dec9SHoria Geantă 4611e09dec9SHoria Geantă sec_jr2: jr@30000 { 4621e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4631e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4641e09dec9SHoria Geantă reg = <0x30000 0x10000>; 4651e09dec9SHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 4661e09dec9SHoria Geantă }; 4671e09dec9SHoria Geantă 4681e09dec9SHoria Geantă sec_jr3: jr@40000 { 4691e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4701e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4711e09dec9SHoria Geantă reg = <0x40000 0x10000>; 4721e09dec9SHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 4731e09dec9SHoria Geantă }; 4741e09dec9SHoria Geantă }; 475647911c8SHou Zhiqiang 476647911c8SHou Zhiqiang pcie@3400000 { 4771fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 478647911c8SHou Zhiqiang reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 479647911c8SHou Zhiqiang 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 480647911c8SHou Zhiqiang reg-names = "regs", "config"; 481647911c8SHou Zhiqiang interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 482647911c8SHou Zhiqiang interrupt-names = "aer"; 483647911c8SHou Zhiqiang #address-cells = <3>; 484647911c8SHou Zhiqiang #size-cells = <2>; 485647911c8SHou Zhiqiang device_type = "pci"; 486647911c8SHou Zhiqiang dma-coherent; 487881e90d2SHou Zhiqiang num-viewport = <256>; 488647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 489647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 490647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 491647911c8SHou Zhiqiang msi-parent = <&its>; 492647911c8SHou Zhiqiang #interrupt-cells = <1>; 493647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 494647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 495647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 496647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 497647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 498f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 499aa2aa888SBao Xiaowei status = "disabled"; 500647911c8SHou Zhiqiang }; 501647911c8SHou Zhiqiang 502647911c8SHou Zhiqiang pcie@3500000 { 5031fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 504647911c8SHou Zhiqiang reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 505647911c8SHou Zhiqiang 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 506647911c8SHou Zhiqiang reg-names = "regs", "config"; 507647911c8SHou Zhiqiang interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 508647911c8SHou Zhiqiang interrupt-names = "aer"; 509647911c8SHou Zhiqiang #address-cells = <3>; 510647911c8SHou Zhiqiang #size-cells = <2>; 511647911c8SHou Zhiqiang device_type = "pci"; 512647911c8SHou Zhiqiang dma-coherent; 513881e90d2SHou Zhiqiang num-viewport = <6>; 514647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 515647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 516647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 517647911c8SHou Zhiqiang msi-parent = <&its>; 518647911c8SHou Zhiqiang #interrupt-cells = <1>; 519647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 520647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 521647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 522647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 523647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 524f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 525aa2aa888SBao Xiaowei status = "disabled"; 526647911c8SHou Zhiqiang }; 527647911c8SHou Zhiqiang 528647911c8SHou Zhiqiang pcie@3600000 { 5291fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 530647911c8SHou Zhiqiang reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 531647911c8SHou Zhiqiang 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 532647911c8SHou Zhiqiang reg-names = "regs", "config"; 533647911c8SHou Zhiqiang interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 534647911c8SHou Zhiqiang interrupt-names = "aer"; 535647911c8SHou Zhiqiang #address-cells = <3>; 536647911c8SHou Zhiqiang #size-cells = <2>; 537647911c8SHou Zhiqiang device_type = "pci"; 538647911c8SHou Zhiqiang dma-coherent; 539881e90d2SHou Zhiqiang num-viewport = <6>; 540647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 541647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 542647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 543647911c8SHou Zhiqiang msi-parent = <&its>; 544647911c8SHou Zhiqiang #interrupt-cells = <1>; 545647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 546647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 547647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 548647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 549647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 550f93f1e72SHou Zhiqiang iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 551aa2aa888SBao Xiaowei status = "disabled"; 552647911c8SHou Zhiqiang }; 553cc223282SZhang Ying-22455 55483c58a55SNipun Gupta smmu: iommu@5000000 { 55583c58a55SNipun Gupta compatible = "arm,mmu-500"; 55683c58a55SNipun Gupta reg = <0 0x5000000 0 0x800000>; 55783c58a55SNipun Gupta #iommu-cells = <1>; 55883c58a55SNipun Gupta stream-match-mask = <0x7C00>; 55983c58a55SNipun Gupta #global-interrupts = <12>; 56083c58a55SNipun Gupta // global secure fault 56183c58a55SNipun Gupta interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 56283c58a55SNipun Gupta // combined secure 56383c58a55SNipun Gupta <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 56483c58a55SNipun Gupta // global non-secure fault 56583c58a55SNipun Gupta <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 56683c58a55SNipun Gupta // combined non-secure 56783c58a55SNipun Gupta <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 56883c58a55SNipun Gupta // performance counter interrupts 0-7 56983c58a55SNipun Gupta <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 57083c58a55SNipun Gupta <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 57183c58a55SNipun Gupta <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 57283c58a55SNipun Gupta <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 57383c58a55SNipun Gupta <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 57483c58a55SNipun Gupta <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 57583c58a55SNipun Gupta <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 57683c58a55SNipun Gupta <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 57783c58a55SNipun Gupta // per context interrupt, 64 interrupts 57883c58a55SNipun Gupta <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 57983c58a55SNipun Gupta <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 58083c58a55SNipun Gupta <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 58183c58a55SNipun Gupta <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 58283c58a55SNipun Gupta <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 58383c58a55SNipun Gupta <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 58483c58a55SNipun Gupta <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 58583c58a55SNipun Gupta <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 58683c58a55SNipun Gupta <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 58783c58a55SNipun Gupta <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 58883c58a55SNipun Gupta <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 58983c58a55SNipun Gupta <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 59083c58a55SNipun Gupta <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 59183c58a55SNipun Gupta <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 59283c58a55SNipun Gupta <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 59383c58a55SNipun Gupta <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 59483c58a55SNipun Gupta <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 59583c58a55SNipun Gupta <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 59683c58a55SNipun Gupta <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 59783c58a55SNipun Gupta <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 59883c58a55SNipun Gupta <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 59983c58a55SNipun Gupta <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 60083c58a55SNipun Gupta <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 60183c58a55SNipun Gupta <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 60283c58a55SNipun Gupta <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 60383c58a55SNipun Gupta <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 60483c58a55SNipun Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 60583c58a55SNipun Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 60683c58a55SNipun Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 60783c58a55SNipun Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 60883c58a55SNipun Gupta <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 60983c58a55SNipun Gupta <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 61083c58a55SNipun Gupta <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 61183c58a55SNipun Gupta <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 61283c58a55SNipun Gupta <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 61383c58a55SNipun Gupta <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 61483c58a55SNipun Gupta <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 61583c58a55SNipun Gupta <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 61683c58a55SNipun Gupta <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 61783c58a55SNipun Gupta <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 61883c58a55SNipun Gupta <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 61983c58a55SNipun Gupta <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 62083c58a55SNipun Gupta <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 62183c58a55SNipun Gupta <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 62283c58a55SNipun Gupta <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 62383c58a55SNipun Gupta <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 62483c58a55SNipun Gupta <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 62583c58a55SNipun Gupta <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 62683c58a55SNipun Gupta <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 62783c58a55SNipun Gupta <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 62883c58a55SNipun Gupta <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 62983c58a55SNipun Gupta <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 63083c58a55SNipun Gupta <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 63183c58a55SNipun Gupta <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 63283c58a55SNipun Gupta <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 63383c58a55SNipun Gupta <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 63483c58a55SNipun Gupta <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 63583c58a55SNipun Gupta <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 63683c58a55SNipun Gupta <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 63783c58a55SNipun Gupta <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 63883c58a55SNipun Gupta <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 63983c58a55SNipun Gupta <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 64083c58a55SNipun Gupta <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 64183c58a55SNipun Gupta <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 64283c58a55SNipun Gupta }; 64383c58a55SNipun Gupta 644546d92d3SIoana Ciornei console@8340020 { 645546d92d3SIoana Ciornei compatible = "fsl,dpaa2-console"; 646546d92d3SIoana Ciornei reg = <0x00000000 0x08340020 0 0x2>; 647546d92d3SIoana Ciornei }; 648546d92d3SIoana Ciornei 649fe844f19SYangbo Lu ptp-timer@8b95000 { 650fe844f19SYangbo Lu compatible = "fsl,dpaa2-ptp"; 651fe844f19SYangbo Lu reg = <0x0 0x8b95000 0x0 0x100>; 652fe844f19SYangbo Lu clocks = <&clockgen 4 0>; 653fe844f19SYangbo Lu little-endian; 654fe844f19SYangbo Lu fsl,extts-fifo; 655fe844f19SYangbo Lu }; 656fe844f19SYangbo Lu 657cc223282SZhang Ying-22455 cluster1_core0_watchdog: wdt@c000000 { 658cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 659cc223282SZhang Ying-22455 reg = <0x0 0xc000000 0x0 0x1000>; 660cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 661cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 662cc223282SZhang Ying-22455 }; 663cc223282SZhang Ying-22455 664cc223282SZhang Ying-22455 cluster1_core1_watchdog: wdt@c010000 { 665cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 666cc223282SZhang Ying-22455 reg = <0x0 0xc010000 0x0 0x1000>; 667cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 668cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 669cc223282SZhang Ying-22455 }; 670cc223282SZhang Ying-22455 671cc223282SZhang Ying-22455 cluster1_core2_watchdog: wdt@c020000 { 672cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 673cc223282SZhang Ying-22455 reg = <0x0 0xc020000 0x0 0x1000>; 674cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 675cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 676cc223282SZhang Ying-22455 }; 677cc223282SZhang Ying-22455 678cc223282SZhang Ying-22455 cluster1_core3_watchdog: wdt@c030000 { 679cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 680cc223282SZhang Ying-22455 reg = <0x0 0xc030000 0x0 0x1000>; 681cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 682cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 683cc223282SZhang Ying-22455 }; 684cc223282SZhang Ying-22455 685cc223282SZhang Ying-22455 cluster2_core0_watchdog: wdt@c100000 { 686cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 687cc223282SZhang Ying-22455 reg = <0x0 0xc100000 0x0 0x1000>; 688cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 689cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 690cc223282SZhang Ying-22455 }; 691cc223282SZhang Ying-22455 692cc223282SZhang Ying-22455 cluster2_core1_watchdog: wdt@c110000 { 693cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 694cc223282SZhang Ying-22455 reg = <0x0 0xc110000 0x0 0x1000>; 695cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 696cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 697cc223282SZhang Ying-22455 }; 698cc223282SZhang Ying-22455 699cc223282SZhang Ying-22455 cluster2_core2_watchdog: wdt@c120000 { 700cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 701cc223282SZhang Ying-22455 reg = <0x0 0xc120000 0x0 0x1000>; 702cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 703cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 704cc223282SZhang Ying-22455 }; 705cc223282SZhang Ying-22455 706cc223282SZhang Ying-22455 cluster2_core3_watchdog: wdt@c130000 { 707cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 708cc223282SZhang Ying-22455 reg = <0x0 0xc130000 0x0 0x1000>; 709cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 710cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 711cc223282SZhang Ying-22455 }; 712a2468676SIoana Ciocoi Radulescu 713a2468676SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 714a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 715a2468676SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 716a2468676SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 717a2468676SIoana Ciocoi Radulescu msi-parent = <&its>; 71883c58a55SNipun Gupta iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 719859873fbSNipun Gupta dma-coherent; 720a2468676SIoana Ciocoi Radulescu #address-cells = <3>; 721a2468676SIoana Ciocoi Radulescu #size-cells = <1>; 722a2468676SIoana Ciocoi Radulescu 723a2468676SIoana Ciocoi Radulescu /* 724a2468676SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 725a2468676SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 726a2468676SIoana Ciocoi Radulescu */ 727a2468676SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 728a2468676SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 729a2468676SIoana Ciocoi Radulescu 730a2468676SIoana Ciocoi Radulescu dpmacs { 731a2468676SIoana Ciocoi Radulescu #address-cells = <1>; 732a2468676SIoana Ciocoi Radulescu #size-cells = <0>; 733a2468676SIoana Ciocoi Radulescu 734a2468676SIoana Ciocoi Radulescu dpmac1: dpmac@1 { 735a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 736a2468676SIoana Ciocoi Radulescu reg = <1>; 737a2468676SIoana Ciocoi Radulescu }; 738a2468676SIoana Ciocoi Radulescu 739a2468676SIoana Ciocoi Radulescu dpmac2: dpmac@2 { 740a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 741a2468676SIoana Ciocoi Radulescu reg = <2>; 742a2468676SIoana Ciocoi Radulescu }; 743a2468676SIoana Ciocoi Radulescu 744a2468676SIoana Ciocoi Radulescu dpmac3: dpmac@3 { 745a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 746a2468676SIoana Ciocoi Radulescu reg = <3>; 747a2468676SIoana Ciocoi Radulescu }; 748a2468676SIoana Ciocoi Radulescu 749a2468676SIoana Ciocoi Radulescu dpmac4: dpmac@4 { 750a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 751a2468676SIoana Ciocoi Radulescu reg = <4>; 752a2468676SIoana Ciocoi Radulescu }; 753a2468676SIoana Ciocoi Radulescu 754a2468676SIoana Ciocoi Radulescu dpmac5: dpmac@5 { 755a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 756a2468676SIoana Ciocoi Radulescu reg = <5>; 757a2468676SIoana Ciocoi Radulescu }; 758a2468676SIoana Ciocoi Radulescu 759a2468676SIoana Ciocoi Radulescu dpmac6: dpmac@6 { 760a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 761a2468676SIoana Ciocoi Radulescu reg = <6>; 762a2468676SIoana Ciocoi Radulescu }; 763a2468676SIoana Ciocoi Radulescu 764a2468676SIoana Ciocoi Radulescu dpmac7: dpmac@7 { 765a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 766a2468676SIoana Ciocoi Radulescu reg = <7>; 767a2468676SIoana Ciocoi Radulescu }; 768a2468676SIoana Ciocoi Radulescu 769a2468676SIoana Ciocoi Radulescu dpmac8: dpmac@8 { 770a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 771a2468676SIoana Ciocoi Radulescu reg = <8>; 772a2468676SIoana Ciocoi Radulescu }; 773a2468676SIoana Ciocoi Radulescu 774a2468676SIoana Ciocoi Radulescu dpmac9: dpmac@9 { 775a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 776a2468676SIoana Ciocoi Radulescu reg = <9>; 777a2468676SIoana Ciocoi Radulescu }; 778a2468676SIoana Ciocoi Radulescu 779a2468676SIoana Ciocoi Radulescu dpmac10: dpmac@a { 780a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 781a2468676SIoana Ciocoi Radulescu reg = <0xa>; 782a2468676SIoana Ciocoi Radulescu }; 783a2468676SIoana Ciocoi Radulescu }; 784a2468676SIoana Ciocoi Radulescu }; 785f4fe3a86SBiwen Li 786f4fe3a86SBiwen Li rcpm: power-controller@1e34040 { 787f4fe3a86SBiwen Li compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; 788f4fe3a86SBiwen Li reg = <0x0 0x1e34040 0x0 0x18>; 789f4fe3a86SBiwen Li #fsl,rcpm-wakeup-cells = <6>; 790f4fe3a86SBiwen Li }; 791f4fe3a86SBiwen Li 792f4fe3a86SBiwen Li ftm_alarm0: timer@2800000 { 793f4fe3a86SBiwen Li compatible = "fsl,ls1088a-ftm-alarm"; 794f4fe3a86SBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 795f4fe3a86SBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 796f4fe3a86SBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 797f4fe3a86SBiwen Li }; 7987a5d7347SHarninder Rai }; 7997a5d7347SHarninder Rai 80051b29445SSumit Garg firmware { 80151b29445SSumit Garg optee { 80251b29445SSumit Garg compatible = "linaro,optee-tz"; 80351b29445SSumit Garg method = "smc"; 80451b29445SSumit Garg }; 80551b29445SSumit Garg }; 8067a5d7347SHarninder Rai}; 807