17a5d7347SHarninder Rai/* 27a5d7347SHarninder Rai * Device Tree Include file for NXP Layerscape-1088A family SoC. 37a5d7347SHarninder Rai * 47a5d7347SHarninder Rai * Copyright 2017 NXP 57a5d7347SHarninder Rai * 67a5d7347SHarninder Rai * Harninder Rai <harninder.rai@nxp.com> 77a5d7347SHarninder Rai * 87a5d7347SHarninder Rai * This file is dual-licensed: you can use it either under the terms 97a5d7347SHarninder Rai * of the GPLv2 or the X11 license, at your option. Note that this dual 107a5d7347SHarninder Rai * licensing only applies to this file, and not this project as a 117a5d7347SHarninder Rai * whole. 127a5d7347SHarninder Rai * 137a5d7347SHarninder Rai * a) This library is free software; you can redistribute it and/or 147a5d7347SHarninder Rai * modify it under the terms of the GNU General Public License as 157a5d7347SHarninder Rai * published by the Free Software Foundation; either version 2 of the 167a5d7347SHarninder Rai * License, or (at your option) any later version. 177a5d7347SHarninder Rai * 187a5d7347SHarninder Rai * This library is distributed in the hope that it will be useful, 197a5d7347SHarninder Rai * but WITHOUT ANY WARRANTY; without even the implied warranty of 207a5d7347SHarninder Rai * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 217a5d7347SHarninder Rai * GNU General Public License for more details. 227a5d7347SHarninder Rai * 237a5d7347SHarninder Rai * Or, alternatively, 247a5d7347SHarninder Rai * 257a5d7347SHarninder Rai * b) Permission is hereby granted, free of charge, to any person 267a5d7347SHarninder Rai * obtaining a copy of this software and associated documentation 277a5d7347SHarninder Rai * files (the "Software"), to deal in the Software without 287a5d7347SHarninder Rai * restriction, including without limitation the rights to use, 297a5d7347SHarninder Rai * copy, modify, merge, publish, distribute, sublicense, and/or 307a5d7347SHarninder Rai * sell copies of the Software, and to permit persons to whom the 317a5d7347SHarninder Rai * Software is furnished to do so, subject to the following 327a5d7347SHarninder Rai * conditions: 337a5d7347SHarninder Rai * 347a5d7347SHarninder Rai * The above copyright notice and this permission notice shall be 357a5d7347SHarninder Rai * included in all copies or substantial portions of the Software. 367a5d7347SHarninder Rai * 377a5d7347SHarninder Rai * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 387a5d7347SHarninder Rai * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 397a5d7347SHarninder Rai * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 407a5d7347SHarninder Rai * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 417a5d7347SHarninder Rai * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 427a5d7347SHarninder Rai * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 437a5d7347SHarninder Rai * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 447a5d7347SHarninder Rai * OTHER DEALINGS IN THE SOFTWARE. 457a5d7347SHarninder Rai */ 467a5d7347SHarninder Rai#include <dt-bindings/interrupt-controller/arm-gic.h> 477a5d7347SHarninder Rai 487a5d7347SHarninder Rai/ { 497a5d7347SHarninder Rai compatible = "fsl,ls1088a"; 507a5d7347SHarninder Rai interrupt-parent = <&gic>; 517a5d7347SHarninder Rai #address-cells = <2>; 527a5d7347SHarninder Rai #size-cells = <2>; 537a5d7347SHarninder Rai 547a5d7347SHarninder Rai cpus { 557a5d7347SHarninder Rai #address-cells = <1>; 567a5d7347SHarninder Rai #size-cells = <0>; 577a5d7347SHarninder Rai 587a5d7347SHarninder Rai /* We have 2 clusters having 4 Cortex-A53 cores each */ 597a5d7347SHarninder Rai cpu0: cpu@0 { 607a5d7347SHarninder Rai device_type = "cpu"; 617a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 627a5d7347SHarninder Rai reg = <0x0>; 637a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 647a5d7347SHarninder Rai }; 657a5d7347SHarninder Rai 667a5d7347SHarninder Rai cpu1: cpu@1 { 677a5d7347SHarninder Rai device_type = "cpu"; 687a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 697a5d7347SHarninder Rai reg = <0x1>; 707a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 717a5d7347SHarninder Rai }; 727a5d7347SHarninder Rai 737a5d7347SHarninder Rai cpu2: cpu@2 { 747a5d7347SHarninder Rai device_type = "cpu"; 757a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 767a5d7347SHarninder Rai reg = <0x2>; 777a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 787a5d7347SHarninder Rai }; 797a5d7347SHarninder Rai 807a5d7347SHarninder Rai cpu3: cpu@3 { 817a5d7347SHarninder Rai device_type = "cpu"; 827a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 837a5d7347SHarninder Rai reg = <0x3>; 847a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 857a5d7347SHarninder Rai }; 867a5d7347SHarninder Rai 877a5d7347SHarninder Rai cpu4: cpu@100 { 887a5d7347SHarninder Rai device_type = "cpu"; 897a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 907a5d7347SHarninder Rai reg = <0x100>; 917a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 927a5d7347SHarninder Rai }; 937a5d7347SHarninder Rai 947a5d7347SHarninder Rai cpu5: cpu@101 { 957a5d7347SHarninder Rai device_type = "cpu"; 967a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 977a5d7347SHarninder Rai reg = <0x101>; 987a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 997a5d7347SHarninder Rai }; 1007a5d7347SHarninder Rai 1017a5d7347SHarninder Rai cpu6: cpu@102 { 1027a5d7347SHarninder Rai device_type = "cpu"; 1037a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 1047a5d7347SHarninder Rai reg = <0x102>; 1057a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 1067a5d7347SHarninder Rai }; 1077a5d7347SHarninder Rai 1087a5d7347SHarninder Rai cpu7: cpu@103 { 1097a5d7347SHarninder Rai device_type = "cpu"; 1107a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 1117a5d7347SHarninder Rai reg = <0x103>; 1127a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 1137a5d7347SHarninder Rai }; 1147a5d7347SHarninder Rai }; 1157a5d7347SHarninder Rai 1167a5d7347SHarninder Rai gic: interrupt-controller@6000000 { 1177a5d7347SHarninder Rai compatible = "arm,gic-v3"; 1187a5d7347SHarninder Rai #interrupt-cells = <3>; 1197a5d7347SHarninder Rai interrupt-controller; 1207a5d7347SHarninder Rai reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1217a5d7347SHarninder Rai <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 1227a5d7347SHarninder Rai <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 1237a5d7347SHarninder Rai <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 1247a5d7347SHarninder Rai <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 1257a5d7347SHarninder Rai interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 1267a5d7347SHarninder Rai }; 1277a5d7347SHarninder Rai 1287a5d7347SHarninder Rai timer { 1297a5d7347SHarninder Rai compatible = "arm,armv8-timer"; 1307a5d7347SHarninder Rai interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 1317a5d7347SHarninder Rai <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 1327a5d7347SHarninder Rai <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 1337a5d7347SHarninder Rai <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 1347a5d7347SHarninder Rai }; 1357a5d7347SHarninder Rai 1367a5d7347SHarninder Rai sysclk: sysclk { 1377a5d7347SHarninder Rai compatible = "fixed-clock"; 1387a5d7347SHarninder Rai #clock-cells = <0>; 1397a5d7347SHarninder Rai clock-frequency = <100000000>; 1407a5d7347SHarninder Rai clock-output-names = "sysclk"; 1417a5d7347SHarninder Rai }; 1427a5d7347SHarninder Rai 1437a5d7347SHarninder Rai soc { 1447a5d7347SHarninder Rai compatible = "simple-bus"; 1457a5d7347SHarninder Rai #address-cells = <2>; 1467a5d7347SHarninder Rai #size-cells = <2>; 1477a5d7347SHarninder Rai ranges; 1487a5d7347SHarninder Rai 1497a5d7347SHarninder Rai clockgen: clocking@1300000 { 1507a5d7347SHarninder Rai compatible = "fsl,ls1088a-clockgen"; 1517a5d7347SHarninder Rai reg = <0 0x1300000 0 0xa0000>; 1527a5d7347SHarninder Rai #clock-cells = <2>; 1537a5d7347SHarninder Rai clocks = <&sysclk>; 1547a5d7347SHarninder Rai }; 1557a5d7347SHarninder Rai 1567a5d7347SHarninder Rai duart0: serial@21c0500 { 1577a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 1587a5d7347SHarninder Rai reg = <0x0 0x21c0500 0x0 0x100>; 1597a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 1607a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 1617a5d7347SHarninder Rai status = "disabled"; 1627a5d7347SHarninder Rai }; 1637a5d7347SHarninder Rai 1647a5d7347SHarninder Rai duart1: serial@21c0600 { 1657a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 1667a5d7347SHarninder Rai reg = <0x0 0x21c0600 0x0 0x100>; 1677a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 1687a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 1697a5d7347SHarninder Rai status = "disabled"; 1707a5d7347SHarninder Rai }; 1717a5d7347SHarninder Rai 1727a5d7347SHarninder Rai gpio0: gpio@2300000 { 1737a5d7347SHarninder Rai compatible = "fsl,qoriq-gpio"; 1747a5d7347SHarninder Rai reg = <0x0 0x2300000 0x0 0x10000>; 1757a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 1767a5d7347SHarninder Rai gpio-controller; 1777a5d7347SHarninder Rai #gpio-cells = <2>; 1787a5d7347SHarninder Rai interrupt-controller; 1797a5d7347SHarninder Rai #interrupt-cells = <2>; 1807a5d7347SHarninder Rai }; 1817a5d7347SHarninder Rai 1827a5d7347SHarninder Rai gpio1: gpio@2310000 { 1837a5d7347SHarninder Rai compatible = "fsl,qoriq-gpio"; 1847a5d7347SHarninder Rai reg = <0x0 0x2310000 0x0 0x10000>; 1857a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 1867a5d7347SHarninder Rai gpio-controller; 1877a5d7347SHarninder Rai #gpio-cells = <2>; 1887a5d7347SHarninder Rai interrupt-controller; 1897a5d7347SHarninder Rai #interrupt-cells = <2>; 1907a5d7347SHarninder Rai }; 1917a5d7347SHarninder Rai 1927a5d7347SHarninder Rai gpio2: gpio@2320000 { 1937a5d7347SHarninder Rai compatible = "fsl,qoriq-gpio"; 1947a5d7347SHarninder Rai reg = <0x0 0x2320000 0x0 0x10000>; 1957a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 1967a5d7347SHarninder Rai gpio-controller; 1977a5d7347SHarninder Rai #gpio-cells = <2>; 1987a5d7347SHarninder Rai interrupt-controller; 1997a5d7347SHarninder Rai #interrupt-cells = <2>; 2007a5d7347SHarninder Rai }; 2017a5d7347SHarninder Rai 2027a5d7347SHarninder Rai gpio3: gpio@2330000 { 2037a5d7347SHarninder Rai compatible = "fsl,qoriq-gpio"; 2047a5d7347SHarninder Rai reg = <0x0 0x2330000 0x0 0x10000>; 2057a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 2067a5d7347SHarninder Rai gpio-controller; 2077a5d7347SHarninder Rai #gpio-cells = <2>; 2087a5d7347SHarninder Rai interrupt-controller; 2097a5d7347SHarninder Rai #interrupt-cells = <2>; 2107a5d7347SHarninder Rai }; 2117a5d7347SHarninder Rai 2127a5d7347SHarninder Rai ifc: ifc@2240000 { 2137a5d7347SHarninder Rai compatible = "fsl,ifc", "simple-bus"; 2147a5d7347SHarninder Rai reg = <0x0 0x2240000 0x0 0x20000>; 2157a5d7347SHarninder Rai interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 2167a5d7347SHarninder Rai little-endian; 2177a5d7347SHarninder Rai #address-cells = <2>; 2187a5d7347SHarninder Rai #size-cells = <1>; 2197a5d7347SHarninder Rai status = "disabled"; 2207a5d7347SHarninder Rai }; 2217a5d7347SHarninder Rai 2227a5d7347SHarninder Rai i2c0: i2c@2000000 { 2237a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 2247a5d7347SHarninder Rai #address-cells = <1>; 2257a5d7347SHarninder Rai #size-cells = <0>; 2267a5d7347SHarninder Rai reg = <0x0 0x2000000 0x0 0x10000>; 2277a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 2287a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2297a5d7347SHarninder Rai status = "disabled"; 2307a5d7347SHarninder Rai }; 2317a5d7347SHarninder Rai 2327a5d7347SHarninder Rai i2c1: i2c@2010000 { 2337a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 2347a5d7347SHarninder Rai #address-cells = <1>; 2357a5d7347SHarninder Rai #size-cells = <0>; 2367a5d7347SHarninder Rai reg = <0x0 0x2010000 0x0 0x10000>; 2377a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 2387a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2397a5d7347SHarninder Rai status = "disabled"; 2407a5d7347SHarninder Rai }; 2417a5d7347SHarninder Rai 2427a5d7347SHarninder Rai i2c2: i2c@2020000 { 2437a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 2447a5d7347SHarninder Rai #address-cells = <1>; 2457a5d7347SHarninder Rai #size-cells = <0>; 2467a5d7347SHarninder Rai reg = <0x0 0x2020000 0x0 0x10000>; 2477a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 2487a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2497a5d7347SHarninder Rai status = "disabled"; 2507a5d7347SHarninder Rai }; 2517a5d7347SHarninder Rai 2527a5d7347SHarninder Rai i2c3: i2c@2030000 { 2537a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 2547a5d7347SHarninder Rai #address-cells = <1>; 2557a5d7347SHarninder Rai #size-cells = <0>; 2567a5d7347SHarninder Rai reg = <0x0 0x2030000 0x0 0x10000>; 2577a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 2587a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2597a5d7347SHarninder Rai status = "disabled"; 2607a5d7347SHarninder Rai }; 2617a5d7347SHarninder Rai 262e56ae178SYangbo Lu esdhc: esdhc@2140000 { 263e56ae178SYangbo Lu compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 264e56ae178SYangbo Lu reg = <0x0 0x2140000 0x0 0x10000>; 265e56ae178SYangbo Lu interrupts = <0 28 0x4>; /* Level high type */ 266e56ae178SYangbo Lu clock-frequency = <0>; 267e56ae178SYangbo Lu voltage-ranges = <1800 1800 3300 3300>; 268e56ae178SYangbo Lu sdhci,auto-cmd12; 269e56ae178SYangbo Lu little-endian; 270e56ae178SYangbo Lu bus-width = <4>; 271e56ae178SYangbo Lu status = "disabled"; 272e56ae178SYangbo Lu }; 273e56ae178SYangbo Lu 2747a5d7347SHarninder Rai sata: sata@3200000 { 2757a5d7347SHarninder Rai compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci"; 27683d0c697SYuantian Tang reg = <0x0 0x3200000 0x0 0x10000>, 27783d0c697SYuantian Tang <0x0 0x20140520 0x0 0x4>; 27883d0c697SYuantian Tang reg-names = "ahci", "sata-ecc"; 2797a5d7347SHarninder Rai interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 2807a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 28183d0c697SYuantian Tang dma-coherent; 2827a5d7347SHarninder Rai status = "disabled"; 2837a5d7347SHarninder Rai }; 2847a5d7347SHarninder Rai }; 2857a5d7347SHarninder Rai 2867a5d7347SHarninder Rai}; 287