17a2aeb91SLi Yang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 27a5d7347SHarninder Rai/* 37a5d7347SHarninder Rai * Device Tree Include file for NXP Layerscape-1088A family SoC. 47a5d7347SHarninder Rai * 57a5d7347SHarninder Rai * Copyright 2017 NXP 67a5d7347SHarninder Rai * 77a5d7347SHarninder Rai * Harninder Rai <harninder.rai@nxp.com> 87a5d7347SHarninder Rai * 97a5d7347SHarninder Rai */ 107a5d7347SHarninder Rai#include <dt-bindings/interrupt-controller/arm-gic.h> 11e4990b44SYuantian Tang#include <dt-bindings/thermal/thermal.h> 127a5d7347SHarninder Rai 137a5d7347SHarninder Rai/ { 147a5d7347SHarninder Rai compatible = "fsl,ls1088a"; 157a5d7347SHarninder Rai interrupt-parent = <&gic>; 167a5d7347SHarninder Rai #address-cells = <2>; 177a5d7347SHarninder Rai #size-cells = <2>; 187a5d7347SHarninder Rai 191e09dec9SHoria Geantă aliases { 201e09dec9SHoria Geantă crypto = &crypto; 211e09dec9SHoria Geantă }; 221e09dec9SHoria Geantă 237a5d7347SHarninder Rai cpus { 247a5d7347SHarninder Rai #address-cells = <1>; 257a5d7347SHarninder Rai #size-cells = <0>; 267a5d7347SHarninder Rai 277a5d7347SHarninder Rai /* We have 2 clusters having 4 Cortex-A53 cores each */ 287a5d7347SHarninder Rai cpu0: cpu@0 { 297a5d7347SHarninder Rai device_type = "cpu"; 307a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 317a5d7347SHarninder Rai reg = <0x0>; 327a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 335334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 34e4990b44SYuantian Tang #cooling-cells = <2>; 357a5d7347SHarninder Rai }; 367a5d7347SHarninder Rai 377a5d7347SHarninder Rai cpu1: cpu@1 { 387a5d7347SHarninder Rai device_type = "cpu"; 397a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 407a5d7347SHarninder Rai reg = <0x1>; 417a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 425334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 43346f5976SViresh Kumar #cooling-cells = <2>; 447a5d7347SHarninder Rai }; 457a5d7347SHarninder Rai 467a5d7347SHarninder Rai cpu2: cpu@2 { 477a5d7347SHarninder Rai device_type = "cpu"; 487a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 497a5d7347SHarninder Rai reg = <0x2>; 507a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 515334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 52346f5976SViresh Kumar #cooling-cells = <2>; 537a5d7347SHarninder Rai }; 547a5d7347SHarninder Rai 557a5d7347SHarninder Rai cpu3: cpu@3 { 567a5d7347SHarninder Rai device_type = "cpu"; 577a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 587a5d7347SHarninder Rai reg = <0x3>; 597a5d7347SHarninder Rai clocks = <&clockgen 1 0>; 605334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 61346f5976SViresh Kumar #cooling-cells = <2>; 627a5d7347SHarninder Rai }; 637a5d7347SHarninder Rai 647a5d7347SHarninder Rai cpu4: cpu@100 { 657a5d7347SHarninder Rai device_type = "cpu"; 667a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 677a5d7347SHarninder Rai reg = <0x100>; 687a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 695334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 70e4990b44SYuantian Tang #cooling-cells = <2>; 717a5d7347SHarninder Rai }; 727a5d7347SHarninder Rai 737a5d7347SHarninder Rai cpu5: cpu@101 { 747a5d7347SHarninder Rai device_type = "cpu"; 757a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 767a5d7347SHarninder Rai reg = <0x101>; 777a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 785334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 79346f5976SViresh Kumar #cooling-cells = <2>; 807a5d7347SHarninder Rai }; 817a5d7347SHarninder Rai 827a5d7347SHarninder Rai cpu6: cpu@102 { 837a5d7347SHarninder Rai device_type = "cpu"; 847a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 857a5d7347SHarninder Rai reg = <0x102>; 867a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 875334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 88346f5976SViresh Kumar #cooling-cells = <2>; 897a5d7347SHarninder Rai }; 907a5d7347SHarninder Rai 917a5d7347SHarninder Rai cpu7: cpu@103 { 927a5d7347SHarninder Rai device_type = "cpu"; 937a5d7347SHarninder Rai compatible = "arm,cortex-a53"; 947a5d7347SHarninder Rai reg = <0x103>; 957a5d7347SHarninder Rai clocks = <&clockgen 1 1>; 965334e1a2SYuantian Tang cpu-idle-states = <&CPU_PH20>; 97346f5976SViresh Kumar #cooling-cells = <2>; 985334e1a2SYuantian Tang }; 995334e1a2SYuantian Tang 1005334e1a2SYuantian Tang CPU_PH20: cpu-ph20 { 1015334e1a2SYuantian Tang compatible = "arm,idle-state"; 1025334e1a2SYuantian Tang idle-state-name = "PH20"; 10369ea29b0SYuantian Tang arm,psci-suspend-param = <0x0>; 1045334e1a2SYuantian Tang entry-latency-us = <1000>; 1055334e1a2SYuantian Tang exit-latency-us = <1000>; 1065334e1a2SYuantian Tang min-residency-us = <3000>; 1077a5d7347SHarninder Rai }; 1087a5d7347SHarninder Rai }; 1097a5d7347SHarninder Rai 1107a5d7347SHarninder Rai gic: interrupt-controller@6000000 { 1117a5d7347SHarninder Rai compatible = "arm,gic-v3"; 1127a5d7347SHarninder Rai #interrupt-cells = <3>; 1137a5d7347SHarninder Rai interrupt-controller; 1147a5d7347SHarninder Rai reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1157a5d7347SHarninder Rai <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 1167a5d7347SHarninder Rai <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 1177a5d7347SHarninder Rai <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 1187a5d7347SHarninder Rai <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 1197a5d7347SHarninder Rai interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 120a3bbf4c5SHou Zhiqiang #address-cells = <2>; 121a3bbf4c5SHou Zhiqiang #size-cells = <2>; 122a3bbf4c5SHou Zhiqiang ranges; 123a3bbf4c5SHou Zhiqiang 124a3bbf4c5SHou Zhiqiang its: gic-its@6020000 { 125a3bbf4c5SHou Zhiqiang compatible = "arm,gic-v3-its"; 126a3bbf4c5SHou Zhiqiang msi-controller; 127a3bbf4c5SHou Zhiqiang reg = <0x0 0x6020000 0 0x20000>; 128a3bbf4c5SHou Zhiqiang }; 1297a5d7347SHarninder Rai }; 1307a5d7347SHarninder Rai 13185530a7aSFabio Estevam thermal-zones { 13285530a7aSFabio Estevam cpu_thermal: cpu-thermal { 13385530a7aSFabio Estevam polling-delay-passive = <1000>; 13485530a7aSFabio Estevam polling-delay = <5000>; 13585530a7aSFabio Estevam thermal-sensors = <&tmu 0>; 13685530a7aSFabio Estevam 13785530a7aSFabio Estevam trips { 13885530a7aSFabio Estevam cpu_alert: cpu-alert { 13985530a7aSFabio Estevam temperature = <85000>; 14085530a7aSFabio Estevam hysteresis = <2000>; 14185530a7aSFabio Estevam type = "passive"; 14285530a7aSFabio Estevam }; 14385530a7aSFabio Estevam 14485530a7aSFabio Estevam cpu_crit: cpu-crit { 14585530a7aSFabio Estevam temperature = <95000>; 14685530a7aSFabio Estevam hysteresis = <2000>; 14785530a7aSFabio Estevam type = "critical"; 14885530a7aSFabio Estevam }; 14985530a7aSFabio Estevam }; 15085530a7aSFabio Estevam 15185530a7aSFabio Estevam cooling-maps { 15285530a7aSFabio Estevam map0 { 15385530a7aSFabio Estevam trip = <&cpu_alert>; 15485530a7aSFabio Estevam cooling-device = 155c9a1f243SViresh Kumar <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 156c9a1f243SViresh Kumar <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 157c9a1f243SViresh Kumar <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 158c9a1f243SViresh Kumar <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159c9a1f243SViresh Kumar <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160c9a1f243SViresh Kumar <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161c9a1f243SViresh Kumar <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162c9a1f243SViresh Kumar <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 16385530a7aSFabio Estevam }; 16485530a7aSFabio Estevam }; 16585530a7aSFabio Estevam }; 16685530a7aSFabio Estevam }; 16785530a7aSFabio Estevam 1687a5d7347SHarninder Rai timer { 1697a5d7347SHarninder Rai compatible = "arm,armv8-timer"; 1707a5d7347SHarninder Rai interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 1717a5d7347SHarninder Rai <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 1727a5d7347SHarninder Rai <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 1737a5d7347SHarninder Rai <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 1747a5d7347SHarninder Rai }; 1757a5d7347SHarninder Rai 1765334e1a2SYuantian Tang psci { 1775334e1a2SYuantian Tang compatible = "arm,psci-0.2"; 1785334e1a2SYuantian Tang method = "smc"; 1795334e1a2SYuantian Tang }; 1805334e1a2SYuantian Tang 1817a5d7347SHarninder Rai sysclk: sysclk { 1827a5d7347SHarninder Rai compatible = "fixed-clock"; 1837a5d7347SHarninder Rai #clock-cells = <0>; 1847a5d7347SHarninder Rai clock-frequency = <100000000>; 1857a5d7347SHarninder Rai clock-output-names = "sysclk"; 1867a5d7347SHarninder Rai }; 1877a5d7347SHarninder Rai 1887a5d7347SHarninder Rai soc { 1897a5d7347SHarninder Rai compatible = "simple-bus"; 1907a5d7347SHarninder Rai #address-cells = <2>; 1917a5d7347SHarninder Rai #size-cells = <2>; 1927a5d7347SHarninder Rai ranges; 193d9a71ef0SIoana Ciocoi Radulescu dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 1947a5d7347SHarninder Rai 1957a5d7347SHarninder Rai clockgen: clocking@1300000 { 1967a5d7347SHarninder Rai compatible = "fsl,ls1088a-clockgen"; 1977a5d7347SHarninder Rai reg = <0 0x1300000 0 0xa0000>; 1987a5d7347SHarninder Rai #clock-cells = <2>; 1997a5d7347SHarninder Rai clocks = <&sysclk>; 2007a5d7347SHarninder Rai }; 2017a5d7347SHarninder Rai 20288b64bb1SAshish Kumar dcfg: dcfg@1e00000 { 20388b64bb1SAshish Kumar compatible = "fsl,ls1088a-dcfg", "syscon"; 20488b64bb1SAshish Kumar reg = <0x0 0x1e00000 0x0 0x10000>; 20588b64bb1SAshish Kumar little-endian; 20688b64bb1SAshish Kumar }; 20788b64bb1SAshish Kumar 208e4990b44SYuantian Tang tmu: tmu@1f80000 { 209e4990b44SYuantian Tang compatible = "fsl,qoriq-tmu"; 210e4990b44SYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 211e4990b44SYuantian Tang interrupts = <0 23 0x4>; 212e4990b44SYuantian Tang fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 213e4990b44SYuantian Tang fsl,tmu-calibration = 214e4990b44SYuantian Tang /* Calibration data group 1 */ 215e4990b44SYuantian Tang <0x00000000 0x00000026 216e4990b44SYuantian Tang 0x00000001 0x0000002d 217e4990b44SYuantian Tang 0x00000002 0x00000032 218e4990b44SYuantian Tang 0x00000003 0x00000039 219e4990b44SYuantian Tang 0x00000004 0x0000003f 220e4990b44SYuantian Tang 0x00000005 0x00000046 221e4990b44SYuantian Tang 0x00000006 0x0000004d 222e4990b44SYuantian Tang 0x00000007 0x00000054 223e4990b44SYuantian Tang 0x00000008 0x0000005a 224e4990b44SYuantian Tang 0x00000009 0x00000061 225e4990b44SYuantian Tang 0x0000000a 0x0000006a 226e4990b44SYuantian Tang 0x0000000b 0x00000071 227e4990b44SYuantian Tang /* Calibration data group 2 */ 228e4990b44SYuantian Tang 0x00010000 0x00000025 229e4990b44SYuantian Tang 0x00010001 0x0000002c 230e4990b44SYuantian Tang 0x00010002 0x00000035 231e4990b44SYuantian Tang 0x00010003 0x0000003d 232e4990b44SYuantian Tang 0x00010004 0x00000045 233e4990b44SYuantian Tang 0x00010005 0x0000004e 234e4990b44SYuantian Tang 0x00010006 0x00000057 235e4990b44SYuantian Tang 0x00010007 0x00000061 236e4990b44SYuantian Tang 0x00010008 0x0000006b 237e4990b44SYuantian Tang 0x00010009 0x00000076 238e4990b44SYuantian Tang /* Calibration data group 3 */ 239e4990b44SYuantian Tang 0x00020000 0x00000029 240e4990b44SYuantian Tang 0x00020001 0x00000033 241e4990b44SYuantian Tang 0x00020002 0x0000003d 242e4990b44SYuantian Tang 0x00020003 0x00000049 243e4990b44SYuantian Tang 0x00020004 0x00000056 244e4990b44SYuantian Tang 0x00020005 0x00000061 245e4990b44SYuantian Tang 0x00020006 0x0000006d 246e4990b44SYuantian Tang /* Calibration data group 4 */ 247e4990b44SYuantian Tang 0x00030000 0x00000021 248e4990b44SYuantian Tang 0x00030001 0x0000002a 249e4990b44SYuantian Tang 0x00030002 0x0000003c 250e4990b44SYuantian Tang 0x00030003 0x0000004e>; 251e4990b44SYuantian Tang little-endian; 252e4990b44SYuantian Tang #thermal-sensor-cells = <1>; 253e4990b44SYuantian Tang }; 254e4990b44SYuantian Tang 2557a5d7347SHarninder Rai duart0: serial@21c0500 { 2567a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 2577a5d7347SHarninder Rai reg = <0x0 0x21c0500 0x0 0x100>; 2587a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2597a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 2607a5d7347SHarninder Rai status = "disabled"; 2617a5d7347SHarninder Rai }; 2627a5d7347SHarninder Rai 2637a5d7347SHarninder Rai duart1: serial@21c0600 { 2647a5d7347SHarninder Rai compatible = "fsl,ns16550", "ns16550a"; 2657a5d7347SHarninder Rai reg = <0x0 0x21c0600 0x0 0x100>; 2667a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 2677a5d7347SHarninder Rai interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 2687a5d7347SHarninder Rai status = "disabled"; 2697a5d7347SHarninder Rai }; 2707a5d7347SHarninder Rai 2717a5d7347SHarninder Rai gpio0: gpio@2300000 { 2727a5d7347SHarninder Rai compatible = "fsl,qoriq-gpio"; 2737a5d7347SHarninder Rai reg = <0x0 0x2300000 0x0 0x10000>; 2747a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 2757a5d7347SHarninder Rai gpio-controller; 2767a5d7347SHarninder Rai #gpio-cells = <2>; 2777a5d7347SHarninder Rai interrupt-controller; 2787a5d7347SHarninder Rai #interrupt-cells = <2>; 2797a5d7347SHarninder Rai }; 2807a5d7347SHarninder Rai 2817a5d7347SHarninder Rai gpio1: gpio@2310000 { 2827a5d7347SHarninder Rai compatible = "fsl,qoriq-gpio"; 2837a5d7347SHarninder Rai reg = <0x0 0x2310000 0x0 0x10000>; 2847a5d7347SHarninder Rai interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 2857a5d7347SHarninder Rai gpio-controller; 2867a5d7347SHarninder Rai #gpio-cells = <2>; 2877a5d7347SHarninder Rai interrupt-controller; 2887a5d7347SHarninder Rai #interrupt-cells = <2>; 2897a5d7347SHarninder Rai }; 2907a5d7347SHarninder Rai 2917a5d7347SHarninder Rai gpio2: gpio@2320000 { 2927a5d7347SHarninder Rai compatible = "fsl,qoriq-gpio"; 2937a5d7347SHarninder Rai reg = <0x0 0x2320000 0x0 0x10000>; 2947a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 2957a5d7347SHarninder Rai gpio-controller; 2967a5d7347SHarninder Rai #gpio-cells = <2>; 2977a5d7347SHarninder Rai interrupt-controller; 2987a5d7347SHarninder Rai #interrupt-cells = <2>; 2997a5d7347SHarninder Rai }; 3007a5d7347SHarninder Rai 3017a5d7347SHarninder Rai gpio3: gpio@2330000 { 3027a5d7347SHarninder Rai compatible = "fsl,qoriq-gpio"; 3037a5d7347SHarninder Rai reg = <0x0 0x2330000 0x0 0x10000>; 3047a5d7347SHarninder Rai interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 3057a5d7347SHarninder Rai gpio-controller; 3067a5d7347SHarninder Rai #gpio-cells = <2>; 3077a5d7347SHarninder Rai interrupt-controller; 3087a5d7347SHarninder Rai #interrupt-cells = <2>; 3097a5d7347SHarninder Rai }; 3107a5d7347SHarninder Rai 3117a5d7347SHarninder Rai ifc: ifc@2240000 { 3127a5d7347SHarninder Rai compatible = "fsl,ifc", "simple-bus"; 3137a5d7347SHarninder Rai reg = <0x0 0x2240000 0x0 0x20000>; 3147a5d7347SHarninder Rai interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 3157a5d7347SHarninder Rai little-endian; 3167a5d7347SHarninder Rai #address-cells = <2>; 3177a5d7347SHarninder Rai #size-cells = <1>; 3187a5d7347SHarninder Rai status = "disabled"; 3197a5d7347SHarninder Rai }; 3207a5d7347SHarninder Rai 3217a5d7347SHarninder Rai i2c0: i2c@2000000 { 3227a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3237a5d7347SHarninder Rai #address-cells = <1>; 3247a5d7347SHarninder Rai #size-cells = <0>; 3257a5d7347SHarninder Rai reg = <0x0 0x2000000 0x0 0x10000>; 3267a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 3277a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 3287a5d7347SHarninder Rai status = "disabled"; 3297a5d7347SHarninder Rai }; 3307a5d7347SHarninder Rai 3317a5d7347SHarninder Rai i2c1: i2c@2010000 { 3327a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3337a5d7347SHarninder Rai #address-cells = <1>; 3347a5d7347SHarninder Rai #size-cells = <0>; 3357a5d7347SHarninder Rai reg = <0x0 0x2010000 0x0 0x10000>; 3367a5d7347SHarninder Rai interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 3377a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 3387a5d7347SHarninder Rai status = "disabled"; 3397a5d7347SHarninder Rai }; 3407a5d7347SHarninder Rai 3417a5d7347SHarninder Rai i2c2: i2c@2020000 { 3427a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3437a5d7347SHarninder Rai #address-cells = <1>; 3447a5d7347SHarninder Rai #size-cells = <0>; 3457a5d7347SHarninder Rai reg = <0x0 0x2020000 0x0 0x10000>; 3467a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 3477a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 3487a5d7347SHarninder Rai status = "disabled"; 3497a5d7347SHarninder Rai }; 3507a5d7347SHarninder Rai 3517a5d7347SHarninder Rai i2c3: i2c@2030000 { 3527a5d7347SHarninder Rai compatible = "fsl,vf610-i2c"; 3537a5d7347SHarninder Rai #address-cells = <1>; 3547a5d7347SHarninder Rai #size-cells = <0>; 3557a5d7347SHarninder Rai reg = <0x0 0x2030000 0x0 0x10000>; 3567a5d7347SHarninder Rai interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 3577a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 3587a5d7347SHarninder Rai status = "disabled"; 3597a5d7347SHarninder Rai }; 3607a5d7347SHarninder Rai 361e56ae178SYangbo Lu esdhc: esdhc@2140000 { 362e56ae178SYangbo Lu compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 363e56ae178SYangbo Lu reg = <0x0 0x2140000 0x0 0x10000>; 364e56ae178SYangbo Lu interrupts = <0 28 0x4>; /* Level high type */ 365e56ae178SYangbo Lu clock-frequency = <0>; 366e56ae178SYangbo Lu voltage-ranges = <1800 1800 3300 3300>; 367e56ae178SYangbo Lu sdhci,auto-cmd12; 368e56ae178SYangbo Lu little-endian; 369e56ae178SYangbo Lu bus-width = <4>; 370e56ae178SYangbo Lu status = "disabled"; 371e56ae178SYangbo Lu }; 372e56ae178SYangbo Lu 373df063a1fSyinbo.zhu usb0: usb3@3100000 { 374df063a1fSyinbo.zhu compatible = "snps,dwc3"; 375df063a1fSyinbo.zhu reg = <0x0 0x3100000 0x0 0x10000>; 376df063a1fSyinbo.zhu interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 377df063a1fSyinbo.zhu dr_mode = "host"; 378df063a1fSyinbo.zhu snps,quirk-frame-length-adjustment = <0x20>; 379df063a1fSyinbo.zhu snps,dis_rxdet_inp3_quirk; 380df063a1fSyinbo.zhu status = "disabled"; 381df063a1fSyinbo.zhu }; 382df063a1fSyinbo.zhu 383df063a1fSyinbo.zhu usb1: usb3@3110000 { 384df063a1fSyinbo.zhu compatible = "snps,dwc3"; 385df063a1fSyinbo.zhu reg = <0x0 0x3110000 0x0 0x10000>; 386df063a1fSyinbo.zhu interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 387df063a1fSyinbo.zhu dr_mode = "host"; 388df063a1fSyinbo.zhu snps,quirk-frame-length-adjustment = <0x20>; 389df063a1fSyinbo.zhu snps,dis_rxdet_inp3_quirk; 390df063a1fSyinbo.zhu status = "disabled"; 391df063a1fSyinbo.zhu }; 392df063a1fSyinbo.zhu 3937a5d7347SHarninder Rai sata: sata@3200000 { 394375b6755SYuantian Tang compatible = "fsl,ls1088a-ahci"; 39583d0c697SYuantian Tang reg = <0x0 0x3200000 0x0 0x10000>, 396375b6755SYuantian Tang <0x7 0x100520 0x0 0x4>; 39783d0c697SYuantian Tang reg-names = "ahci", "sata-ecc"; 3987a5d7347SHarninder Rai interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 3997a5d7347SHarninder Rai clocks = <&clockgen 4 3>; 40083d0c697SYuantian Tang dma-coherent; 4017a5d7347SHarninder Rai status = "disabled"; 4027a5d7347SHarninder Rai }; 4031e09dec9SHoria Geantă 4041e09dec9SHoria Geantă crypto: crypto@8000000 { 4051e09dec9SHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 4061e09dec9SHoria Geantă fsl,sec-era = <8>; 4071e09dec9SHoria Geantă #address-cells = <1>; 4081e09dec9SHoria Geantă #size-cells = <1>; 4091e09dec9SHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 4101e09dec9SHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 4111e09dec9SHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 4121e09dec9SHoria Geantă dma-coherent; 4131e09dec9SHoria Geantă 4141e09dec9SHoria Geantă sec_jr0: jr@10000 { 4151e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4161e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4171e09dec9SHoria Geantă reg = <0x10000 0x10000>; 4181e09dec9SHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4191e09dec9SHoria Geantă }; 4201e09dec9SHoria Geantă 4211e09dec9SHoria Geantă sec_jr1: jr@20000 { 4221e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4231e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4241e09dec9SHoria Geantă reg = <0x20000 0x10000>; 4251e09dec9SHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 4261e09dec9SHoria Geantă }; 4271e09dec9SHoria Geantă 4281e09dec9SHoria Geantă sec_jr2: jr@30000 { 4291e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4301e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4311e09dec9SHoria Geantă reg = <0x30000 0x10000>; 4321e09dec9SHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 4331e09dec9SHoria Geantă }; 4341e09dec9SHoria Geantă 4351e09dec9SHoria Geantă sec_jr3: jr@40000 { 4361e09dec9SHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4371e09dec9SHoria Geantă "fsl,sec-v4.0-job-ring"; 4381e09dec9SHoria Geantă reg = <0x40000 0x10000>; 4391e09dec9SHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 4401e09dec9SHoria Geantă }; 4411e09dec9SHoria Geantă }; 442647911c8SHou Zhiqiang 443647911c8SHou Zhiqiang pcie@3400000 { 4441fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 445647911c8SHou Zhiqiang reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 446647911c8SHou Zhiqiang 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 447647911c8SHou Zhiqiang reg-names = "regs", "config"; 448647911c8SHou Zhiqiang interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 449647911c8SHou Zhiqiang interrupt-names = "aer"; 450647911c8SHou Zhiqiang #address-cells = <3>; 451647911c8SHou Zhiqiang #size-cells = <2>; 452647911c8SHou Zhiqiang device_type = "pci"; 453647911c8SHou Zhiqiang dma-coherent; 454647911c8SHou Zhiqiang num-lanes = <4>; 455881e90d2SHou Zhiqiang num-viewport = <256>; 456647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 457647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 458647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 459647911c8SHou Zhiqiang msi-parent = <&its>; 460647911c8SHou Zhiqiang #interrupt-cells = <1>; 461647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 462647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 463647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 464647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 465647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 466aa2aa888SBao Xiaowei status = "disabled"; 467647911c8SHou Zhiqiang }; 468647911c8SHou Zhiqiang 469647911c8SHou Zhiqiang pcie@3500000 { 4701fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 471647911c8SHou Zhiqiang reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 472647911c8SHou Zhiqiang 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 473647911c8SHou Zhiqiang reg-names = "regs", "config"; 474647911c8SHou Zhiqiang interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 475647911c8SHou Zhiqiang interrupt-names = "aer"; 476647911c8SHou Zhiqiang #address-cells = <3>; 477647911c8SHou Zhiqiang #size-cells = <2>; 478647911c8SHou Zhiqiang device_type = "pci"; 479647911c8SHou Zhiqiang dma-coherent; 480647911c8SHou Zhiqiang num-lanes = <4>; 481881e90d2SHou Zhiqiang num-viewport = <6>; 482647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 483647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 484647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 485647911c8SHou Zhiqiang msi-parent = <&its>; 486647911c8SHou Zhiqiang #interrupt-cells = <1>; 487647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 488647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 489647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 490647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 491647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 492aa2aa888SBao Xiaowei status = "disabled"; 493647911c8SHou Zhiqiang }; 494647911c8SHou Zhiqiang 495647911c8SHou Zhiqiang pcie@3600000 { 4961fa35bc0SHou Zhiqiang compatible = "fsl,ls1088a-pcie"; 497647911c8SHou Zhiqiang reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 498647911c8SHou Zhiqiang 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 499647911c8SHou Zhiqiang reg-names = "regs", "config"; 500647911c8SHou Zhiqiang interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 501647911c8SHou Zhiqiang interrupt-names = "aer"; 502647911c8SHou Zhiqiang #address-cells = <3>; 503647911c8SHou Zhiqiang #size-cells = <2>; 504647911c8SHou Zhiqiang device_type = "pci"; 505647911c8SHou Zhiqiang dma-coherent; 506647911c8SHou Zhiqiang num-lanes = <8>; 507881e90d2SHou Zhiqiang num-viewport = <6>; 508647911c8SHou Zhiqiang bus-range = <0x0 0xff>; 509647911c8SHou Zhiqiang ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 510647911c8SHou Zhiqiang 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 511647911c8SHou Zhiqiang msi-parent = <&its>; 512647911c8SHou Zhiqiang #interrupt-cells = <1>; 513647911c8SHou Zhiqiang interrupt-map-mask = <0 0 0 7>; 514647911c8SHou Zhiqiang interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 515647911c8SHou Zhiqiang <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 516647911c8SHou Zhiqiang <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 517647911c8SHou Zhiqiang <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 518aa2aa888SBao Xiaowei status = "disabled"; 519647911c8SHou Zhiqiang }; 520cc223282SZhang Ying-22455 52183c58a55SNipun Gupta smmu: iommu@5000000 { 52283c58a55SNipun Gupta compatible = "arm,mmu-500"; 52383c58a55SNipun Gupta reg = <0 0x5000000 0 0x800000>; 52483c58a55SNipun Gupta #iommu-cells = <1>; 52583c58a55SNipun Gupta stream-match-mask = <0x7C00>; 52683c58a55SNipun Gupta #global-interrupts = <12>; 52783c58a55SNipun Gupta // global secure fault 52883c58a55SNipun Gupta interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 52983c58a55SNipun Gupta // combined secure 53083c58a55SNipun Gupta <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 53183c58a55SNipun Gupta // global non-secure fault 53283c58a55SNipun Gupta <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 53383c58a55SNipun Gupta // combined non-secure 53483c58a55SNipun Gupta <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 53583c58a55SNipun Gupta // performance counter interrupts 0-7 53683c58a55SNipun Gupta <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 53783c58a55SNipun Gupta <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 53883c58a55SNipun Gupta <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 53983c58a55SNipun Gupta <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 54083c58a55SNipun Gupta <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 54183c58a55SNipun Gupta <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 54283c58a55SNipun Gupta <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 54383c58a55SNipun Gupta <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 54483c58a55SNipun Gupta // per context interrupt, 64 interrupts 54583c58a55SNipun Gupta <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 54683c58a55SNipun Gupta <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 54783c58a55SNipun Gupta <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 54883c58a55SNipun Gupta <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 54983c58a55SNipun Gupta <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 55083c58a55SNipun Gupta <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 55183c58a55SNipun Gupta <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 55283c58a55SNipun Gupta <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 55383c58a55SNipun Gupta <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 55483c58a55SNipun Gupta <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 55583c58a55SNipun Gupta <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 55683c58a55SNipun Gupta <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 55783c58a55SNipun Gupta <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 55883c58a55SNipun Gupta <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 55983c58a55SNipun Gupta <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 56083c58a55SNipun Gupta <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 56183c58a55SNipun Gupta <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 56283c58a55SNipun Gupta <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 56383c58a55SNipun Gupta <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 56483c58a55SNipun Gupta <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 56583c58a55SNipun Gupta <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 56683c58a55SNipun Gupta <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 56783c58a55SNipun Gupta <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 56883c58a55SNipun Gupta <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 56983c58a55SNipun Gupta <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 57083c58a55SNipun Gupta <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 57183c58a55SNipun Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 57283c58a55SNipun Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 57383c58a55SNipun Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 57483c58a55SNipun Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 57583c58a55SNipun Gupta <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 57683c58a55SNipun Gupta <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 57783c58a55SNipun Gupta <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 57883c58a55SNipun Gupta <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 57983c58a55SNipun Gupta <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 58083c58a55SNipun Gupta <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 58183c58a55SNipun Gupta <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 58283c58a55SNipun Gupta <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 58383c58a55SNipun Gupta <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 58483c58a55SNipun Gupta <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 58583c58a55SNipun Gupta <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 58683c58a55SNipun Gupta <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 58783c58a55SNipun Gupta <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 58883c58a55SNipun Gupta <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 58983c58a55SNipun Gupta <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 59083c58a55SNipun Gupta <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 59183c58a55SNipun Gupta <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 59283c58a55SNipun Gupta <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 59383c58a55SNipun Gupta <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 59483c58a55SNipun Gupta <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 59583c58a55SNipun Gupta <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 59683c58a55SNipun Gupta <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 59783c58a55SNipun Gupta <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 59883c58a55SNipun Gupta <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 59983c58a55SNipun Gupta <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 60083c58a55SNipun Gupta <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 60183c58a55SNipun Gupta <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 60283c58a55SNipun Gupta <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 60383c58a55SNipun Gupta <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 60483c58a55SNipun Gupta <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 60583c58a55SNipun Gupta <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 60683c58a55SNipun Gupta <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 60783c58a55SNipun Gupta <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 60883c58a55SNipun Gupta <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 60983c58a55SNipun Gupta }; 61083c58a55SNipun Gupta 611cc223282SZhang Ying-22455 cluster1_core0_watchdog: wdt@c000000 { 612cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 613cc223282SZhang Ying-22455 reg = <0x0 0xc000000 0x0 0x1000>; 614cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 615cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 616cc223282SZhang Ying-22455 }; 617cc223282SZhang Ying-22455 618cc223282SZhang Ying-22455 cluster1_core1_watchdog: wdt@c010000 { 619cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 620cc223282SZhang Ying-22455 reg = <0x0 0xc010000 0x0 0x1000>; 621cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 622cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 623cc223282SZhang Ying-22455 }; 624cc223282SZhang Ying-22455 625cc223282SZhang Ying-22455 cluster1_core2_watchdog: wdt@c020000 { 626cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 627cc223282SZhang Ying-22455 reg = <0x0 0xc020000 0x0 0x1000>; 628cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 629cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 630cc223282SZhang Ying-22455 }; 631cc223282SZhang Ying-22455 632cc223282SZhang Ying-22455 cluster1_core3_watchdog: wdt@c030000 { 633cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 634cc223282SZhang Ying-22455 reg = <0x0 0xc030000 0x0 0x1000>; 635cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 636cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 637cc223282SZhang Ying-22455 }; 638cc223282SZhang Ying-22455 639cc223282SZhang Ying-22455 cluster2_core0_watchdog: wdt@c100000 { 640cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 641cc223282SZhang Ying-22455 reg = <0x0 0xc100000 0x0 0x1000>; 642cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 643cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 644cc223282SZhang Ying-22455 }; 645cc223282SZhang Ying-22455 646cc223282SZhang Ying-22455 cluster2_core1_watchdog: wdt@c110000 { 647cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 648cc223282SZhang Ying-22455 reg = <0x0 0xc110000 0x0 0x1000>; 649cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 650cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 651cc223282SZhang Ying-22455 }; 652cc223282SZhang Ying-22455 653cc223282SZhang Ying-22455 cluster2_core2_watchdog: wdt@c120000 { 654cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 655cc223282SZhang Ying-22455 reg = <0x0 0xc120000 0x0 0x1000>; 656cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 657cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 658cc223282SZhang Ying-22455 }; 659cc223282SZhang Ying-22455 660cc223282SZhang Ying-22455 cluster2_core3_watchdog: wdt@c130000 { 661cc223282SZhang Ying-22455 compatible = "arm,sp805-wdt", "arm,primecell"; 662cc223282SZhang Ying-22455 reg = <0x0 0xc130000 0x0 0x1000>; 663cc223282SZhang Ying-22455 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 664cc223282SZhang Ying-22455 clock-names = "apb_pclk", "wdog_clk"; 665cc223282SZhang Ying-22455 }; 666a2468676SIoana Ciocoi Radulescu 667a2468676SIoana Ciocoi Radulescu fsl_mc: fsl-mc@80c000000 { 668a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc"; 669a2468676SIoana Ciocoi Radulescu reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 670a2468676SIoana Ciocoi Radulescu <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 671a2468676SIoana Ciocoi Radulescu msi-parent = <&its>; 67283c58a55SNipun Gupta iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 673a2468676SIoana Ciocoi Radulescu #address-cells = <3>; 674a2468676SIoana Ciocoi Radulescu #size-cells = <1>; 675a2468676SIoana Ciocoi Radulescu 676a2468676SIoana Ciocoi Radulescu /* 677a2468676SIoana Ciocoi Radulescu * Region type 0x0 - MC portals 678a2468676SIoana Ciocoi Radulescu * Region type 0x1 - QBMAN portals 679a2468676SIoana Ciocoi Radulescu */ 680a2468676SIoana Ciocoi Radulescu ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 681a2468676SIoana Ciocoi Radulescu 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 682a2468676SIoana Ciocoi Radulescu 683a2468676SIoana Ciocoi Radulescu dpmacs { 684a2468676SIoana Ciocoi Radulescu #address-cells = <1>; 685a2468676SIoana Ciocoi Radulescu #size-cells = <0>; 686a2468676SIoana Ciocoi Radulescu 687a2468676SIoana Ciocoi Radulescu dpmac1: dpmac@1 { 688a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 689a2468676SIoana Ciocoi Radulescu reg = <1>; 690a2468676SIoana Ciocoi Radulescu }; 691a2468676SIoana Ciocoi Radulescu 692a2468676SIoana Ciocoi Radulescu dpmac2: dpmac@2 { 693a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 694a2468676SIoana Ciocoi Radulescu reg = <2>; 695a2468676SIoana Ciocoi Radulescu }; 696a2468676SIoana Ciocoi Radulescu 697a2468676SIoana Ciocoi Radulescu dpmac3: dpmac@3 { 698a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 699a2468676SIoana Ciocoi Radulescu reg = <3>; 700a2468676SIoana Ciocoi Radulescu }; 701a2468676SIoana Ciocoi Radulescu 702a2468676SIoana Ciocoi Radulescu dpmac4: dpmac@4 { 703a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 704a2468676SIoana Ciocoi Radulescu reg = <4>; 705a2468676SIoana Ciocoi Radulescu }; 706a2468676SIoana Ciocoi Radulescu 707a2468676SIoana Ciocoi Radulescu dpmac5: dpmac@5 { 708a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 709a2468676SIoana Ciocoi Radulescu reg = <5>; 710a2468676SIoana Ciocoi Radulescu }; 711a2468676SIoana Ciocoi Radulescu 712a2468676SIoana Ciocoi Radulescu dpmac6: dpmac@6 { 713a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 714a2468676SIoana Ciocoi Radulescu reg = <6>; 715a2468676SIoana Ciocoi Radulescu }; 716a2468676SIoana Ciocoi Radulescu 717a2468676SIoana Ciocoi Radulescu dpmac7: dpmac@7 { 718a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 719a2468676SIoana Ciocoi Radulescu reg = <7>; 720a2468676SIoana Ciocoi Radulescu }; 721a2468676SIoana Ciocoi Radulescu 722a2468676SIoana Ciocoi Radulescu dpmac8: dpmac@8 { 723a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 724a2468676SIoana Ciocoi Radulescu reg = <8>; 725a2468676SIoana Ciocoi Radulescu }; 726a2468676SIoana Ciocoi Radulescu 727a2468676SIoana Ciocoi Radulescu dpmac9: dpmac@9 { 728a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 729a2468676SIoana Ciocoi Radulescu reg = <9>; 730a2468676SIoana Ciocoi Radulescu }; 731a2468676SIoana Ciocoi Radulescu 732a2468676SIoana Ciocoi Radulescu dpmac10: dpmac@a { 733a2468676SIoana Ciocoi Radulescu compatible = "fsl,qoriq-mc-dpmac"; 734a2468676SIoana Ciocoi Radulescu reg = <0xa>; 735a2468676SIoana Ciocoi Radulescu }; 736a2468676SIoana Ciocoi Radulescu }; 737a2468676SIoana Ciocoi Radulescu }; 7387a5d7347SHarninder Rai }; 7397a5d7347SHarninder Rai 74051b29445SSumit Garg firmware { 74151b29445SSumit Garg optee { 74251b29445SSumit Garg compatible = "linaro,optee-tz"; 74351b29445SSumit Garg method = "smc"; 74451b29445SSumit Garg }; 74551b29445SSumit Garg }; 7467a5d7347SHarninder Rai}; 747